Power distribution terminal for monitoring system power supply voltage and system

Abstract

The invention provides a power distribution terminal and system for monitoring system power supply voltage, and belongs to the field of relay protection. The power distribution terminal comprises a CPU chip and an external independent first AD chip. Wherein the first AD chip comprises a data acquisition end, a data output end and a power supply end; the CPU chip is connected with the data output end and is used for acquiring the analog quantity of the power distribution network acquired by the first AD chip through the data acquisition end, and the CPU chip is also connected with the power supply end and is used for acquiring the voltage of a system power supply of the first AD chip and performing locking control based on the voltage of the system power supply; or, the first AD chip is used for monitoring the power supply voltage of the first AD chip so as to obtain the power management code, and the CPU chip is connected with the data output end and used for obtaining the power management code of the first AD chip and the analog quantity of the power distribution network collected by the data collection end and conducting locking control based on the power management code. The operation safety of the power distribution terminal and other equipment connected with the power distribution terminal can be ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of relay protection, and in particular to a power distribution terminal and a system for monitoring system power supply voltage. Background Art

[0002] The hardware part of the power distribution terminal is generally composed of an external independent AD chip and a CPU chip. The power supply voltage of most CPU chips is rated at 3.3V, and the power supply voltage of the external independent AD chip is rated at 5V or plus or minus 12V.

[0003] The external independent AD chip is used for analog quantity acquisition, and after analog-to-digital conversion, the collected data is transmitted to the CPU for use. However, due to the different power supplies of the CPU chip and the external independent AD chip, the power supply chip that powers the CPU chip usually has a large input range, stable output power, and is not easily affected by the input power supply. The power supply of the external independent AD chip usually directly uses the system power supply. When the system power supply is abnormal, the data collected by the external independent AD chip is easily affected. When there are errors in the collected data, it is easy to cause false tripping on site, which in turn has serious consequences. Summary of the invention

[0004] The embodiment of the present invention provides a power distribution terminal and system for monitoring system power supply voltage, so as to solve the problem that sampling errors occur when an external independent AD chip performs sampling at the current stage, thereby affecting the safe operation of the power distribution terminal.

[0005] In a first aspect, an embodiment of the present invention provides a power distribution terminal for monitoring system power supply voltage, comprising: a CPU chip and an external independent first AD chip; wherein the first AD chip comprises a data acquisition terminal, a data output terminal and a power supply terminal;

[0006] The CPU chip is connected to the data output terminal, and is used to obtain the power distribution network analog quantity collected by the first AD chip through the data collection terminal. At the same time, the CPU chip is also connected to the power supply terminal, and is used to obtain the voltage of the system power supply of the first AD chip and perform locking control based on the voltage of the system power supply;

[0007] Alternatively, the first AD chip is used to monitor its own power supply voltage to obtain the power management code. The CPU chip is connected to the data output end to obtain the power management code of the first AD chip and the analog quantity of the distribution network collected by the data acquisition end, and perform locking control based on the power management code.

[0008] In a possible implementation, the CPU chip includes a second AD chip;

[0009] The second AD chip is connected to the power supply terminal and is used to obtain the voltage of the system power supply of the first AD chip.

[0010] In a possible implementation, the CPU chip is specifically used for:

[0011] Determine whether the voltage of the system power supply is within a preset system power supply voltage range;

[0012] If it is not within the preset system power supply voltage range, a system abnormality signal is generated to perform locking control based on the system abnormality signal.

[0013] In a possible implementation, the CPU chip is further used for:

[0014] After the locking control is performed, if it is monitored that the voltage of the system power supply is within a preset system power supply voltage range, the locking control is released after a first preset time.

[0015] In one possible implementation, the power management code includes a Vcc code and / or an LDO code;

[0016] The CPU chip is specifically used to receive and perform locking control based on the Vcc code and / or LDO code of the external independent first AD chip.

[0017] In a possible implementation, the CPU chip is specifically used for:

[0018] Performing locking control based on the value range of the Vcc code and the Vcc code of the first AD chip; wherein the value range of the Vcc code is determined based on the operating voltage range of the first AD chip;

[0019] And / or, locking control is performed based on the numerical range of the LDO code and the Vcc code of the first AD chip; wherein the numerical range of the LDO code is determined based on the operating voltage range of the first AD chip.

[0020] In a possible implementation, the CPU chip is specifically used for:

[0021] When the received Vcc code of the first AD chip reaches a preset number, it is determined whether the Vcc code within the preset number is within the value range of the Vcc code; if it is not within the value range of the Vcc code, a pre-locking flag is generated; when the number of pre-locking flags is greater than or equal to the first preset number of pre-locking flags, a locking flag is generated to perform locking control;

[0022] And / or, when the LDO code of the received first AD chip reaches a preset number, it is determined whether the LDO code within the preset number is within the numerical range of the LDO code; if it is not within the numerical range of the LDO code, a pre-locking flag is generated; when the number of pre-locking flags is greater than or equal to the first preset pre-locking flag number, a locking flag is generated to perform locking control.

[0023] In a possible implementation, the CPU chip is specifically used for:

[0024] When the Vcc code of any first AD chip is not within the value range of the Vcc code within the second preset time, a pre-locking flag is generated; when the number of pre-locking flags within the second preset time is greater than or equal to the second preset number of pre-locking flags, a locking flag is generated to perform locking control;

[0025] And / or, within the second preset time, when the LDO code of any first AD chip is not within the numerical range of the LDO code, a pre-locking flag is generated; when the number of pre-locking flags within the second preset time is greater than or equal to the second preset number of pre-locking flags, a locking flag is generated to perform locking control.

[0026] In a possible implementation, the CPU chip is further configured to release the locking state if no new pre-locking flag is generated within a third preset time in the locking state.

[0027] In a second aspect, an embodiment of the present invention provides a system for monitoring a system power supply voltage, comprising:

[0028] A master station and a power distribution terminal for monitoring system power supply voltage as described in the first aspect;

[0029] The master station is connected to the CPU chip in the power distribution terminal;

[0030] The master station is used to receive the system abnormality signal sent by the CPU chip and control all protection logics in the power distribution terminal to lock;

[0031] Alternatively, the master station is used to receive a blocking flag sent by the CPU chip, and control the protection logic associated with the analog quantity of the distribution network to be blocked.

[0032] The embodiment of the present invention provides a power distribution terminal and system for monitoring the system power supply voltage. Compared with the traditional method, the embodiment of the present invention connects the CPU chip to the power supply end of the external independent first AD chip, collects the voltage of the system power supply for the external independent first AD chip of the power distribution terminal through the CPU chip, and judges whether the analog quantity of the power distribution network collected by the external independent first AD chip is affected by the voltage of the system power supply, so as to judge whether to perform the locking control, which can minimize the safe operation of the power distribution terminal and other devices connected to it. Alternatively, the embodiment of the present invention can also configure a self-diagnosis function in its external independent first AD chip, so that the first AD chip can monitor its own power supply voltage in addition to collecting the conventional analog quantity of the power distribution network to determine the power management code, so that the CPU chip can judge whether the analog quantity of the power distribution network collected by the first AD chip is affected by monitoring the power management code. It can be seen that the present invention can ensure the safe operation of the power distribution terminal and other devices connected to it. In addition, the embodiment of the present invention does not need to install other external devices or chips, and does not need to modify the original power distribution terminal, which can reduce hardware costs and development costs and shorten the development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 is a schematic diagram of the structure of a power distribution terminal for monitoring system power supply voltage provided by an embodiment of the present invention;

[0035] Figure 2 is a graph of the relationship between the Vcc value and the supply voltage at the first AD chip pin;

[0036] Figure 3 is a graph of the relationship between the ALDO value and the supply voltage at the first AD chip pin;

[0037] Figure 4 Schematic diagram of the structure of a system for monitoring system power supply voltage provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0040] Figure 1 is a schematic diagram of the structure of a power distribution terminal for monitoring system power supply voltage provided by an embodiment of the present invention, such as Figure 1 As shown, the power distribution terminal may include:

[0041] The CPU chip 10 and the external independent first AD chip 20; wherein the first AD chip 20 includes a data acquisition terminal, a data output terminal and a power supply terminal.

[0042] The CPU chip 10 is connected to the data output end, and is used to obtain the distribution network analog quantity collected by the first AD chip 20 through the data acquisition end. At the same time, the CPU chip is also connected to the power supply end, and is used to obtain the voltage of the system power supply of the first AD chip 20 and perform locking control based on the voltage of the system power supply.

[0043] Alternatively, the first AD chip 20 is used to monitor its own power supply voltage to obtain the power management code. The CPU chip 10 is connected to the data output end to obtain the power management code of the first AD chip 20 and the analog quantity of the distribution network collected by the data acquisition end, and perform locking control based on the power management code.

[0044] In this embodiment, Figure 1 The diagram includes two data flow directions, a dotted line and a solid line. The dotted line is used to represent the data flow direction in the first type of locking control; the solid line is used to represent the data flow direction in the second type of locking control.

[0045] The first type of locking control is explained below:

[0046] In this embodiment, when the power distribution terminal is actually in operation, there is data interaction between the power distribution terminal and other power equipment connected to it. In the process of data interaction, there is corresponding signal flow and control logic. These signals and control logic are collected based on the data acquisition end of the first AD chip 20 to form corresponding power distribution network analog quantities, and are sent to the CPU chip 10 through the data output end of the first AD chip 20, so that the power distribution terminal can monitor other power equipment in real time based on the collected power distribution analog quantities to ensure the safe operation of the power equipment.

[0047] In order to prevent the data collected by the first AD chip 20 from being affected when the system power supply is abnormal, this embodiment uses the CPU chip 10 to collect the voltage of the system power supply of the first AD chip 20 through the power supply end of the first AD chip 20, so as to determine whether the voltage of the system power supply is abnormal through the obtained system power supply voltage, thereby ensuring the safe operation of each power equipment in the power system.

[0048] In an optional embodiment, the CPU chip 10 includes a second AD chip 12 .

[0049] The second AD chip 12 is connected to the power supply terminal and is used to obtain the voltage of the system power supply of the first AD chip 20 .

[0050] In this embodiment, in order to collect the system power voltage of the first AD chip 20 , the second AD chip 12 in the CPU chip 10 may be functionally configured to collect the system power voltage of the first AD chip 20 through the second AD chip 12 .

[0051] In the traditional method, an external independent AD chip is separately configured on the hardware of the power distribution terminal, and the voltage of the system power supply of the first AD chip 20 is acquired through the separately configured AD chip. The device provided in the embodiment of the present invention does not need to separately configure an AD chip, saving the cost of one AD chip. In addition, considering that the AD chip is separately configured, the original structure of the power distribution terminal needs to be modified, and after the modification, it needs to be deployed before it can be put into use, which increases the hardware cost and the development cost, and prolongs the development cycle. However, the embodiment of the present invention does not modify the structure of the power distribution terminal, which can save costs and shorten the development cycle.

[0052] In the first method, based on a possible implementation, after receiving the voltage of the system power supply of the first AD chip 20, the CPU chip 10 can perform locking control in the following manner:

[0053] Determine whether the voltage of the system power supply is within a preset system power supply voltage range.

[0054] If it is not within the preset system power supply voltage range, a system abnormality signal is generated to perform locking control based on the system abnormality signal.

[0055] In this embodiment, the preset system power supply voltage range is determined based on the power chip data manual of the CPU chip 10 , which is the system power supply voltage range within which the CPU chip 10 can work normally.

[0056] When the collected system power supply voltage is not within the preset system power supply voltage range, it is determined that the system power supply is abnormal. At this time, the distribution network analog quantity collected by the first AD chip 20 is abnormal. Therefore, the CPU chip 10 generates a system abnormality signal to enable the distribution terminal to perform corresponding locking operations.

[0057] When the collected system power supply voltage is within a preset system power supply voltage range, it is determined that the system power supply is in a normal state at this time.

[0058] Based on the first method, after the power distribution terminal performs the locking operation, the locking state can be released through the following steps.

[0059] Accordingly, the CPU chip 10 can also be used for:

[0060] After the locking control is performed, if it is monitored that the voltage of the system power supply is within a preset system power supply voltage range, the locking control is released after a first preset time.

[0061] In this embodiment, after the power distribution terminal performs the locking operation, the second AD chip 12 continues to collect the voltage of the system power supply of the first AD chip 20. If the voltage of the system power supply collected is still not within the preset system power supply voltage range, the locking state is maintained. If the voltage of the system power supply collected is within the preset system power supply voltage range, a locking release signal is generated again when the first preset time is reached to release the locking state. This is because the process from normal to abnormal in the system power supply is very complicated. It is a process of repeated normal and repeated abnormality. It may be that the current state is normal, but the next second is abnormal. If the locking state is immediately released after the voltage of the system power supply is monitored to be within the preset system power supply voltage range, repeated locking and repeated unlocking may occur. Therefore, this embodiment is set to release the locking control after the first preset time to ensure that the system power supply is indeed restored to normal and prevent repeated locking. Among them, the first preset time can be set as needed, for example, one minute and thirty seconds, two minutes, two minutes and thirty seconds, etc., which are not limited here.

[0062] The second type of locking control is explained below:

[0063] In this embodiment, the first AD chip 20 in this embodiment is equipped with a self-monitoring function. In addition to realizing the conventional collection of distribution network analog quantities through its data collection terminal and sending the collected distribution network analog quantities to the CPU chip 10 through the data output terminal, it can also monitor the power supply voltage on its pin while collecting the distribution network analog quantities to obtain the power management code of the power supply voltage, and send the collected power management code to the CPU chip 10 through the data output terminal. The CPU chip 10 determines whether the voltage of the system power supply is abnormal according to the received power management code, thereby ensuring the safe operation of each power device in the power system.

[0064] Among them, in the second method, the power management code determined by the first AD chip 20 and the distribution network analog quantity collected by it correspond one to one, that is, while collecting a group of distribution network analog quantities, it can obtain a group of power management codes by monitoring the power supply voltage on its own pins. In the storage process, the distribution network analog quantity and the power management code are also stored according to their corresponding relationship, so that when the CPU chip 10 determines that there is an abnormality in the power management code, the corresponding abnormal distribution network analog quantity is determined in time, and the corresponding processing is performed in time to ensure the safe operation of each power equipment in the power system.

[0065] In an optional embodiment, the power management code obtained in the second method may include a Vcc code and / or an LDO code.

[0066] Correspondingly, the CPU chip can be specifically used to receive and perform locking control based on the Vcc code and / or LDO code of the external independent first AD chip 20.

[0067] In this embodiment, while the first AD chip 20 monitors the power supply voltage at its own pin, the power supply voltage will generate a corresponding code value in the first AD chip 20. The code value is based on the Vcc diagnostic transfer function and the ALDO diagnostic transfer function, and will be converted into Vcc code and LDO code in the first AD chip 20.

[0068] Among them, the Vcc diagnostic transfer function and the ALDO diagnostic transfer function can be expressed as:

[0069]

[0070] Among them, V CC V is the code value generated in the first AD chip 20 by the voltage of the system power supply; REF is the voltage on the pin of the first AD chip 20, that is, the power supply voltage at its own pin; V ALDO It is the code value generated in the first AD chip 20 by the voltage of the system power supply.

[0071] Figure 2 It is a voltage relationship diagram of Vcc value and supply voltage at the pin; Figure 3 is the voltage relationship diagram of ALDO value and supply voltage at the pin. Accordingly, V CC With V ALDO Can be based on Figure 2 and Figure 3 Sure.

[0072] exist Figure 2 In the figure, the horizontal axis is the supply voltage at the pin, and the vertical axis is V CC Code value, V CC The value is linearly related to the voltage on the pin of the first AD chip 20.

[0073] exist Figure 3 In the figure, the horizontal axis is the supply voltage at the pin, and the vertical axis is V ALDO Code value, V ALDO The value is linearly related to the voltage on the pin of the first AD chip 20.

[0074] based on Figure 2 and Figure 3 It is possible to determine the corresponding V at different voltages on the pins of the first AD chip 20 CC Value and V ALDO value, and then determine the Vcc code and LDO code.

[0075] Accordingly, since the Vcc code and the LDO code reflect the voltage on the pin of the first AD chip 20, it is possible to determine whether the voltage of the system power supply is abnormal based on any one of the Vcc code and the LDO code, and further determine whether locking is required.

[0076] In the second method, based on a possible implementation, after receiving the system power analog quantity, the CPU chip 10 can perform locking control in the following manner:

[0077] The locking control is performed based on the numerical range of the Vcc code and the Vcc code of the first AD chip 20 ; wherein the numerical range of the Vcc code is determined based on the operating voltage range of the first AD chip 20 .

[0078] And / or, locking control is performed based on the numerical range of the LDO code and the Vcc code of the first AD chip 20 ; wherein the numerical range of the LDO code is determined based on the operating voltage range of the first AD chip 20 .

[0079] In this embodiment, although the Vcc code and the LDO code are determined in the same way, the linear relationship between them and the system power supply voltage is different. Therefore, for the voltage of a monitoring point, the corresponding Vcc code and LDO code are different. Taking this embodiment as an example, when performing a lockout judgment, it can be judged based on only the Vcc code or only the LDO code. Of course, the Vcc code and the LDO code can also be combined for judgment. The following other related embodiments can refer to this embodiment.

[0080] In this embodiment, since the first AD chip 20 needs to work within its rated voltage range, that is, the working voltage range of the first AD chip 20 is predetermined, the corresponding Vcc code value range and LDO code value range can be determined based on its working voltage range.

[0081] After receiving the system power analog quantity, that is, after receiving the Vcc code and / or LDO code, the CPU chip 10 determines whether the received Vcc code and / or LDO code is within its corresponding numerical range according to the numerical range of the Vcc code and / or the numerical range of the LDO code, so as to perform locking control.

[0082] In this embodiment, for the second method, the CPU chip 10 can determine whether a locking operation is required through two operation steps. The first operation step is described below:

[0083] When the received Vcc code of the first AD chip 20 reaches a preset number, it is determined whether the Vcc code within the preset number is within the numerical range of the Vcc code; if it is not within the numerical range of the Vcc code, a pre-locking flag is generated; when the number of pre-locking flags is greater than or equal to the first preset pre-locking flag number, a locking flag is generated to perform locking control.

[0084] And / or, when the LDO code received from the first AD chip 20 reaches a preset number, it is determined whether the LDO code within the preset number is within the numerical range of the LDO code; if it is not within the numerical range of the LDO code, a pre-locking flag is generated; when the number of pre-locking flags is greater than or equal to the first preset pre-locking flag number, a locking flag is generated to perform locking control.

[0085] In this embodiment, the first AD chip 20 collects analog quantities according to the periodic frequency fluctuation, and the corresponding power management code also presents periodicity. Exemplarily, based on the pre-set settings, the analog quantities collected by the first AD chip 20 can be 80 groups of data in each periodic fluctuation. Accordingly, with 80 data as a group, a judgment can be made each time the Vcc code and / or LDO code obtained reaches 80 to determine whether to perform a locking operation.

[0086] Exemplarily, assuming that the preset number is 80, taking the Vcc code as an example, in the CPU chip 10, whenever the obtained Vcc code reaches 80, it is determined whether there is a Vcc code that is not within the numerical range of the Vcc code among the 80 Vcc codes. If there is, a pre-locking flag is generated for each one. When the pre-locking flag generated among the 80 Vcc codes is greater than or equal to the first preset number of pre-locking flags, it means that the system power supply or the power supply voltage at the pin of the first AD chip 20 is abnormal at this time, and a locking operation is required, then a locking flag is generated to perform locking control according to the locking flag, thereby protecting the power distribution terminal and other related power equipment.

[0087] In this embodiment, if the pre-locking flag generated in these 80 Vcc codes is less than the first preset pre-locking flag number, it means that the Vcc code is not within the numerical range of the Vcc code due to external influences or calculation errors, and the system power supply is not abnormal. In this case, it can be considered that the current 80 Vcc codes and their corresponding distribution network analog quantities are normal, and there is no need to perform locking control, and the next group of system power supply analog quantities can be judged.

[0088] In this embodiment, the number of the first preset pre-locking flags can be 6, 7, or 8, which can be set according to actual needs and is not specifically limited here. In addition, the logic for judging the LDO code or combining the Vcc code and the LDO code is the same as the above judgment logic, which will not be repeated here.

[0089] The following is an explanation of the second operation steps in the second method:

[0090] Accordingly, the CPU chip 10 can be specifically used for:

[0091] Within the second preset time, when the Vcc code of any first AD chip 20 is not within the numerical range of the Vcc code, a pre-locking flag is generated; when the number of pre-locking flags within the second preset time is greater than or equal to the second preset number of pre-locking flags, a locking flag is generated to perform locking control.

[0092] And / or, within the second preset time, when the LDO code of any first AD chip 20 is not within the numerical range of the LDO code, a pre-locking flag is generated; when the number of pre-locking flags within the second preset time is greater than or equal to the second preset number of pre-locking flags, a locking flag is generated to perform locking control.

[0093] In this embodiment, since the process of the system power supply changing from normal to abnormal is a complex process, when it is abnormal, it usually does not appear suddenly, and it may be a process of repeated abnormality and repeated normality. Therefore, in the initial stage of the system power supply abnormality, the number of pre-locking marks that exist may not reach the first preset number of pre-locking marks within the preset number, which is easy to cause misjudgment. In view of this problem, this embodiment provides a second operation.

[0094] In this embodiment, the Vcc code is used as an example for explanation. The CPU chip 10 receives the Vcc code of the first AD chip 20, and determines whether all Vcc codes within the preset time are within the numerical range of the Vcc code. If there is any Vcc code that is not within the numerical range of the Vcc code, the CPU chip 10 generates a corresponding pre-locking flag. After the CPU chip 10 determines all Vcc codes within the preset time, it counts the pre-locking flags generated within the preset time. If the pre-locking flag is greater than or equal to the second preset pre-locking flag number, it means that the system power supply is abnormal within the preset time, and the CPU chip 10 generates a locking flag to perform locking control.

[0095] In this embodiment, the second preset time can be one minute and thirty seconds, two minutes, two minutes and thirty seconds, etc., which is not limited here; the number of second preset pre-locking marks can be 14, 15, 16, etc., which is not limited here.

[0096] In addition, the logic for judging the LDO code or combining the Vcc code and the LDO code is the same as the above judgment logic, which will not be repeated here.

[0097] Based on the second method, after the power distribution terminal performs the locking operation, the locking state can be released by following the steps below:

[0098] Correspondingly, the CPU chip 10 can also be used to release the locked state if no new pre-locking flag is generated within a third preset time in the locked state.

[0099] In this embodiment, in order to avoid false tripping and repeated locking of the protection, when the CPU chip 10 detects that no pre-locking mark is generated continuously within the third preset time, that is, within the third preset time, all Vcc codes and / or LDO codes are within their corresponding value ranges, a lock release signal is generated to release the lock protection function.

[0100] In summary, the embodiments of the present invention provide two methods for monitoring the voltage of the system power supply. Through these two methods, it is possible to determine in real time whether the analog quantity of the distribution network collected by the first AD chip is affected, thereby ensuring the safe operation of the distribution terminal and other equipment connected to it. In addition, the embodiments of the present invention do not require other external devices or chips, do not need to modify the original distribution terminal, and can reduce hardware.

[0101] In addition, it should be understood that in actual use, the two methods for determining whether the voltage of the system power supply is abnormal provided in this embodiment can be used in combination with each other or can be used separately.

[0102] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0103] The following is a system embodiment of the present invention. For details not described in detail therein, reference may be made to the above-mentioned corresponding power distribution terminal embodiment.

[0104] Figure 4 A schematic diagram of the structure of a system for monitoring system power supply voltage provided by an embodiment of the present invention is shown. For ease of description, only the parts related to the embodiment of the present invention are shown, which are described in detail as follows:

[0105] like Figure 4 As shown, the system 4 for monitoring the system power supply voltage includes:

[0106] A master station 1 and a power distribution terminal 2 for monitoring the system power supply voltage.

[0107] The master station 1 is communicatively connected to the CPU chip 10 in the power distribution terminal 2 .

[0108] The master station 1 is used to receive the system abnormality signal sent by the CPU chip 10 and control all protection logics in the power distribution terminal 2 to be locked.

[0109] Alternatively, the master station 1 is used to receive a blocking flag sent by the CPU chip 10 and control the protection logic associated with the analog quantity of the distribution network to be blocked.

[0110] In this embodiment, since the power distribution terminal can use two different methods to monitor the voltage of the system power supply, for these two monitoring methods, when there is a fault in the voltage of the system power supply, the CPU chip 10 generates two different signals. According to these two different signals, the master station 1 has different locking controls.

[0111] Specifically, for the first method, after the CPU chip 10 generates a system abnormality signal, the generated system abnormality signal can be uploaded to the main station 1 in the form of remote signaling. Considering that the first method is to directly monitor the voltage of the system power supply, the system power supply not only supplies power to the first AD chip 20, but also supplies power to other power equipment. When the voltage of the system power supply is determined to be abnormal, it will affect all analog quantities collected by the first AD chip 20 and other related power equipment. Therefore, at this time, the main station 1 needs to control all protection logics and all functions in the distribution terminal 2 to be locked.

[0112] For the second method, after the CPU chip 10 generates a lockout mark, the generated lockout mark can be uploaded to the master station 1 in the form of remote signaling. Considering that the power management code is the power supply voltage at the pin 20 of the first AD chip, in actual applications, when an abnormality is determined based on the power management code, it is possible that only the power supply voltage at the pin 20 of the first AD chip is abnormal, and the system power supply voltage for other power equipment is normal. Since the power management code obtained in the second method corresponds one-to-one to the analog quantity of the distribution network, when an abnormality occurs in the power management code, it will only affect the corresponding protection logic and will not affect other functions. Therefore, the master station 1 can lock the protection logic associated with the analog quantity of the distribution network based on the lockout mark control, and there is no need to lock other functions that do not involve analog quantities.

[0113] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] Those of ordinary skill in the art will appreciate that the templates, units, and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0115] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A power distribution terminal for monitoring system power supply voltage, characterized in that: include: A CPU chip and an external independent first AD chip; wherein the first AD chip includes a data acquisition terminal, a data output terminal and a power supply terminal; The CPU chip is connected to the data output terminal, and is used to obtain the power distribution network analog quantity collected by the first AD chip through the data collection terminal. At the same time, the CPU chip is also connected to the power supply terminal, and is used to obtain the voltage of the system power supply of the first AD chip and perform locking control based on the voltage of the system power supply; Alternatively, the first AD chip is used to monitor its own power supply voltage to obtain a power management code, and the CPU chip is connected to the data output end to obtain the power management code of the first AD chip and the analog quantity of the distribution network collected by the data acquisition end, and perform locking control based on the power management code.

2. The power distribution terminal for monitoring system power supply voltage according to claim 1, characterized in that: The CPU chip includes a second AD chip; The second AD chip is connected to the power supply terminal and is used to obtain the voltage of the system power supply of the first AD chip.

3. The power distribution terminal for monitoring system power supply voltage according to claim 1, characterized in that: The CPU chip is specifically used for: Determining whether the voltage of the system power supply is within a preset system power supply voltage range; If it is not within the preset system power supply voltage range, a system abnormality signal is generated to perform locking control based on the system abnormality signal.

4. The power distribution terminal for monitoring system power supply voltage according to claim 3, characterized in that: The CPU chip is also used for: After the locking control is performed, if it is monitored that the voltage of the system power supply is within the preset system power supply voltage range, the locking control is released after a first preset time.

5. The power distribution terminal for monitoring system power supply voltage according to claim 1, characterized in that: The power management code includes a Vcc code and / or an LDO code; The CPU chip is specifically used to receive and perform locking control based on the Vcc code and / or LDO code of the external independent first AD chip.

6. The power distribution terminal for monitoring system power supply voltage according to claim 5, characterized in that: The CPU chip is specifically used for: Performing locking control based on the value range of the Vcc code and the Vcc code of the first AD chip; wherein the value range of the Vcc code is determined based on the operating voltage range of the first AD chip; And / or, performing locking control based on a numerical range of the LDO code and a Vcc code of the first AD chip; wherein the numerical range of the LDO code is determined based on an operating voltage range of the first AD chip.

7. The power distribution terminal for monitoring system power supply voltage according to claim 6, characterized in that: The CPU chip is specifically used for: When the received Vcc code of the first AD chip reaches a preset number, determining whether the Vcc codes within the preset number are within the value range of the Vcc code; If it is not within the value range of the Vcc code, a pre-locking flag is generated; When the number of the pre-locking flags is greater than or equal to the first preset number of pre-locking flags, generating a locking flag to perform locking control; and / or, when the received LDO codes of the first AD chip reach a preset number, determining whether the LDO codes within the preset number are within a value range of the LDO codes; If it is not within the value range of the LDO code, a pre-locking flag is generated; When the number of the pre-locking flags is greater than or equal to the first preset number of pre-locking flags, a locking flag is generated to perform locking control.

8. The power distribution terminal for monitoring system power supply voltage according to claim 5, characterized in that: The CPU chip is specifically used for: Within the second preset time, when the Vcc code of any one of the first AD chips is not within the value range of the Vcc code, a pre-locking flag is generated; When the number of pre-locking marks within the second preset time is greater than or equal to the second preset number of pre-locking marks, generating a locking mark to perform locking control; and / or, within a second preset time, when the LDO code of any one of the first AD chips is not within the value range of the LDO code, a pre-locking flag is generated; When the number of pre-locking marks within the second preset time is greater than or equal to the second preset number of pre-locking marks, a locking mark is generated to perform locking control.

9. The power distribution terminal for monitoring system power supply voltage according to claim 7 or 8, characterized in that: The CPU chip is further used for releasing the locking state if no new pre-locking mark is generated within a third preset time in the locking state.

10. A system for monitoring system power supply voltage, characterized in that: include: A master station and a power distribution terminal for monitoring system power supply voltage as claimed in any one of claims 1 to 9; The master station is communicatively connected with the CPU chip in the power distribution terminal; The master station is used to receive the system abnormality signal sent by the CPU chip and control all protection logics in the power distribution terminal to be locked; Alternatively, the master station is used to receive a blocking flag sent by the CPU chip, and control the protection logic associated with the analog quantity of the distribution network to be blocked.

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