Detection and regulation circuits, switching power supplies, chips and electronic equipment

Abstract

The present application provides a detection and regulation circuit, a switching power supply, a chip, and an electronic device. The detection and regulation circuit includes: a detection circuit, a regulation circuit, and a COT control circuit. The detection circuit obtains a square wave signal and a first control signal, and obtains a detection signal based on the square wave signal and the first control signal, and transmits the detection signal to the regulation circuit. In this way, the regulation circuit can obtain a clock signal in the next switching cycle, and obtain an adjustment signal based on the clock signal and the detection signal, and transmit the adjustment signal to the COT control circuit. Furthermore, the COT control circuit can change the switching cycle of the switching power supply based on the adjustment signal and the second control signal to dynamically adjust the switching frequency of the switching power supply. As a result, the output voltage of the switching power supply reaches a preset stable voltage value, ensuring that the switching power supply has the ability to adjust the output voltage and improving the performance of the switching power supply.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a detection and regulation circuit, a switching power supply, a chip, and an electronic device. Background Art

[0002] A switching power supply converts its input voltage into a preset output voltage by periodically turning on or off the power transistors in the switching power supply using a pulse width modulation (PWM) signal with a specific duty cycle. When a PWM signal is modulated using a variable frequency modulation method with a constant on-time or constant off-time, if the voltage conversion ratio between the input and output voltages causes the PWM signal to approach the minimum on-time or minimum off-time, the output voltage will not reach the preset voltage, resulting in reduced performance of the switching power supply. Summary of the Invention

[0003] The present application provides a detection and regulation circuit, a switching power supply, a chip, and an electronic device, which can ensure that the output voltage reaches a preset voltage value and improve the performance of the switching power supply.

[0004] In a first aspect, the present application provides a detection and regulation circuit, which is applied to a switching power supply, the switching power supply comprising: a pulse width modulation comparator; the detection and regulation circuit comprising: a detection circuit, a regulation circuit and a COT control circuit;

[0005] The first input terminal of the detection circuit is electrically connected to the output terminal of the pulse width modulation comparator, the second input terminal of the detection circuit is electrically connected to the output terminal of the COT control circuit, the first output terminal of the detection circuit is electrically connected to the first input terminal of the regulation circuit, the second output terminal of the detection circuit is electrically connected to the second input terminal of the regulation circuit, and the output terminal of the regulation circuit is electrically connected to the input terminal of the COT control circuit;

[0006] The detection circuit is configured to obtain a square wave signal from the pulse width modulation comparator and a first control signal from the COT control circuit, and to obtain a detection signal based on the square wave signal and the first control signal, and transmit the detection signal to the regulation circuit, wherein the square wave signal is used to indicate whether the switching power supply is in a constant on-time control mode or a constant off-time control mode, the first control signal is used to indicate the duration of the on-time or off-time of the switching power supply in a previous switching cycle, and the detection signal is used to indicate whether the switching power supply has entered a minimum off-time or minimum on-time in the previous switching cycle;

[0007] The regulating circuit is configured to obtain a clock signal from the detection circuit in a subsequent switching cycle, obtain a regulating signal based on the clock signal and the detection signal, and transmit the regulating signal to the COT control circuit, wherein the regulating signal is used to determine whether it is necessary to extend the duration of the on-time or the off-time in the subsequent switching cycle;

[0008] The COT control circuit is used to obtain the second control signal according to the adjustment signal to dynamically adjust the switching frequency of the switching power supply, and the second control signal is used to represent the duration of the on-time or off-time of the switching power supply in the subsequent switching cycle.

[0009] The detection and regulation circuit provided in the first aspect obtains a square wave signal from a pulse width modulation comparator indicating that the switching power supply is in a constant on-time control mode or a constant off-time control mode, and obtains a first control signal from a COT control circuit indicating the duration of the on-time or off-time of the switching power supply in a previous switching cycle. Based on the square wave signal and the first control signal, a detection signal is obtained indicating whether the switching power supply entered a minimum off-time or minimum on-time in the previous switching cycle, and the detection signal is transmitted to the regulation circuit so that the regulation circuit can obtain the detection signal. In this way, the regulation circuit can obtain a clock signal from the detection circuit in a subsequent switching cycle, obtain an adjustment signal based on the clock signal and the detection signal, and transmit the adjustment signal to the COT control circuit to determine whether the on-time or off-time in the subsequent switching cycle needs to be extended, so that the COT control circuit can obtain the adjustment signal. Furthermore, the COT control circuit can generate a second control signal based on the adjustment signal, representing the duration of the switching power supply's on-time or off-time in the next switching cycle. This changes the on-time or off-time of the pulse-width modulation signal generated based on the second control signal and the square wave signal in the next switching cycle, thereby changing the switching cycle of the switching power supply and dynamically adjusting its switching frequency. This ensures that the output voltage of the switching power supply reaches a preset stable voltage value, ensuring the switching power supply's ability to regulate the output voltage and improving its performance.

[0010] In one possible design, the first control signal includes: a first sub-control signal and a second sub-control signal; the detection signal includes: a first detection signal and a second detection signal; the clock signal includes: a first clock signal and a second clock signal; the adjustment signal includes: a first adjustment signal and a second adjustment signal; and the second control signal includes: a third sub-control signal and a fourth sub-control signal;

[0011] The detection circuit is specifically configured to, when the square wave signal indicates that the switching power supply is in the constant on-time control mode, obtain a first detection signal based on the square wave signal and the first sub-control signal, and transmit the first detection signal to the regulation circuit, wherein the first sub-control signal is used to indicate a duration of the on-time of the switching power supply in the previous switching cycle, and the first detection signal is used to indicate whether the switching power supply entered the minimum off-time in the previous switching cycle;

[0012] The regulating circuit is specifically configured to obtain, in the subsequent switching cycle, the first regulating signal according to the first clock signal and the first detection signal, and transmit the first regulating signal to the COT control circuit, wherein the first regulating signal is used to determine whether the on-time in the subsequent switching cycle needs to be extended;

[0013] The COT control circuit is specifically configured to obtain the third sub-control signal according to the first adjustment signal, wherein the third sub-control signal is used to represent the duration of the on-time of the switching power supply in the subsequent switching cycle;

[0014] or,

[0015] The detection circuit is specifically configured to, when the square wave signal indicates that the switching power supply is in the constant off-time control mode, obtain a second detection signal based on the square wave signal and the second sub-control signal, and transmit the second detection signal to the regulation circuit, wherein the second sub-control signal is used to indicate the duration of the off-time of the switching power supply in the previous switching cycle, and the second detection signal is used to indicate whether the switching power supply entered the minimum on-time in the previous switching cycle;

[0016] The regulating circuit is specifically configured to obtain, in a subsequent switching cycle, the second regulating signal according to the second clock signal and the second detection signal, and transmit the second regulating signal to the COT control circuit, wherein the second regulating signal is used to determine whether the off time in the subsequent switching cycle needs to be extended;

[0017] The COT control circuit is specifically configured to obtain the fourth sub-control signal according to the second adjustment signal, wherein the fourth sub-control signal is configured to represent the duration of the on-time of the switching power supply in the subsequent switching cycle.

[0018] In one possible design, the detection circuit includes: a detection control component, a clock signal output component, and a detection signal output component;

[0019] The first input end of the detection and control component is electrically connected to the output end of the pulse width modulation comparator, the second input end of the detection and control component is electrically connected to the output end of the COT control circuit, the input end of the clock signal output component is electrically connected to the first output end or the second output end of the detection and control component, the output end of the clock signal output component is electrically connected to the second input end of the regulation circuit and the first input end of the detection signal output component respectively, the second input end of the detection signal output component is used to access the power supply voltage, and the output end of the detection signal output component is electrically connected to the first input end of the regulation circuit;

[0020] the detection and control component being configured to control, when the square wave signal indicates that the switching power supply is in a constant on-time control mode, to electrically connect the first output terminal of the detection and control component to the input terminal of the clock signal output component, and to obtain a first pulse width modulation signal based on the square wave signal and the first sub-control signal, and to transmit the first pulse width modulation signal to the clock signal output component;

[0021] The clock signal output component is configured to transmit the first clock signal to the detection signal output component according to the first pulse width modulation signal;

[0022] The detection signal output component is configured to detect, based on the first clock signal, whether the switching power supply enters the minimum off-time in the previous switching cycle, and obtain the first detection signal;

[0023] or,

[0024] the detection and control component being configured to control the second output terminal of the detection and control component to be electrically connected to the input terminal of the clock signal output component when the square wave signal indicates that the switching power supply is in a constant off-time control mode, and to obtain a second pulse-width modulation signal based on the square wave signal and the second sub-control signal, and to transmit the second pulse-width modulation signal to the clock signal output component;

[0025] The clock signal output component is configured to transmit the second clock signal to the detection signal output component according to the second pulse width modulation signal;

[0026] The detection signal output component is used to detect whether the switching power supply enters the minimum on-time in the previous switching cycle according to the second clock signal, so as to obtain the second detection signal.

[0027] In one possible design, the detection control component includes: a first trigger;

[0028] The set end of the first trigger is electrically connected to the output end of the pulse width modulation comparator, the reset end of the first trigger is electrically connected to the output end of the COT control circuit, and the positive output end or the reverse output end of the first trigger is electrically connected to the input end of the clock signal output component.

[0029] In one possible design, the clock signal output component includes: a first switch tube, a second switch tube and a first inverter;

[0030] The first end of the second switching tube is electrically connected to the first output end or the second output end of the detection control component, the second end of the second switching tube is electrically connected to the first end of the first switching tube and the input end of the first inverter respectively, the second end of the first switching tube and the output end of the first inverter are both electrically connected to the first input end of the detection signal output component, and the control end of the first switching tube and the control end of the second switching tube are both used to receive a switching signal, and the switching signal is used to control the conduction or shutdown of the switching tube.

[0031] In one possible design, the detection signal output component includes: a second inverter, a delay device, and a second trigger;

[0032] The input end of the second inverter and the input end of the delay device are both electrically connected to the output end of the clock signal output component, the output end of the second inverter is electrically connected to the clock input end of the second trigger, the output end of the delay device is electrically connected to the set input end of the second trigger, the data input end of the second trigger is used to access the power supply voltage, and the output end of the second trigger is electrically connected to the first input end of the regulation circuit.

[0033] In one possible design, the regulating circuit includes: a counter;

[0034] The clock input terminal of the counter is electrically connected to the second output terminal of the detection circuit, the count input terminal of the counter is electrically connected to the first output terminal of the detection circuit, and the output terminal of the counter is electrically connected to the input terminal of the COT control circuit;

[0035] the counter being configured to obtain the first clock signal from the detection circuit during the subsequent switching cycle, and determine, at a rising edge of the first clock signal, based on the first detection signal, whether to count up the first value of the counter to obtain the first adjustment signal;

[0036] or,

[0037] The counter is used to obtain the second clock signal from the detection circuit during the next switching cycle, and determine whether to count up the first value of the counter based on the second detection signal at the rising edge of the second clock signal to obtain the second adjustment signal.

[0038] In one possible design, the regulating circuit further includes: a frequency divider;

[0039] The input end of the frequency divider is electrically connected to the second output end of the detection circuit, and the output end of the frequency divider is electrically connected to the clock input end of the counter;

[0040] The frequency divider is configured to divide the first clock signal to obtain a first frequency-divided clock signal, and transmit the first frequency-divided clock signal to the counter so that the counter obtains the first adjustment signal;

[0041] or,

[0042] The frequency divider is used to divide the second clock signal to obtain a second frequency-divided clock signal, and transmit the second frequency-divided clock signal to the counter so that the counter obtains the second adjustment signal.

[0043] In one possible design, the COT control circuit includes: a current output component, a capacitor, and a timing comparator;

[0044] The control end of the current output component is electrically connected to the output end of the regulating circuit, the output end of the current output component is electrically connected to the first plate of the capacitor, the positive input end of the timing comparator is electrically connected between the output end of the current output component and the first plate of the capacitor, the negative input end of the timing comparator is used to access a reference voltage, the reference voltage is related to the square wave signal, and the output end of the timing comparator is electrically connected to the first input end of the detection circuit;

[0045] The current output component is configured to output a first charging current corresponding to the first regulating signal, and charge the capacitor using the first charging current;

[0046] The timing comparator is configured to compare the voltage on the capacitor with the reference voltage to obtain the third sub-control signal;

[0047] or,

[0048] The current output component is configured to output a second charging current corresponding to the second adjustment signal, and charge the capacitor using the second charging current;

[0049] The timing comparator is used to compare the voltage on the capacitor with the reference voltage to obtain the fourth sub-control signal.

[0050] In one possible design, the current output component includes: a current source, a first N-type transistor, a second N-type transistor, a first P-type transistor, a second P-type transistor, a plurality of N-type transistor groups, and a plurality of third inverters;

[0051] The output end of the current source is electrically connected to the drain end of the first N-type transistor, the gate end of the first N-type transistor is electrically connected to the gate end of the second N-type transistor and the first gate end of each N-type transistor group, the drain end of the first N-type transistor is electrically connected to the drain end of each N-type transistor group, the drain end of the first P-type transistor, the gate end of the first P-type transistor and the gate end of the second P-type transistor, the drain end of the second P-type transistor is electrically connected to the first plate of the capacitor, the source end of the first P-type transistor and the source end of the second P-type transistor are both used to access the power supply voltage, the second gate end of each N-type transistor group is electrically connected to the output end of each third inverter, the input end of each third inverter is electrically connected to the output end of the regulation circuit, and the source end of the first N-type transistor, the source end of the second N-type transistor and the source end of each N-type transistor group are all grounded.

[0052] In one possible design, the number of the first N-type transistors is the sum of the number of the second N-type transistors and the number of the multiple N-type transistor groups, the number of the first P-type transistors is equal to the number of the second P-type transistors, the number of the second N-type transistors is related to the longest duration of the on-time or off-time of the switching power supply, and the number of the multiple N-type transistor groups is related to the step size of the adjustment of the switching frequency.

[0053] In a second aspect, the present application provides a switching power supply, comprising: a high-side power transistor, a low-side power transistor, an inductor, an output capacitor, a first resistor, a second resistor, a pulse width modulation comparator, a controller, a loop-controlled current output circuit, and the detection and regulation circuit in the first aspect and each possible design of the first aspect;

[0054] The input end of the loop-controlled current output circuit is electrically connected to the second end of the inductor and the first plate of the output capacitor respectively. The second end of the inductor is also used to output the output voltage of the switching power supply. The output end of the loop-controlled current output circuit is electrically connected to the first end of the first resistor. The second end of the first resistor is electrically connected to the negative phase input end of the pulse width modulation comparator. The first end of the second resistor is used to detect the current of the inductor. The second end of the second resistor is electrically connected to the positive phase input end of the pulse width modulation comparator. The output end of the pulse width modulation comparator is respectively connected to the first input end of the detection circuit and the first input end of the controller. The input end is electrically connected to the output end of the COT control circuit is electrically connected to the second input end of the controller, the first output end of the controller is electrically connected to the control end of the high-side power transistor, the second output end of the controller is electrically connected to the control end of the low-side power transistor, the first end of the high-side power transistor is used to access the input voltage of the switching power supply, the second end of the high-side power transistor is electrically connected to the first end of the low-side power transistor, the first end of the inductor is electrically connected between the second end of the high-side power transistor and the first end of the low-side power transistor, and the second end of the low-side power transistor and the second plate of the output capacitor are both grounded.

[0055] The beneficial effects of the switching power supply provided in the second aspect and each possible design of the second aspect can be referred to the beneficial effects brought about by the first aspect and each possible implementation method of the first aspect, and will not be repeated here.

[0056] In a third aspect, the present application provides a chip, comprising: the detection and regulation circuit in the above-mentioned first aspect and each possible design of the above-mentioned first aspect, and / or the switching power supply in the above-mentioned second aspect.

[0057] In a fourth aspect, the present application provides an electronic device, comprising: the chip in the third aspect above.

[0058] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] Figure 1 A schematic structural diagram of a detection and adjustment circuit provided in one embodiment of the present application;

[0061] Figure 2 A schematic diagram of the structure of a COT control circuit in a detection and regulation circuit provided in one embodiment of the present application;

[0062] Figure 3 A detection timing diagram of a detection and adjustment circuit provided in one embodiment of the present application;

[0063] Figure 4 A detection timing diagram of another detection and adjustment circuit provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of the structure of a switching power supply provided in one embodiment of the present application. DETAILED DESCRIPTION

[0065] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0066] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0067] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0068] Typically, pulse width modulation (PWM) signals are modulated using fixed-frequency modulation (FFM) and variable-frequency modulation (VFM). VFM has a faster response than fixed-frequency modulation. VFM includes constant on-time (COT) or constant off-time (COT) modulation.

[0069] When the input voltage and output voltage of the switching power supply are stable, the duty cycle of the pulse width modulation signal is fixed.

[0070] For switching power supplies operating in constant on-time (COT) control mode, or valley current mode, COT control only takes effect when the switching frequency changes due to changes in input or output voltage. Therefore, to stabilize the switching frequency, the switching power supply incorporates an adaptive controller, COT timer1, to achieve adaptive on-time control when the input and output voltages change.

[0071] Taking a buck converter (Buck) as an example, the voltage conversion ratio between the input voltage and the output voltage of the Buck converter can be expressed by formula (1):

[0072]

[0073] Where VOUT1 is the output voltage, VIN1 is the input voltage, Ton' is the on-time, Toff' is the off-time, and Tsw' is the switching period.

[0074] When the output voltage VOUT1 remains unchanged and the input voltage VIN1 gradually decreases, due to the use of adaptive on-time control, the on-time Ton' will gradually increase, while the switching period Tsw' remains unchanged. Therefore, the loop in the Buck converter will adjust the off-time Toff' to gradually decrease. Since the off-time Toff' cannot be reduced indefinitely, the off-time Toff' of the Buck converter will be fixed to a minimum off-time Toff_min1. When the input voltage VIN1 continues to decrease, since the loop can no longer adjust the off-time Toff' lower than the minimum off-time Toff_min1, the output voltage VOUT1 will drop, making the output voltage VOUT1 unable to reach the preset voltage value, resulting in reduced performance of the Buck converter.

[0075] For switching power supplies operating in constant off-time (COT) control mode, or peak current mode, an adaptive controller (COT timer1) is introduced to stabilize the switching frequency when the input and output voltages change. This controller implements adaptive off-time control. Similarly, in a buck converter, when there is a significant difference between the input voltage VIN1 and the output voltage VOUT1, the off-time Toff' gradually increases due to adaptive on-time control, while the switching period Tsw' remains constant. Consequently, the loop adjusts the on-time Ton' to gradually decrease. Because the on-time Ton' cannot be reduced indefinitely, the buck converter's on-time Ton' is fixed to a minimum on-time Ton_min1. When the output voltage VOUT1 remains constant and the input voltage VIN1 gradually increases, the loop adjusts the on-time Ton' to gradually decrease to ensure a stable output voltage VOUT1. When the on-time Ton' falls below the minimum on-time Ton_min1, the loop cannot adjust further downward. Therefore, the output voltage VOUT1 increases due to the excessive energy transferred, so that the output voltage VOUT1 cannot reach the preset voltage value, resulting in a decrease in the performance of the Buck converter.

[0076] Based on the above description, it can be seen that when the voltage conversion ratio between the input voltage and the output voltage causes the pulse width modulation signal to approach the minimum on-time or the minimum off-time, that is, when the switching power supply enters the minimum on-time or the minimum off-time, the output voltage value cannot reach the preset voltage value, resulting in a decrease in the performance of the switching power supply.

[0077] To address the aforementioned issues, the present application provides a detection and regulation circuit that dynamically adjusts the switching frequency of a switching power supply by detecting whether the switching power supply has entered its minimum on-time or off-time and adjusting the on-time or off-time. This ensures that the output voltage of the switching power supply reaches a preset voltage value, thereby improving the performance of the switching power supply.

[0078] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a detection and adjustment circuit provided in one embodiment of the present application. Figure 1 As shown, the detection and regulation circuit 100 may include: a detection circuit 110 , a regulation circuit 120 and a COT control circuit 130 .

[0079] A first input terminal of the detection circuit 110 is electrically connected to an output terminal of the pulse width modulation comparator PWM Comp, a second input terminal of the detection circuit 110 is electrically connected to an output terminal of the COT control circuit 130, a first output terminal of the detection circuit 110 is electrically connected to a first input terminal of the regulation circuit 120, a second output terminal of the detection circuit 110 is electrically connected to a second input terminal of the regulation circuit 120, and an output terminal of the regulation circuit 120 is electrically connected to an input terminal of the COT control circuit 130.

[0080] The detection circuit 110 , the adjustment circuit 120 and the COT control circuit 130 may be provided separately or integrated, and this embodiment of the present application does not specifically limit this.

[0081] The detection circuit 110 can obtain a square wave signal CMPO from the pulse width modulation comparator PWM Comp and a first control signal TCOT1 from the COT control circuit 130. Furthermore, based on the square wave signal CMPO and the first control signal TCOT1, the detection circuit 110 can detect whether the switching power supply 1000 has entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle, thereby generating a detection signal DROP. The detection circuit 110 then transmits the detection signal DROP to the regulation circuit 120, allowing the regulation circuit 120 to obtain the detection signal DROP.

[0082] The square wave signal CMPO is used to indicate whether the switching power supply 1000 is in a constant on-time control mode or a constant off-time control mode, and the first control signal TCOT1 is used to indicate the on-time or off-time duration of the switching power supply 1000 in the previous switching cycle.

[0083] For example, when square wave signal CMPO is at a low level, the current in inductor L1 in switching power supply 1000 begins to decrease from its peak current. When square wave signal CMPO transitions from a low level to a high level, the current in inductor L1 decreases to a valley current. In other words, switching power supply 1000 is in constant on-time control mode. In this manner, detection and regulation circuit 100 can detect the valley current of switching power supply 1000.

[0084] For example, when square wave signal CMPO is at a low level, the current in inductor L1 begins to increase from a valley current. When square wave signal CMPO transitions from a low level to a high level, the current in inductor L1 increases to a peak current. In other words, switching power supply 1000 is in constant off-time control mode. In this manner, detection and regulation circuit 100 can detect the peak current of switching power supply 1000.

[0085] For example, when the detection signal DROP is at a high level, the detection signal DROP may indicate that the switching power supply 1000 has entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle. When the detection signal DROP is at a low level, the detection signal DROP may indicate that the switching power supply 1000 has not entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle.

[0086] In this way, the regulating circuit 120 can obtain the clock signal from the detection circuit 110 in the next switching cycle. In addition, the regulating circuit 120 can obtain the regulating signal Q according to the clock signal and the detection signal DROP. <n:1>, and transmits the adjustment signal Q to the COT control circuit 130 <n:1>, so that the COT control circuit 130 can obtain the adjustment signal Q <n:1>.

[0087] Among them, the adjustment signal Q <n:1>It is used to determine whether it is necessary to extend the on-time or off-time in the next switching cycle. <n:1>When the corresponding value increases, it means that the adjustment signal Q <n:1>It is used to determine the duration of the on-time or off-time in the next switching cycle. <n:1>When the corresponding value decreases, it means that the adjustment signal Q <n:1>Used to determine how long the on-time or off-time does not need to be extended in the following switching cycle.

[0088] For example, when the detection signal DROP indicates that the switching power supply 1000 has entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding value increases, adjusting the signal Q <n:1>It is used to determine the length of time that the on-time or off-time needs to be extended in the next switching cycle. For multiple switching cycles, if the detection signal DROP indicates that the switching power supply 1000 has entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding values ​​are getting larger and larger.

[0089] When the detection signal DROP indicates that the switching power supply 1000 has not entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding value decreases, adjusting the signal Q <n:1>For multiple switching cycles, if the detection signal DROP indicates that the switching power supply 1000 has not entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding values ​​are getting smaller and smaller.

[0090] Furthermore, the COT control circuit 130 can adjust the signal Q <n:1>, obtaining a second control signal TCOT2, thereby changing the on-duration or off-duration of the pulse-width modulation signal generated based on the second control signal TCOT2 and the square wave signal CMPO in the next switching cycle. This allows the switching cycle of the switching power supply 1000 to be changed, thereby dynamically adjusting the switching frequency of the switching power supply 1000. Consequently, the output voltage of the switching power supply 1000 reaches a preset stable voltage value, ensuring that the switching power supply 1000 has the ability to adjust the output voltage and improving the performance of the switching power supply 1000.

[0091] The second control signal TCOT2 is used to represent the duration of the on-time or off-time of the switching power supply 1000 in the next switching cycle.

[0092] For example, when adjusting the signal Q <n:1>When determining whether the on-time or off-time needs to be extended in the next switching cycle, the COT control circuit 130 can adjust the signal Q <n:1>, prolonging the timing of the on-time or off-time in the next switching cycle, so that the on-time or off-time in the next switching cycle is prolonged, so that the COT control circuit 130 can obtain the second control signal TCOT2. For multiple switching cycles, if the adjustment signal Q <n:1>To determine the length of time for which the on-time or off-time needs to be extended in the next switching cycle, the COT control circuit 130 counts the on-time or off-time longer and longer, thereby achieving a spread spectrum of the switching frequency.

[0093] When the adjustment signal Q <n:1>When it is determined that there is no need to extend the on-time or off-time in the next switching cycle, the COT control circuit 130 can adjust the signal Q <n:1>, the timing of the on-time or off-time in the next switching cycle is not extended, so that the on-time or off-time in the next switching cycle is reduced, so that the COT control circuit 130 can obtain the second control signal TCOT2. For multiple switching cycles, if the adjustment signal Q <n:1>To determine that there is no need to extend the on-time or off-time in the next switching cycle, the COT control circuit 130 shortens the on-time or off-time until the spread spectrum of the switching frequency is completely exited.

[0094] The detection and regulation circuit provided in the present application obtains a square wave signal from a pulse width modulation comparator through the detection circuit, indicating that the switching power supply is in a constant on-time control mode or a constant off-time control mode, and obtains a first control signal from a COT control circuit, indicating the duration of the on-time or off-time of the switching power supply in the previous switching cycle. Based on the square wave signal and the first control signal, a detection signal is obtained to indicate whether the switching power supply has entered a minimum off-time or minimum on-time in the previous switching cycle, and the detection signal is transmitted to the regulation circuit so that the regulation circuit can obtain the detection signal. In this way, the regulation circuit can obtain a clock signal from the detection circuit in the next switching cycle, obtain a regulation signal based on the clock signal and the detection signal, and transmit the regulation signal to the COT control circuit to determine whether the on-time or off-time in the next switching cycle needs to be extended, so that the COT control circuit can obtain the regulation signal. Furthermore, the COT control circuit can generate a second control signal based on the adjustment signal, representing the duration of the switching power supply's on-time or off-time in the next switching cycle. This changes the on-time or off-time of the pulse-width modulation signal generated based on the second control signal and the square wave signal in the next switching cycle, thereby changing the switching cycle of the switching power supply and dynamically adjusting its switching frequency. This ensures that the output voltage of the switching power supply reaches a preset stable voltage value, ensuring the switching power supply's ability to regulate the output voltage and improving its performance.

[0095] The first control signal TCOT1 may include: a first sub-control signal TCOT1-1 and a second sub-control signal TCOT1-2. The detection signal DROP may include: a first detection signal DROP1 and a second detection signal DROP2. The clock signal may include: a first clock signal and a second clock signal. The adjustment signal Q <n:1>May include: first adjustment signal Q1 <n:1>and the second adjustment signal Q2 <n:1>The second control signal TCOT2 may include a third sub-control signal TCOT2-1 and a fourth sub-control signal TCOT2-2.

[0096] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant on-time control mode, the detection circuit 110 can obtain the first detection signal DROP1 based on the square wave signal CMPO and the first sub-control signal TCOT1-1, and transmit the first detection signal DROP1 to the regulation circuit 120, so that the regulation circuit 120 can obtain the first detection signal DROP1.

[0097] The first sub-control signal TCOT1-1 is used to indicate the duration of the on-time of the switching power supply 1000 in the previous switching cycle, and the first detection signal DROP1 is used to indicate whether the switching power supply 1000 enters the minimum off-time Toff_min2 in the previous switching cycle.

[0098] In this way, the regulating circuit 120 can obtain the first regulating signal Q1 according to the first clock signal and the first detection signal DROP1 in the next switching cycle. <n:1>, and transmits the first adjustment signal Q1 to the COT control circuit 130 <n:1>, so that the COT control circuit 130 can obtain the first adjustment signal Q1 <n:1>.

[0099] Among them, the first adjustment signal Q1 <n:1>Used to determine whether it is necessary to extend the on-time in the next switching cycle.

[0100] Thus, the COT control circuit 130 can adjust the first signal Q1 according to <n:1>, and obtain the third sub-control signal TCOT2-1.

[0101] The third sub-control signal TCOT2-1 is used to represent the duration of the on-time of the switching power supply 1000 in the next switching cycle.

[0102] Based on this, when the square wave signal indicates that the switching power supply is in constant on-time control mode, the detection circuit can, based on the square wave signal and a first sub-control signal indicating the on-time duration of the switching power supply in the previous switching cycle, obtain a first detection signal indicating whether the switching power supply entered the minimum off-time state in the previous switching cycle. The detection circuit can then transmit the first detection signal to the regulation circuit, allowing the regulation circuit to obtain the first detection signal. Consequently, in the next switching cycle, the regulation circuit can, based on the first clock signal and the first detection signal, obtain a first adjustment signal for determining whether the on-time duration in the next switching cycle needs to be extended. The detection circuit can then transmit the first adjustment signal to the COT control circuit, allowing the COT control circuit to obtain the first adjustment signal. Furthermore, the COT control circuit can, based on the first adjustment signal, obtain a third sub-control signal indicating the on-time duration of the switching power supply in the next switching cycle. Thus, the COT control circuit can obtain the third sub-control signal.

[0103] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant off-time control mode, the detection circuit 110 can obtain the second detection signal DROP2 based on the square wave signal CMPO and the second sub-control signal TCOT1-2, and transmit the second detection signal DROP2 to the regulation circuit 120, so that the regulation circuit 120 can obtain the second detection signal DROP2.

[0104] The second sub-control signal TCOT1-2 is used to indicate the duration of the off time of the switching power supply 1000 in the previous switching cycle, and the second detection signal DROP2 is used to indicate whether the switching power supply 1000 enters the minimum on time Ton_min2 in the previous switching cycle.

[0105] In this way, the regulating circuit 120 can obtain the second regulating signal Q2 according to the second clock signal and the second detection signal DROP2 in the next switching cycle. <n:1>, and transmits the second adjustment signal Q2 to the COT control circuit 130 <n:1>, so that the COT control circuit 130 can obtain the second adjustment signal Q2 <n:1>.

[0106] Among them, the second adjustment signal Q2 <n:1>Used to determine whether the off time in the next switching cycle needs to be extended.

[0107] Thus, the COT control circuit 130 can adjust the second signal Q2 <n:1>, a fourth sub-control signal TCOT2-2 is obtained, and the fourth sub-control signal TCOT2-2 is used to represent the duration of the conduction time of the switching power supply 1000 in the next switching cycle.

[0108] Based on this, when the square wave signal indicates that the switching power supply is in constant off-time control mode, the detection circuit can obtain a second detection signal indicating whether the switching power supply entered minimum on-time during the previous switching cycle based on the square wave signal and the second sub-control signal indicating the duration of the switching power supply's off-time during the previous switching cycle. The detection circuit can then transmit the second detection signal to the regulation circuit, allowing the regulation circuit to obtain the second detection signal. Consequently, during the next switching cycle, the regulation circuit can obtain a second adjustment signal for determining whether the duration of the off-time during the next switching cycle needs to be extended based on the second clock signal and the second detection signal. The second adjustment signal can then be transmitted to the COT control circuit, allowing the COT control circuit to obtain the second adjustment signal. Furthermore, the COT control circuit can obtain a fourth sub-control signal indicating the duration of the switching power supply's on-time during the next switching cycle based on the second adjustment signal. Consequently, the COT control circuit 130 can obtain the fourth sub-control signal.

[0109] Based on the description of the above embodiment, a possible implementation of the detection circuit 110 is exemplified. Figure 1 As shown, the detection circuit 110 may include: a detection control component 111 , a clock signal output component 112 and a detection signal output component 113 .

[0110] The first input terminal of the detection and control component 111 is electrically connected to the output terminal of the pulse width modulation comparator PWM Comp, the second input terminal of the detection and control component 111 is electrically connected to the output terminal of the COT control circuit 130, the input terminal of the clock signal output component 112 is electrically connected to the first output terminal or the second output terminal of the detection and control component 111, the output terminal of the clock signal output component 112 is electrically connected to the second input terminal of the regulation circuit 120 and the first input terminal of the detection signal output component 113 respectively, the second input terminal of the detection signal output component 113 is used to access the power supply voltage VDD, and the output terminal of the detection signal output component 113 is electrically connected to the first input terminal of the regulation circuit 120.

[0111] Among them, the first input end of the detection control component 111 is the first input end of the detection circuit 110, the second input end of the detection control component 111 is the second input end of the detection circuit 110, the output end of the detection signal output component 113 is the first output end of the detection circuit 110, and the output end of the clock signal output component 112 is the second output end of the detection circuit 110.

[0112] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant on-time control mode, the detection and control component 111 can control the first output terminal of the detection and control component 111 to be electrically connected to the input terminal of the clock signal output component 112. Furthermore, the detection and control component 111 can obtain the first pulse-width modulation signal PWM1 based on the square wave signal CMPO and the first sub-control signal TCOT1-1, and transmit the first pulse-width modulation signal PWM1 to the clock signal output component 112, so that the clock signal output component 112 can obtain the first pulse-width modulation signal PWM1.

[0113] In this way, the clock signal output component 112 can transmit the first clock signal to the detection signal output component 113 according to the first pulse width modulation signal PWM1, so that the detection signal output component 113 can obtain the first clock signal.

[0114] Furthermore, the detection signal output component 113 can detect whether the switching power supply 1000 enters the minimum off time Toff_min2 in the previous switching cycle according to the first clock signal, and obtain the first detection signal DROP1. Therefore, the detection circuit 110 can obtain the first detection signal DROP1.

[0115] Based on this, when the square wave signal indicates that the switching power supply is in constant on-time control mode, the detection and control component can control the first output terminal of the detection and control component to be electrically connected to the input terminal of the clock signal output component, and based on the square wave signal and the first sub-control signal, obtain a first pulse-width modulated signal, and transmit the first pulse-width modulated signal to the clock signal output component, so that the clock signal output component can obtain the first pulse-width modulated signal. In this way, the clock signal output component can transmit the first clock signal to the detection signal output component based on the first pulse-width modulated signal, so that the detection signal output component can obtain the first clock signal. Furthermore, the detection signal output component can detect whether the switching power supply entered the minimum off-time during the previous switching cycle based on the first clock signal, and obtain a first detection signal. As a result, the detection circuit can obtain the first detection signal.

[0116] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant off-time control mode, the detection and control component 111 can control the second output end of the detection and control component 111 to be electrically connected to the input end of the clock signal output component 112, and the detection and control component 111 can obtain the second pulse width modulation signal PWM2 based on the square wave signal CMPO and the first control signal TCOT1, and transmit the second pulse width modulation signal PWM2 to the clock signal output component 112, so that the clock signal output component 112 can obtain the second pulse width modulation signal PWM2.

[0117] In this way, the clock signal output component 112 can transmit the second clock signal to the detection signal output component 113 according to the second pulse width modulation signal PWM2, so that the detection signal output component 113 can obtain the second clock signal.

[0118] Furthermore, the detection signal output component 113 can detect whether the switching power supply 1000 enters the minimum on-time Ton_min2 in the previous switching cycle according to the second clock signal, and obtain the second detection signal DROP2. Therefore, the detection circuit 110 can obtain the second detection signal DROP2.

[0119] Based on this, when the square wave signal indicates that the switching power supply is in constant off-time control mode, the detection and control component can control the second output terminal of the detection and control component to be electrically connected to the input terminal of the clock signal output component, and based on the square wave signal and the second sub-control signal, obtain a second pulse-width modulated signal, and transmit the second pulse-width modulated signal to the clock signal output component, so that the clock signal output component can obtain the second pulse-width modulated signal. In this way, the clock signal output component can transmit a second clock signal to the detection signal output component based on the second pulse-width modulated signal, so that the detection signal output component can obtain the second clock signal. Furthermore, the detection signal output component can detect whether the switching power supply entered the minimum on-time during the previous switching cycle based on the second clock signal, and obtain a second detection signal. As a result, the detection circuit can obtain the second detection signal.

[0120] Based on the description of the above embodiment, a possible implementation of the detection control component 111 is exemplified. Figure 1 As shown, the detection control component 111 may include: a first trigger SR.

[0121] The set terminal S of the first flip-flop SR is electrically connected to the output terminal of the pulse width modulation comparator PWM Comp, the reset terminal R of the first flip-flop SR is electrically connected to the output terminal of the COT control circuit 130, and the positive output terminal Q or the reverse output terminal QZ of the first flip-flop SR is electrically connected to the input terminal of the clock signal output component 112.

[0122] Among them, the set end S of the first trigger SR is the first input end of the detection control component 111, the reset end R of the first trigger SR is the second input end of the detection control component 111, the forward output end Q of the first trigger SR is the first output end of the detection control component 111, and the reverse output end QZ of the first trigger SR is the second output end of the detection control component 111.

[0123] Based on the description of the above embodiment, a possible implementation of the clock signal output component 112 is exemplified. Figure 1 As shown, the clock signal output component 112 may include: a first switch tube S1, a second switch tube S2 and a first inverter INV1.

[0124] The first end of the second switch tube S2 is electrically connected to the first output end or the second output end of the detection control component 111, and the second end of the second switch tube S2 is electrically connected to the first end of the first switch tube S1 and the input end of the first inverter INV1 respectively. The second end of the first switch tube S1 and the output end of the first inverter INV1 are both electrically connected to the first input end of the detection signal output component 113. The control end of the first switch tube S1 and the control end of the second switch tube S2 are both used to receive the switching signal, and the switching signal is used to control the conduction or shutdown of the switch tube.

[0125] The first end of the second switch tube S2 is the input end of the clock signal output component 112 , and the second end of the first switch tube S1 and the output end of the first inverter INV1 are both output ends of the clock signal output component 112 .

[0126] The first switch transistor S1 and the second switch transistor S2 may include but are not limited to gallium nitride transistors, bipolar junction transistors, insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors, field-controlled thyristors, gate turn-off thyristors and transmission gates.

[0127] For example, when the first switch tube S1 and the second switch tube S2 are gallium nitride transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gates of the gallium nitride transistors, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the drain or source of the gallium nitride transistors, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the source or drain of the gallium nitride transistors.

[0128] For example, when the first switch tube S1 and the second switch tube S2 are bipolar junction transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the base of the bipolar junction transistor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the collector or emitter of the bipolar junction transistor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the emitter or collector of the bipolar junction transistor.

[0129] For example, when the first switch tube S1 and the second switch tube S2 are insulated gate bipolar transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gates of the insulated gate bipolar transistors, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the collector or emitter of the insulated gate bipolar transistors, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the emitter or collector of the insulated gate bipolar transistors.

[0130] For example, when the first switch tube S1 and the second switch tube S2 are metal-oxide semiconductor field-effect transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the metal-oxide semiconductor field-effect transistor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the drain or source of the metal-oxide semiconductor field-effect transistor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the source or drain of the metal-oxide semiconductor field-effect transistor.

[0131] For example, when the first switch tube S1 and the second switch tube S2 are field-controlled thyristors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the field-controlled thyristor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the drain or source of the field-controlled thyristor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the source or drain of the field-controlled thyristor.

[0132] For example, when the first switching tube S1 and the second switching tube S2 are gate-turn-off thyristors, the control end of the first switching tube S1 and the control end of the second switching tube S2 refer to the gates of the gate-turn-off thyristors, the first end of the first switching tube S1 and the first end of the second switching tube S2 can be the cathodes or anodes of the gate-turn-off thyristors, and correspondingly, the second end of the first switching tube S1 and the second end of the second switching tube S2 can be the cathodes or anodes of the gate-turn-off thyristors.

[0133] For example, when the first switch tube S1 and the second switch tube S2 are transmission gates, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the ports of the transmission gate used to access the gate control signal. The first end of the first switch tube S1 and the first end of the second switch tube S2 can be the input end or the output end of the transmission gate, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the input end or the output end of the transmission gate.

[0134] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant on-time control mode, the first switch S1 is always on. When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant off-time control mode, the first switch S1 is always off.

[0135] Based on the description of the above embodiment, a possible implementation of the detection signal output component 113 is exemplified. Figure 1 As shown, the detection signal output component 113 may include: a second inverter INV2 , a delay device and a second flip-flop DFF.

[0136] The input end of the second inverter INV2 and the input end of the delay device are both electrically connected to the output end of the clock signal output component 112, the output end of the second inverter INV2 is electrically connected to the clock input end of the second trigger DFF, the output end of the delay device is electrically connected to the set input end of the second trigger DFF, the data input end of the second trigger DFF is used to access the power supply voltage VDD, and the output end of the second trigger DFF is electrically connected to the first input end of the adjustment circuit 120.

[0137] Among them, the input end of the second inverter INV2 and the input end of the delay device are both the first input end of the detection signal output component 113, the data input end of the second trigger DFF is the second input end of the detection signal output component 111, and the output end of the second trigger DFF is the output end of the detection signal output component 113.

[0138] Based on the description of the above embodiment, a possible implementation of the regulating circuit 120 is exemplified. Figure 1 As shown, the regulating circuit 120 may include: an Up Down Counter.

[0139] The clock input of the counter Up Down Counter is electrically connected to the second output of the detection circuit 110 , the count input of the counter Up Down Counter is electrically connected to the first output of the detection circuit 110 , and the output of the counter Up Down Counter is electrically connected to the input of the COT control circuit 130 .

[0140] The clock input of the counter Up Down Counter is the second input of the regulating circuit 120 , the counting input of the counter Up Down Counter is the first input of the regulating circuit 120 , and the output of the counter Up Down Counter is the output of the regulating circuit 120 .

[0141] The counter Up Down Counter can obtain the first clock signal from the detection circuit 110 in the next switching cycle, and determine whether to count up the first value of the counter Up Down Counterer according to the first detection signal DROP1 at the rising edge of the first clock signal to obtain the first adjustment signal Q1 <n:1>.

[0142] Alternatively, the counter Up Down Counter can obtain the second clock signal from the detection circuit 110 in the next switching cycle. Moreover, at the rising edge of the second clock signal, the counter Up Down Counter determines whether to count up the first value of the counter Up Down Counter according to the second detection signal DROP2 to obtain the second adjustment signal Q2. <n:1>.

[0143] For example, in the second switching cycle, the first value is the value output by the counter Up Down Counter in the first switching cycle, that is, the first value is the value of the adjustment signal Q in the first switching cycle. <n:1>For example, in the fourth switching cycle, the first value is the value output by the counter Up Down Counter in the third switching cycle, that is, the first value is the value of the adjustment signal Q in the third switching cycle. <n:1>The corresponding numerical value.

[0144] In summary, during the next switching cycle, the counter can obtain the first clock signal from the detection circuit and, at the rising edge of the first clock signal, determine based on the first detection signal whether to count up the first value of the counter to obtain the first adjustment signal. Alternatively, during the next switching cycle, the counter can obtain the second clock signal from the detection circuit and, at the rising edge of the second clock signal, determine based on the second detection signal whether to count up the first value of the counter to obtain the second adjustment signal. Thus, the adjustment circuit can obtain the first adjustment signal or the second adjustment signal.

[0145] Based on the description of the above embodiment, a possible implementation of the regulating circuit 120 is exemplified. Figure 1 As shown, the regulating circuit 120 may further include: a frequency divider.

[0146] An input end of the frequency divider Divider is electrically connected to the second output end of the detection circuit 110 , and an output end of the frequency divider Divider is electrically connected to a clock input end of the counter Up Down Counter.

[0147] The frequency divider Divider can divide the first clock signal to obtain a first divided clock signal PWM_DIV1. Furthermore, the frequency divider Divider can transmit the first divided clock signal PWM_DIV1 to the counter Up Down Counter, so that the counter Up Down Counter can obtain the first adjustment signal Q1. <n:1>.

[0148] Alternatively, the frequency divider Divider can divide the second clock signal to obtain a second divided clock signal PWM_DIV2. Furthermore, the frequency divider Divider can transmit the second divided clock signal PWM_DIV2 to the counter Up Down Counter, so that the counter Up Down Counter can obtain the second adjustment signal Q2. <n:1>.

[0149] The first divided clock signal PWM_DIV1 and the second divided clock signal PWM_DIV2 are both divided clock signals PWM_DIV. The divided clock signal PWM_DIV output by the divider can reduce the adjustment signal Q <n:1>The change speed of the COT control circuit 130 is prevented from being adjusted too quickly and causing jitter in the output voltage VOUT2.

[0150] Based on the description of the above embodiment, a possible implementation of the COT control circuit 130 is exemplified. Figure 2 , Figure 2 This is a schematic diagram of the structure of a COT control circuit in a detection and regulation circuit provided in an embodiment of the present application. Figure 2 As shown, the COT control circuit 130 may include: a current output component 131 , a capacitor Ccot and a timing comparator COT COMP.

[0151] The control end of the current output component 131 is electrically connected to the output end of the regulation circuit 120, the output end of the current output component 131 is electrically connected to the first plate of the capacitor Ccot, the positive input end of the timing comparator COT COMP is electrically connected between the output end of the current output component 131 and the first plate of the capacitor Ccot, the negative input end of the timing comparator COT COMP is used to connect to the reference voltage Vcot, and the reference voltage Vcot is related to the square wave signal CMPO. The output end of the timing comparator COT COMP is electrically connected to the first input end of the detection circuit 110.

[0152] The control terminal of the current output component 131 is the input terminal of the COT control circuit 130 , and the output terminal of the timing comparator COTCOMP is the output terminal of the COT control circuit 130 .

[0153] The current output component 131 can output a first adjustment signal Q1 <n:1>Furthermore, the current output component 131 can use the first charging current to charge the capacitor Ccot, thereby increasing the voltage on the capacitor Ccot.

[0154] In this way, the timing comparator COT COMP can compare the voltage on the capacitor Ccot with the reference voltage Vcot to obtain the third sub-control signal TCOT2 - 1 .

[0155] Alternatively, the current output component 131 can output a second adjustment signal Q2 <n:1>Furthermore, the current output component 131 can use the second charging current to charge the capacitor Ccot, thereby increasing the voltage on the capacitor Ccot.

[0156] In this way, the timing comparator COT COMP can compare the voltage on the capacitor Ccot with the reference voltage Vcot to obtain the fourth sub-control signal TCOT2-2.

[0157] The first charging current and the second charging current are both charging currents Icot.

[0158] In the case where the square wave signal CMPO indicates that the switching power supply 1000 is in the constant on-time control mode, the reference voltage Vcot is the output voltage VOUT2 of the switching power supply 1000, i.e., Vcot=VOUT2, and the charging current Icot is the ratio between the input voltage VIN2 of the switching power supply 1000 and the resistance Rcot of the current output component 131, i.e., VIN2 / Rcot.

[0159] When the square wave signal CMPO indicates that the switching power supply 1000 is in constant off-time control mode, the reference voltage Vcot is the difference between the input voltage VIN2 of the switching power supply 1000 and the output voltage VOUT2 of the switching power supply 1000, i.e., Vcot = VIN2 - VOUT2. The charging current Icot is the ratio between the input voltage VIN2 of the switching power supply 1000 and the resistance Rcot of the current output component 131, i.e., VIN2 / Rcot.

[0160] In summary, the current output component can output a first charging current corresponding to the first adjustment signal and use the first charging current to charge the capacitor. In this way, the timing comparator can compare the voltage across the capacitor with the reference voltage to obtain a third sub-control signal, enabling the COT control circuit to obtain the third sub-control signal. Alternatively, the current output component can output a second charging current corresponding to the second adjustment signal and use the second charging current to charge the capacitor. In this way, the timing comparator can compare the voltage across the capacitor with the reference voltage to obtain a fourth sub-control signal, enabling the COT control circuit to obtain the fourth sub-control signal. Consequently, the COT control circuit can obtain either the third sub-control signal or the fourth sub-control signal.

[0161] Based on the description of the above embodiment, a possible implementation of the current output component 131 is exemplified. Figure 2 As shown, the current output component 131 may include: a current source, a first N-type transistor Mx, a second N-type transistor M0, a first P-type transistor MP1, a second P-type transistor MP2, multiple N-type transistor groups and multiple third inverters INV3.

[0162] The output end of the current source is electrically connected to the drain end of the first N-type transistor Mx. The gate end of the first N-type transistor Mx is electrically connected to the gate end of the second N-type transistor M0 and the first gate end of each N-type transistor group. The drain end of the first N-type transistor Mx is electrically connected to the drain end of each N-type transistor group, the drain end of the first P-type transistor MP1, the gate end of the first P-type transistor MP1, and the gate end of the second P-type transistor MP2. The drain end of the second P-type transistor MP2 is electrically connected to the first plate of the capacitor Ccot. The source end of the first P-type transistor MP1 and the source end of the second P-type transistor MP2 are both used to access the power supply voltage VDD. The second gate end of each N-type transistor group is electrically connected to the output end of each third inverter INV3. The input end of each third inverter INV3 is electrically connected to the output end of the regulation circuit 120. The source end of the first N-type transistor Mx, the source end of the second N-type transistor M0, and the source end of each N-type transistor group are all grounded.

[0163] In some examples, each N-type transistor group may include: a transistor Ms and a transistor M.

[0164] The drain terminal of the transistor Ms is electrically connected to the drain terminal of the first N-type transistor Mx, the gate terminal of the transistor Ms is electrically connected to the output terminal of the third inverter INV3, the source terminal of the transistor Ms is electrically connected to the drain terminal of the transistor M, the gate terminal of the transistor Ms is electrically connected to the gate terminal of the second N-type transistor M0, and the source terminal of the transistor M is grounded.

[0165] In some examples, the number of first N-type transistors Mx is the sum of the number of second N-type transistors M0 and multiple N-type transistor groups, and the number of first P-type transistors MP1 is equal to the number of second P-type transistors MP2.

[0166] The number of second N-type transistors M0 determines the maximum timing time of the COT control circuit 130 for the on-time or off-time within the switching cycle. In other words, the number of second N-type transistors M0 is related to the maximum duration of the on-time or off-time of the switching power supply 1000. The n current mirrors are formed by the first N-type transistor Mx and multiple N-type transistor groups. The value of the number n of current mirrors affects the step size of the frequency modulation of the switching frequency. When the number n of current mirrors is larger, the step size of each timing adjustment by the COT control circuit 130 is shorter. The shorter the step size, the smaller the jitter of the output voltage VOUT2. In other words, the number of multiple N-type transistor groups is related to the step size of the switching frequency adjustment.

[0167] When the counter Up Down Counter outputs the adjustment signal Q <n:1>When the corresponding values ​​are all 0, the output signal of each third inverter INV3 is high, turning on transistors Ms1, Ms2, Msn, and so on. Thus, the reference current Icot-ef output by the current source is mirrored proportionally by the current mirror group formed by the first N-type transistor Mx, the second N-type transistor M0, and the multiple N-type transistor groups. The resulting charging current Icot charges the capacitor Ccot, preventing the COT control circuit 130 from extending the on-time or off-time timing within the switching cycle.

[0168] When the output of the counter Up Down Counter is adjusted, the signal Q <n:1>As the corresponding value gradually increases, the output signal of each third inverter INV3 gradually becomes low, causing transistors Ms1, Ms2, through Msn to be gradually turned off. Thus, the charging current Icot, obtained by mirroring the reference current Icot-ef output by the current source at a reduced ratio through the current mirror formed by the first N-type transistor Mx, the second N-type transistor M0, and the multiple N-type transistor groups, gradually decreases. This causes the COT control circuit 130 to extend the time it measures the on-time or off-time within the switching cycle, thereby extending the time and achieving the purpose of frequency spread.

[0169] When the output of the counter Up Down Counter is adjusted, the signal Q <n:1>When the corresponding values ​​are all 1, the adjustment signal Q <n:1>When the corresponding value reaches its maximum, the output signal of each third inverter INV3 is low, turning off transistors Ms1, Ms2, Msn, and so on. This minimizes the reduction ratio, minimizes the charging current Icot, and maximizes the delay time for the COT control circuit 130 to measure the on-time or off-time within the switching cycle.

[0170] The following combination Figure 3 , Figure 3 This is a detection timing diagram of a detection and regulation circuit provided in one embodiment of the present application. The working principle of the detection and regulation circuit 1000 when the switching power supply 1000 is in a constant on-time control mode is described in detail as follows:

[0171] The first pulse-width modulation signal PWM1 is generated by the square wave signal CMPO and the control signal TCOT. When the switching power supply 1000 is in constant on-time control mode, the first switch S1 is turned on, and the second switch S2 is electrically connected to the non-inverting output terminal Q of the first flip-flop SR. The detection circuit 110 detects whether the switching power supply 1000 has entered the minimum off-time Toff_min2 after the first pulse-width modulation signal PWM1 is at a low level.

[0172] At time t0, control signal TCOT is low, current iL1 in inductor L1 drops to its valley current, square wave signal CMPO is high, and the positive-inverting output terminal Q of first flip-flop SR outputs a high level, turning first pulse-width modulation signal PWM1 high. This turns the top transistor on and the bottom transistor off. At this moment, COT control circuit 130 begins timing the on-time Ton1 of the first switching cycle Tsw1.

[0173] During the period t0-t1, the COT control circuit 130 times the on-time Ton1 in the first switching cycle Tsw1. That is, the control signal TCOT during this period represents the duration of the on-time Ton1 of the switching power supply 1000 in the first switching cycle Tsw1.

[0174] At time t1, the control signal TCOT is high, the square wave signal CMPO is low, and the positive-phase output Q of the first flip-flop SR outputs a low level, causing the first pulse-width modulation signal PWM1 to be low, turning off the upper transistor and turning on the lower transistor. At this moment, the COT control circuit 130 ends timing the on-time Ton1 of the first switching cycle Tsw1. At this moment, when the first pulse-width modulation signal PWM1 transitions from high to low, a rising edge is input to the clock input of the second flip-flop DFF, setting the output of the second flip-flop DFF to a high level and the first detection signal DROP1 to a high level. In other words, the switching power supply 1000 enters the minimum off-time Toff_min2 state.

[0175] During the time period t1-t2, the duration of this period is the off time in the first switching cycle Tsw1.

[0176] During the time period t0-t2, the duration of this period is the first switching cycle Tsw1.

[0177] At time t2, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the positive phase output terminal Q of the first flip-flop SR outputs a high level, making the first pulse width modulation signal PWM1 high, turning on the upper tube and turning off the lower tube. At this moment, the COT control circuit 130 begins timing the on-time Ton2 of the second switching cycle Tsw2. At this moment, when the first pulse width modulation signal PWM1 changes from a low level to a high level, a rising edge is input to the clock input terminal of the counter Up Down Counter, causing the counter Up Down Counter to count up the first value. In this way, the first adjustment signal Q1 output by the counter Up Down Counter is <n:1>The first charging current decreases, so that the COT control circuit 130 prolongs the timing of the on-time Ton2 in the second switching period Tsw2.

[0178] During the time period t1-t3, the length of this period is the delay time Tdly of the delay device. Since the off time in the first switching cycle Tsw1 is less than the delay time Tdly of the delay device, the first detection signal DROP1 cannot be set to a low level during the off time in the first switching cycle Tsw1.

[0179] During the period t2-t4, the COT control circuit 130 measures the on-time Ton2 within the second switching cycle Tsw2. Specifically, the control signal TCOT during this period represents the duration of the on-time Ton2 of the switching power supply 1000 within the second switching cycle Tsw2. Because the COT control circuit 130 extends the timing of the on-time Ton2 within the second switching cycle Tsw2, the on-time Ton2 is longer than the on-time Ton1, thereby achieving frequency spread.

[0180] At time t4, control signal TCOT is high, square wave signal CMPO is low, and the positive-phase output terminal Q of the first flip-flop SR outputs a low level, causing the first pulse-width modulation signal PWM1 to be low, turning off the upper transistor and turning on the lower transistor. At this moment, COT control circuit 130 ends timing the on-time Ton2 of the second switching cycle Tsw2. At this moment, when the first pulse-width modulation signal PWM1 transitions from high to low, a rising edge is input to the clock input terminal of the second flip-flop DFF, causing the output terminal of the second flip-flop DFF to be high, thus setting the first detection signal DROP1 to a high level.

[0181] During the period t4-t5, after the on-time Ton1 is extended, the loop will readjust the off-time to obtain the off-time within the second switching cycle Tsw2. This period is the off-time within the second switching cycle Tsw2.

[0182] During the time period t2-t5, the duration of this period is the second switching cycle Tsw2.

[0183] At time t5, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the positive phase output terminal Q of the first flip-flop SR outputs a high level, making the first pulse width modulation signal PWM1 at a high level, turning on the upper tube and turning off the lower tube. At this moment, the COT control circuit 130 begins timing the on-time Ton3 of the third switching cycle Tsw3. At this moment, when the first pulse width modulation signal PWM1 changes from a low level to a high level, a rising edge is input to the clock input terminal of the counter Up Down Counter, causing the counter Up Down Counter to continue counting upwards. In this way, the first adjustment signal Q1 output by the counter Up Down Counter is <n:1>The first charging current continues to increase, causing the first charging current to continue to decrease, so that the COT control circuit 130 continues to extend the timing of the on-time Ton3 in the third switching cycle Tsw3.

[0184] During the time period T4-t6, which is equal to the delay time Tdly of the delay device, the first detection signal DROP1 cannot be set to a low level during the off time of the second switching cycle Tsw2 because the off time of the second switching cycle Tsw2 is less than the delay time Tdly of the delay device.

[0185] At time t7, the control signal TCOT is high, the square wave signal CMPO is low, and the non-inverting output Q of the first flip-flop SR outputs a low level, causing the first pulse-width modulation signal PWM1 to be low, turning off the upper transistor and turning on the lower transistor. At this moment, the COT control circuit 130 ends timing the on-time Ton3 of the third switching cycle Tsw3. At this moment, when the first pulse-width modulation signal PWM1 transitions from high to low, a rising edge is input to the clock input of the second flip-flop DFF, setting the output of the second flip-flop DFF to a high level and causing the first detection signal DROP1 to be high.

[0186] During the time period t7-t8, the length of this period is the delay time Tdly of the delay device.

[0187] At time t8, because the off-time in the third switching cycle Tsw3 exceeds the delay time Tdly of the delay device, the set input of the second flip-flop DFF is at a low level. Therefore, the first detection signal DROP1 is reset to a low level during the off-time in the third switching cycle Tsw3. In other words, the switching power supply 1000 is not in the state of entering the minimum off-time Toff_min2.

[0188] During the period t7-t9, after the on-time Ton2 is extended, the loop will readjust the off-time to obtain the off-time within the third switching cycle Tsw3. This period is the off-time within the third switching cycle Tsw3.

[0189] During the time period from t5 to t9, the duration of this period is the third switching cycle Tsw3.

[0190] After time t9, since the off time after the third switching cycle Tsw3 is greater than the delay time Tdly, the first detection signal DROP1 will be built into a low level during the off time, making the first adjustment signal Q1 output by the counter Up Down Counter <n:1>It will gradually decrease until it completely exits the spread spectrum.

[0191] Based on the above description, it can be seen that by setting the delay time Tdly equal to the minimum off-time Toff_min2, the detection of the minimum off-time Toff_min2 is achieved.

[0192] The following combination Figure 4 , Figure 4 This is a detection timing diagram of another detection and regulation circuit provided in an embodiment of the present application. The working principle of the detection and regulation circuit 1000 when the switching power supply 1000 is in a constant off-time control mode is described in detail as follows:

[0193] When switching power supply 1000 is in constant off-time control mode, first switch S1 is turned off, causing first inverter INV1 to enter control logic. Second switch S2 is electrically connected to negative output terminal QZ of first flip-flop SR. Detection circuit 110 detects whether switching power supply 1000 enters minimum on-time Ton_min2 after first pulse-width modulation signal PWM1 reaches a high level.

[0194] At time t0, control signal TCOT is low, current iL1 in inductor L1 increases to its peak current, square wave signal CMPO is high, and the positive-inverting output terminal Q of first flip-flop SR outputs a low level, causing first pulse-width modulation signal PWM1 to be low, turning off the upper transistor and turning on the lower transistor. At this moment, COT control circuit 130 begins timing the off-time Toff1 of the first switching cycle Tsw1.

[0195] During the period t0-t1, the COT control circuit 130 times the off time Toff1 in the first switching cycle Tsw1. That is, the control signal TCOT during this period represents the duration of the off time Toff1 of the switching power supply 1000 in the first switching cycle Tsw1.

[0196] At time t1, the control signal TCOT is high, the square wave signal CMPO is low, and the negative phase output terminal QZ of the first flip-flop SR outputs a high level, causing the second pulse-width modulation signal PWM2 to be high, turning on the upper transistor and turning off the lower transistor. At this moment, the COT control circuit 130 ends timing the off-time Toff1 of the first switching cycle Tsw1. At this moment, when the first pulse-width modulation signal PWM1 transitions from low to high, a rising edge is input to the clock input terminal of the second flip-flop DFF, setting the output terminal of the second flip-flop DFF to a high level and the second detection signal DROP2 to a high level. In other words, the switching power supply 1000 enters the minimum on-time Ton_min2 state.

[0197] During the time period t1-t2, the duration of this period is the on-time of the first switching cycle Tsw1.

[0198] During the time period t0-t2, the duration of this period is the first switching cycle Tsw1.

[0199] At time t2, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the negative phase output terminal QZ of the first flip-flop SR outputs a low level, causing the second pulse width modulation signal PWM2 to be at a low level, turning off the upper tube and turning on the lower tube. At this moment, the COT control circuit 130 begins timing the off time Toff2 of the second switching cycle Tsw2. At this moment, when the second pulse width modulation signal PWM2 changes from a high level to a low level, a rising edge is input to the clock input terminal of the counter Up Down Counter, causing the counter Up Down Counter to count up the first value. In this way, the second adjustment signal Q2 output by the counter Up Down Counter is <n:1>The second charging current decreases, so that the COT control circuit 130 prolongs the timing of the off time Toff2 in the second switching cycle Tsw2.

[0200] During the period t1-t3, the length of this period is the delay time Tdly of the delay device. Since the on-time in the first switching cycle Tsw1 is less than the delay time Tdly of the delay device, the second detection signal DROP2 cannot be set to a low level during the on-time in the first switching cycle Tsw1.

[0201] During the period t2-t4, the COT control circuit 130 measures the off-time Toff2 within the second switching cycle Tsw2. That is, the control signal TCOT during this period represents the duration of the off-time Toff2 of the switching power supply 1000 within the second switching cycle Tsw2. Because the COT control circuit 130 extends the timing of the off-time Toff2 within the second switching cycle Tsw2, the off-time Toff2 is longer than the off-time Toff1, thereby achieving frequency spread.

[0202] At time t4, control signal TCOT is high, square wave signal CMPO is low, and negative phase output terminal QZ of first flip-flop SR outputs a high level, causing second pulse-width modulation signal PWM2 to be high, turning on the upper transistor and turning off the lower transistor. At this moment, COT control circuit 130 ends timing the off-time Toff2 of the second switching cycle Tsw2. At this moment, when second pulse-width modulation signal PWM2 transitions from low to high, a rising edge is input to the clock input terminal of second flip-flop DFF, causing the output terminal of second flip-flop DFF to be high, thus causing second detection signal DROP2 to be high.

[0203] During the period t4-t5, after the off-time Toff1 is extended, the loop will readjust the on-time to obtain the on-time in the second switching cycle Tsw2. This period is the on-time in the second switching cycle Tsw2.

[0204] During the time period t2-t5, the duration of this period is the second switching cycle Tsw2.

[0205] At time t5, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the negative phase output terminal QZ of the first flip-flop SR outputs a low level, making the second pulse width modulation signal PWM2 at a low level, turning off the upper tube and turning on the lower tube. At this moment, the COT control circuit 130 begins timing the off time Toff3 of the third switching cycle Tsw3. At this moment, when the second pulse width modulation signal PWM1 changes from a high level to a low level, a rising edge is input to the clock input terminal of the counter Up Down Counter, causing the counter Up Down Counter to continue counting upwards. In this way, the second adjustment signal Q2 output by the counter Up Down Counter is <n:1>The second charging current continues to increase, causing the second charging current to continue to decrease, so that the COT control circuit 130 continues to extend the timing of the off time Toff3 in the third switching cycle Tsw3.

[0206] During the time period T4-t6, which is equal to the delay time Tdly of the delay device, the second detection signal DROP2 cannot be set to a low level during the on-time of the second switching cycle Tsw2 because the on-time of the second switching cycle Tsw2 is less than the delay time Tdly of the delay device.

[0207] At time t7, control signal TCOT is high, square wave signal CMPO is low, and negative phase output QZ of first flip-flop SR outputs a high level, causing second pulse-width modulation signal PWM2 to be high, turning on the upper transistor and turning off the lower transistor. At this moment, COT control circuit 130 completes timing of off-time Toff3 of the third switching cycle Tsw3. At this moment, when second pulse-width modulation signal PWM1 transitions from low to high, a rising edge is input to the clock input of second flip-flop DFF, causing the output of second flip-flop DFF to be high, thus causing second detection signal DROP2 to be high.

[0208] During the time period t7-t8, the length of this period is the delay time Tdly of the delay device.

[0209] At time t8, because the on-time of the third switching cycle Tsw3 exceeds the delay time Tdly of the delay device, the set input of the second flip-flop DFF is at a low level. Therefore, the second detection signal DROP2 is reset to a low level during the on-time of the third switching cycle Tsw3. In other words, the switching power supply 1000 is not in the state of entering the minimum on-time Ton_min2.

[0210] During the period t7-t9, after the off-time Toff2 is extended, the loop will readjust the on-time to obtain the on-time in the third switching cycle Tsw3. This period is the on-time in the third switching cycle Tsw3.

[0211] During the time period from t5 to t9, the duration of this period is the third switching cycle Tsw3.

[0212] After time t9, since the on-time after the third switching cycle Tsw3 is greater than the delay time Tdly, the second detection signal DROP2 will be built into the low level during the on-time, making the second adjustment signal Q2 output by the counter Up Down Counter <n:1>It will gradually decrease until it completely exits the spread spectrum.

[0213] Based on the above description, it can be seen that by setting the delay time Tdly equal to the minimum on-time Ton_min2, the minimum on-time Ton_min2 can be detected.

[0214] Reference Figure 5 , Figure 5 This is a schematic diagram of the structure of a switching power supply provided in one embodiment of the present application. Figure 5 As shown, the switching power supply 1000 may include: a high-side power transistor M1, a low-side power transistor M2, an inductor L1, an output capacitor Cout, a first resistor Rsns1, a second resistor Rsns2, a pulse width modulation comparator PWM Comp, a controller 300, a loop-controlled current output circuit 200 and a detection and regulation circuit 100.

[0215] The input end of the loop-controlled current output circuit 200 is electrically connected to the second end of the inductor L1 and the first plate of the output capacitor Cout, respectively. The second end of the inductor L1 is also used to output the output voltage VOUT2 of the switching power supply 1000. The output end of the loop-controlled current output circuit 200 is electrically connected to the first end of the first resistor Rsns1. The second end of the first resistor Rsns1 is electrically connected to the negative phase input end of the pulse width modulation comparator PWM Comp. The first end of the second resistor Rsns2 is used to detect the current of the inductor L1. The second end of the second resistor Rsns2 is electrically connected to the positive phase input end of the pulse width modulation comparator PWM Comp. The output end of Comp is electrically connected to the first input end of the detection circuit 110 and the first input end of the controller 300 respectively, the output end of the COT control circuit 130 is electrically connected to the second input end of the controller 300, the first output end of the controller 300 is electrically connected to the control end of the high-side power transistor M1, the second output end of the controller 300 is electrically connected to the control end of the low-side power transistor M2, the first end of the high-side power transistor M1 is used to access the input voltage VIN2 of the switching power supply 1000, the second end of the high-side power transistor M1 is electrically connected to the first end of the low-side power transistor M2, the first end of the inductor L1 is electrically connected between the second end of the high-side power transistor M1 and the first end of the low-side power transistor M2, and the second end of the low-side power transistor M2 and the second plate of the output capacitor Cout are both grounded.

[0216] The high-side power transistor M1 is usually referred to as the upper transistor, and the low-side power transistor M2 is usually referred to as the lower transistor.

[0217] In some examples, the loop-controlled current output circuit 200 may include: a feedback circuit, an error amplifier, a compensation circuit, and a conversion circuit OTA&Ictrl.

[0218] The input end of the feedback circuit is electrically connected to the second end of the inductor L1, the output end of the feedback circuit is electrically connected to the negative input end of the error amplifier EA, the positive input end of the error amplifier EA is used to access the reference voltage VREF, the output end of the error amplifier EA is electrically connected to the input end of the conversion circuit OTA&Ictrl through the compensation circuit, and the output end of the conversion circuit OTA&Ictrl is electrically connected to the first end of the first resistor Rsns1.

[0219] The input end of the feedback circuit is the input end of the loop-controlled current output circuit 200 , and the output end of the conversion circuit OTA&Ictrl is the output end of the loop-controlled current output circuit 200 .

[0220] Exemplarily, the feedback circuit may include: a first feedback resistor RT and a second feedback resistor RB.

[0221] A first end of the first feedback resistor RT is electrically connected to the second end of the inductor L1, a second end of the first feedback resistor RT is electrically connected to a first end of the second feedback resistor RB, a negative input end of the error amplifier EA is electrically connected between the second end of the first feedback resistor RT and the first end of the second feedback resistor RB, and a second end of the second feedback resistor RB is grounded.

[0222] The first end of the first feedback resistor RT is the input end of the feedback circuit, and the output end of the feedback circuit is located between the second end of the first feedback resistor RT and the first end of the second feedback resistor RB.

[0223] Exemplarily, the compensation circuit may include: a resistor Rcmp and a capacitor Ccmp.

[0224] A first end of the resistor Rcmp is electrically connected to the output end of the error amplifier EA, a second end of the resistor Rcmp is electrically connected to a first plate of the capacitor Ccmp, and a second plate of the capacitor Ccmp is grounded.

[0225] Exemplarily, the conversion circuit OTA&Ictrl may include: a transconductance amplifier OTA and a current controller Ictrl.

[0226] The output voltage VOUT2 is sampled through the first feedback resistor RT and the second feedback resistor RB to obtain the feedback voltage VFB. The difference between the feedback voltage VFB and the reference voltage VREF is amplified by the error amplifier EA and filtered by the compensation circuit to obtain the loop compensation voltage Vcmp. The loop compensation voltage Vcmp is converted into a current by the transconductance amplifier OTA and converted into the loop control current Iloop by the current controller Ictrl. In this way, the loop control current Iloop is compared with the sampled current of the inductor L1 to generate a square wave signal COMP. At the same time, the detection and regulation circuit 100 can transmit the control signal TCOT to the controller 300. In this way, the logic processing module logic in the controller 300 can process the square wave signal COMP and the control signal TCOT to obtain the pulse width modulation signal PWM that controls the high-side power transistor M1 and the low-side power transistor M2 to turn on or off.

[0227] The switching power supply provided in the embodiment of the present application has the same beneficial effects as the detection and regulation circuit provided in the embodiment of the present application, which will not be repeated here.

[0228] An embodiment of the present application further provides a chip, including: a detection and regulation circuit, and / or a switching power supply 1000 .

[0229] Among them, the detection and regulation circuit and the switching power supply can be integrated into one chip or into different chips, and the embodiments of the present application do not specifically limit this.

[0230] The chip provided in the embodiment of the present application has the same beneficial effects as the detection and adjustment circuit provided in the embodiment of the present application, and will not be repeated here.

[0231] An embodiment of the present application also provides an electronic device, including: a chip.

[0232] In this application, electronic devices may include but are not limited to: tablet computers, routers, industrial robots and televisions.

[0233] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be repeated here.

[0234] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A detection and adjustment circuit, characterized in that: The detection and regulation circuit is applied to a switching power supply, and the switching power supply includes: a pulse width modulation comparator; the detection and regulation circuit includes: a detection circuit, a regulation circuit and a COT control circuit; The first input terminal of the detection circuit is electrically connected to the output terminal of the pulse width modulation comparator, the second input terminal of the detection circuit is electrically connected to the output terminal of the COT control circuit, the first output terminal of the detection circuit is electrically connected to the first input terminal of the regulation circuit, the second output terminal of the detection circuit is electrically connected to the second input terminal of the regulation circuit, and the output terminal of the regulation circuit is electrically connected to the input terminal of the COT control circuit; The detection circuit is configured to obtain a square wave signal from the pulse width modulation comparator and a first control signal from the COT control circuit, and to obtain a detection signal based on the square wave signal and the first control signal, and transmit the detection signal to the regulation circuit, wherein the square wave signal is used to indicate whether the switching power supply is in a constant on-time control mode or a constant off-time control mode, the first control signal is used to indicate the duration of the on-time or off-time of the switching power supply in a previous switching cycle, and the detection signal is used to indicate whether the switching power supply has entered a minimum off-time or minimum on-time in the previous switching cycle; The regulating circuit is configured to obtain a clock signal from the detection circuit in a subsequent switching cycle, obtain a regulating signal based on the clock signal and the detection signal, and transmit the regulating signal to the COT control circuit, wherein the regulating signal is used to determine whether it is necessary to extend the duration of the on-time or the off-time in the subsequent switching cycle; The COT control circuit is used to obtain a second control signal based on the adjustment signal to dynamically adjust the switching frequency of the switching power supply, and the second control signal is used to represent the duration of the on-time or off-time of the switching power supply in the subsequent switching cycle.

2. The circuit according to claim 1, characterized in that The first control signal includes: a first sub-control signal and a second sub-control signal; the detection signal includes: a first detection signal and a second detection signal; the clock signal includes: a first clock signal and a second clock signal; the adjustment signal includes: a first adjustment signal and a second adjustment signal; the second control signal includes: a third sub-control signal and a fourth sub-control signal; The detection circuit is specifically configured to, when the square wave signal indicates that the switching power supply is in the constant on-time control mode, obtain a first detection signal based on the square wave signal and the first sub-control signal, and transmit the first detection signal to the regulation circuit, wherein the first sub-control signal is used to indicate a duration of the on-time of the switching power supply in the previous switching cycle, and the first detection signal is used to indicate whether the switching power supply entered the minimum off-time in the previous switching cycle; The regulating circuit is specifically configured to obtain, in the subsequent switching cycle, the first regulating signal according to the first clock signal and the first detection signal, and transmit the first regulating signal to the COT control circuit, wherein the first regulating signal is used to determine whether the on-time in the subsequent switching cycle needs to be extended; The COT control circuit is specifically configured to obtain the third sub-control signal according to the first adjustment signal, wherein the third sub-control signal is used to represent the duration of the on-time of the switching power supply in the subsequent switching cycle; or, The detection circuit is specifically configured to, when the square wave signal indicates that the switching power supply is in the constant off-time control mode, obtain a second detection signal based on the square wave signal and the second sub-control signal, and transmit the second detection signal to the regulation circuit, wherein the second sub-control signal is used to indicate the duration of the off-time of the switching power supply in the previous switching cycle, and the second detection signal is used to indicate whether the switching power supply entered the minimum on-time in the previous switching cycle; The regulating circuit is specifically configured to obtain, in the subsequent switching cycle, the second regulating signal according to the second clock signal and the second detection signal, and transmit the second regulating signal to the COT control circuit, wherein the second regulating signal is used to determine whether the off time in the subsequent switching cycle needs to be extended; The COT control circuit is specifically configured to obtain the fourth sub-control signal according to the second adjustment signal, wherein the fourth sub-control signal is configured to represent the duration of the on-time of the switching power supply in the subsequent switching cycle.

3. The circuit according to claim 2, characterized in that The detection circuit includes: a detection control component, a clock signal output component and a detection signal output component; The first input end of the detection and control component is electrically connected to the output end of the pulse width modulation comparator, the second input end of the detection and control component is electrically connected to the output end of the COT control circuit, the input end of the clock signal output component is electrically connected to the first output end or the second output end of the detection and control component, the output end of the clock signal output component is electrically connected to the second input end of the regulation circuit and the first input end of the detection signal output component respectively, the second input end of the detection signal output component is used to access the power supply voltage, and the output end of the detection signal output component is electrically connected to the first input end of the regulation circuit; the detection and control component being configured to control, when the square wave signal indicates that the switching power supply is in a constant on-time control mode, to electrically connect the first output terminal of the detection and control component to the input terminal of the clock signal output component, and to obtain a first pulse width modulation signal based on the square wave signal and the first sub-control signal, and to transmit the first pulse width modulation signal to the clock signal output component; The clock signal output component is configured to transmit the first clock signal to the detection signal output component according to the first pulse width modulation signal; The detection signal output component is configured to detect, based on the first clock signal, whether the switching power supply enters the minimum off-time in the previous switching cycle, and obtain the first detection signal; or, the detection and control component being configured to control the second output terminal of the detection and control component to be electrically connected to the input terminal of the clock signal output component when the square wave signal indicates that the switching power supply is in a constant off-time control mode, and to obtain a second pulse-width modulation signal based on the square wave signal and the second sub-control signal, and to transmit the second pulse-width modulation signal to the clock signal output component; The clock signal output component is configured to transmit the second clock signal to the detection signal output component according to the second pulse width modulation signal; The detection signal output component is used to detect whether the switching power supply enters the minimum on-time in the previous switching cycle according to the second clock signal, so as to obtain the second detection signal.

4. The circuit according to claim 3, characterized in that The detection control component includes: a first trigger; The set end of the first trigger is electrically connected to the output end of the pulse width modulation comparator, the reset end of the first trigger is electrically connected to the output end of the COT control circuit, and the positive output end or the reverse output end of the first trigger is electrically connected to the input end of the clock signal output component.

5. The circuit according to claim 3, characterized in that The clock signal output component includes: a first switch tube, a second switch tube and a first inverter; The first end of the second switching tube is electrically connected to the first output end or the second output end of the detection control component, the second end of the second switching tube is electrically connected to the first end of the first switching tube and the input end of the first inverter respectively, the second end of the first switching tube and the output end of the first inverter are both electrically connected to the first input end of the detection signal output component, and the control end of the first switching tube and the control end of the second switching tube are both used to receive a switching signal, and the switching signal is used to control the conduction or shutdown of the switching tube.

6. The circuit according to claim 3, characterized in that The detection signal output component includes: a second inverter, a delay device and a second trigger; The input end of the second inverter and the input end of the delay device are both electrically connected to the output end of the clock signal output component, the output end of the second inverter is electrically connected to the clock input end of the second trigger, the output end of the delay device is electrically connected to the set input end of the second trigger, the data input end of the second trigger is used to access the power supply voltage, and the output end of the second trigger is electrically connected to the first input end of the regulation circuit.

7. The circuit according to claim 2, characterized in that The regulating circuit includes: a counter; The clock input terminal of the counter is electrically connected to the second output terminal of the detection circuit, the count input terminal of the counter is electrically connected to the first output terminal of the detection circuit, and the output terminal of the counter is electrically connected to the input terminal of the COT control circuit; the counter being configured to obtain the first clock signal from the detection circuit during the subsequent switching cycle, and determine, at a rising edge of the first clock signal, based on the first detection signal, whether to count up the first value of the counter to obtain the first adjustment signal; or, The counter is used to obtain the second clock signal from the detection circuit during the next switching cycle, and determine whether to count up the first value of the counter based on the second detection signal at the rising edge of the second clock signal to obtain the second adjustment signal.

8. The circuit according to claim 7, characterized in that The regulating circuit further includes: a frequency divider; The input end of the frequency divider is electrically connected to the second output end of the detection circuit, and the output end of the frequency divider is electrically connected to the clock input end of the counter; The frequency divider is configured to divide the first clock signal to obtain a first frequency-divided clock signal, and transmit the first frequency-divided clock signal to the counter so that the counter obtains the first adjustment signal; or, The frequency divider is used to divide the second clock signal to obtain a second frequency-divided clock signal, and transmit the second frequency-divided clock signal to the counter so that the counter obtains the second adjustment signal.

9. The circuit according to any one of claims 2 to 8, characterized in that: The COT control circuit includes: a current output component, a capacitor and a timing comparator; The control end of the current output component is electrically connected to the output end of the regulating circuit, the output end of the current output component is electrically connected to the first plate of the capacitor, the positive input end of the timing comparator is electrically connected between the output end of the current output component and the first plate of the capacitor, the negative input end of the timing comparator is used to access a reference voltage, the reference voltage is related to the square wave signal, and the output end of the timing comparator is electrically connected to the first input end of the detection circuit; The current output component is configured to output a first charging current corresponding to the first regulating signal, and charge the capacitor using the first charging current; The timing comparator is configured to compare the voltage on the capacitor with the reference voltage to obtain the third sub-control signal; or, The current output component is configured to output a second charging current corresponding to the second adjustment signal, and charge the capacitor using the second charging current; The timing comparator is used to compare the voltage on the capacitor with the reference voltage to obtain the fourth sub-control signal.

10. The circuit according to claim 9, characterized in that The current output component includes: a current source, a first N-type crystal, a second N-type transistor, a first P-type transistor, a second P-type transistor, a plurality of N-type transistor groups and a plurality of third inverters; The output end of the current source is electrically connected to the drain end of the first N-type transistor, the gate end of the first N-type transistor is electrically connected to the gate end of the second N-type transistor and the first gate end of each N-type transistor group, the drain end of the first N-type transistor is electrically connected to the drain end of each N-type transistor group, the drain end of the first P-type transistor, the gate end of the first P-type transistor and the gate end of the second P-type transistor, the drain end of the second P-type transistor is electrically connected to the first plate of the capacitor, the source end of the first P-type transistor and the source end of the second P-type transistor are both used to access the power supply voltage, the second gate end of each N-type transistor group is electrically connected to the output end of each third inverter, the input end of each third inverter is electrically connected to the output end of the regulation circuit, and the source end of the first N-type transistor, the source end of the second N-type transistor and the source end of each N-type transistor group are all grounded.

11. The circuit according to claim 10, characterized in that The number of the first N-type transistors is the sum of the number of the second N-type transistors and the number of the multiple N-type transistor groups, the number of the first P-type transistors is equal to the number of the second P-type transistors, the number of the second N-type transistors is related to the longest duration of the on-time or off-time of the switching power supply, and the number of the multiple N-type transistor groups is related to the step size of the adjustment of the switching frequency.

12. A switching power supply, characterized in that: The switching power supply comprises: a high-side power transistor, a low-side power transistor, an inductor, an output capacitor, a first resistor, a second resistor, a pulse width modulation comparator, a controller, a loop control current output circuit and the detection and regulation circuit according to any one of claims 1 to 11; The input end of the loop-controlled current output circuit is electrically connected to the second end of the inductor and the first plate of the output capacitor respectively. The second end of the inductor is also used to output the output voltage of the switching power supply. The output end of the loop-controlled current output circuit is electrically connected to the first end of the first resistor. The second end of the first resistor is electrically connected to the negative phase input end of the pulse width modulation comparator. The first end of the second resistor is used to detect the current of the inductor. The second end of the second resistor is electrically connected to the positive phase input end of the pulse width modulation comparator. The output end of the pulse width modulation comparator is respectively connected to the first input end of the detection circuit and the first input end of the controller. The input end is electrically connected to the output end of the COT control circuit is electrically connected to the second input end of the controller, the first output end of the controller is electrically connected to the control end of the high-side power transistor, the second output end of the controller is electrically connected to the control end of the low-side power transistor, the first end of the high-side power transistor is used to access the input voltage of the switching power supply, the second end of the high-side power transistor is electrically connected to the first end of the low-side power transistor, the first end of the inductor is electrically connected between the second end of the high-side power transistor and the first end of the low-side power transistor, and the second end of the low-side power transistor and the second plate of the output capacitor are both grounded.

13. A chip, characterized in that: include: The detection and regulation circuit according to any one of claims 1 to 11, and / or the switching power supply according to claim 12.

14. An electronic device, characterized in that: include: The chip as claimed in claim 13.

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