Gate drive control circuit, boost converter, chip and electronic device

Abstract

The application provides a gate drive control circuit, a boost converter, a chip and an electronic device. In the case that the boost converter is in starting, an indication signal output circuit can transmit a first indication signal to an up pull circuit and a capacitive drive circuit according to an output voltage and an input voltage. In this way, the up pull circuit can pull up the voltage of the first end of the first transistor to the power supply voltage according to the first indication signal. The capacitive drive circuit can drive the first transistor to be turned on according to the first drive signal and the first indication signal, so that the voltage of the gate end of the first P-type transistor is constant as the power supply voltage. Further, when the voltage of the source end of the first P-type transistor rises, the first P-type transistor is turned on and is in a saturation region, so that the voltage of the source end of the first P-type transistor charges to the output voltage of the boost converter. Therefore, the output voltage of the boost converter starts from zero voltage, so that the boost converter can complete starting.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a gate drive control circuit, a boost converter, a chip, and an electronic device. Background Art

[0002] When the output voltage of a boost converter (Boost) is lower than the input voltage and the output voltage starts from zero voltage, a P-type transistor needs to be provided outside the Boost converter to block the conduction of the body diode of the upper transistor in the Boost converter, so that the output voltage gradually rises from zero voltage, i.e., the soft start process, to avoid the risk of damage to the upper transistor. However, the conduction of the P-type transistor requires a gate drive control circuit. Therefore, there is an urgent need for a gate drive control circuit that can control the conduction of the P-type transistor to enable the Boost converter to complete startup. Summary of the Invention

[0003] The present application provides a gate drive control circuit, a boost converter, a chip and an electronic device, which can control the conduction of a P-type transistor so that the Boost converter can be started in a buck mode.

[0004] In a first aspect, the present application provides a gate drive control circuit, comprising: the gate drive control circuit is applied to a boost converter, the boost converter comprising: a high-side power transistor, a low-side power transistor, an inductor, a drive circuit, and a first P-type transistor; the gate drive control circuit comprises: an indication signal output circuit, a pull-up circuit, a capacitive drive circuit, and a first transistor;

[0005] The first input end of the indication signal output circuit is used to access the output voltage of the boost converter, the second input end of the indication signal output circuit is used to access the input voltage of the boost converter, the output end of the indication signal output circuit is electrically connected to the control end of the pull-up circuit and the first input end of the capacitive drive circuit respectively, the second input end of the capacitive drive circuit is electrically connected to the first output end of the drive circuit, the output end of the capacitive drive circuit is electrically connected to the control end of the first transistor, the input end of the pull-up circuit is used to access the power supply voltage, the output end of the pull-up circuit and the power supply end of the capacitive drive circuit are both electrically connected to the first end of the first transistor, The second end of the first transistor is electrically connected to the gate end of the first P-type transistor, the drain end of the first P-type transistor is used to output the output voltage of the boost converter, the source end of the first P-type transistor is electrically connected to the second end of the high-side power transistor, the control end of the high-side power transistor is electrically connected to the second output end of the drive circuit, the first end of the high-side power transistor is electrically connected to the second end of the low-side power transistor, the first end of the inductor is electrically connected between the first end of the high-side power transistor and the second end of the low-side power transistor, the control end of the low-side power transistor is electrically connected to the first output end of the drive circuit, and the first end of the low-side power transistor is grounded;

[0006] The indication signal output circuit is configured to transmit a first indication signal to the pull-up circuit and the capacitive driving circuit respectively according to the output voltage and the input voltage when the boost converter is started, wherein the first indication signal is configured to indicate that the output voltage is less than the input voltage;

[0007] The pull-up circuit is configured to pull up the voltage of the first terminal of the first transistor to the power supply voltage according to the first indication signal;

[0008] The capacitive driving circuit is used to obtain a first driving signal from the driving circuit, and drive the first transistor to be turned on according to the first driving signal and the first indication signal, so that the voltage at the gate terminal of the first P-type transistor is constant to the power supply voltage, so that when the inductor charges the voltage at the source terminal of the first P-type transistor through the high-side power transistor, the first P-type transistor is turned on and is in a saturation region.

[0009] With the gate drive control circuit provided in the first aspect, when the boost converter is in startup, the indication signal output circuit can transmit a first indication signal indicating that the output voltage is less than the input voltage to the pull-up circuit and the capacitive drive circuit, respectively, based on the output voltage and the input voltage, so that the pull-up circuit and the capacitive drive circuit can receive the first indication signal. In this way, the pull-up circuit can pull up the voltage at the first terminal of the first transistor to the power supply voltage based on the first indication signal. The capacitive drive circuit can receive the first drive signal from the drive circuit and, based on the first drive signal and the first indication signal, drive the first transistor to conduct, so that the voltage at the gate terminal of the first P-type transistor is constant at the power supply voltage. Furthermore, when the inductor charges the voltage at the source terminal of the first P-type transistor through the high-side power transistor, increasing the voltage at the source terminal of the first P-type transistor, the gate-source voltage of the first P-type transistor increases because the voltage at the gate terminal of the first P-type transistor is constant at the power supply voltage. As a result, the first P-type transistor is turned on and in a saturation region, causing the voltage at the source terminal of the first P-type transistor to charge toward the output voltage of the boost converter through the first P-type transistor. Thus, the output voltage of the boost converter starts from zero voltage, so that the boost converter can complete startup in the buck mode.

[0010] In one possible design, the gate drive control circuit further includes: a pull-down circuit and a switch-off circuit;

[0011] The input end of the pull-down circuit and the control end of the switch-off circuit are both electrically connected to the output end of the indication signal output circuit, the output end of the pull-down circuit is electrically connected to the gate end of the first P-type transistor, the second end of the switch-off circuit is electrically connected to the control end of the first transistor, and the first end of the switch-off circuit is grounded;

[0012] The indication signal output circuit is further configured to transmit a second indication signal to the pull-up circuit, the pull-down circuit, the switch off circuit, and the capacitive driving circuit respectively according to the output voltage and the input voltage, wherein the second indication signal is configured to indicate that the output voltage is equal to or greater than the input voltage;

[0013] The pull-up circuit is further configured to stop pulling up the voltage of the first end of the first transistor according to the second indication signal;

[0014] The switch-off circuit is configured to turn off the first transistor according to the second indication signal when the voltage at the first end of the first transistor stops being pulled up;

[0015] The capacitive driving circuit is further configured to stop driving the first transistor to be turned on according to the second indication signal, so that the first transistor is always turned off;

[0016] The pull-down circuit is configured to pull down a voltage at a gate terminal of the first P-type transistor according to the second indication signal, so that the first P-type transistor is turned on and is in a linear region.

[0017] In a possible design, the gate driving control circuit further includes a control circuit.

[0018] A first terminal of the control circuit is electrically connected with a gate terminal of the first P-type transistor, and a second terminal of the control circuit is electrically connected with a source terminal of the first P-type transistor.

[0019] The control circuit is configured to control the first P-type transistor to be turned off before the boost converter is started.

[0020] In a possible design, the control circuit is a first resistor, and a resistance of the first resistor is greater than a preset resistance.

[0021] In a possible design, the capacitive driving circuit includes a charge pump, an OR gate, and a first inverter.

[0022] A first input terminal of the OR gate is electrically connected with a first output terminal of the driving circuit, a second input terminal of the OR gate is electrically connected with an output terminal of the indication signal output circuit, an output terminal of the OR gate is electrically connected with an input terminal of the first inverter, an output terminal of the first inverter is electrically connected with an input terminal of the charge pump, a power supply terminal of the charge pump is electrically connected with a first terminal of the first transistor, and an output terminal of the charge pump is electrically connected with a control terminal of the first transistor.

[0023] The OR gate is configured to perform logical operation on the first indication signal and the first driving signal to obtain a first signal, and transmit the first signal to the first inverter.

[0024] The first inverter is configured to change a level state of the first signal to obtain a second signal, and transmit the second signal to the charge pump.

[0025] The charge pump is configured to drive the first transistor to be turned on according to the second signal.

[0026] Alternatively,

[0027] The OR gate is configured to perform logical operation on the second indication signal and the first driving signal to obtain a third signal, and transmit the third signal to the first inverter.

[0028] The first inverter is configured to change a level state of the third signal to obtain a fourth signal, and transmit the fourth signal to the charge pump.

[0029] The charge pump is configured to stop driving the first transistor to be turned on according to the fourth signal.

[0030] In one possible design, the charge pump includes: a first N-type transistor, a second N-type transistor, a first capacitor, a second capacitor, and a second inverter;

[0031] An input terminal of the second inverter is electrically connected to an output terminal of the first inverter, an output terminal of the second inverter is electrically connected to a second plate of the second capacitor, a first plate of the second capacitor is electrically connected to a drain terminal of the second N-type transistor, a source terminal of the second N-type transistor and a source terminal of the first N-type transistor are both electrically connected to a first terminal of the first transistor, a drain terminal of the first N-type transistor is electrically connected to a first plate of the first capacitor, a gate terminal of the first N-type transistor is electrically connected between the first plate of the second capacitor and the drain terminal of the second N-type transistor, a gate terminal of the second N-type transistor and a control terminal of the first transistor are both electrically connected between the drain terminal of the first N-type transistor and the first plate of the first capacitor, and a second plate of the first capacitor is electrically connected between an input terminal of the second inverter and an output terminal of the first inverter.

[0032] In one possible design, the pull-up circuit includes: a second P-type transistor and a third N-type transistor;

[0033] The source terminal of the second P-type transistor is used to access the power supply voltage, the gate terminal of the second P-type transistor and the gate terminal of the third N-type transistor are both electrically connected to the output terminal of the indication signal output circuit, the drain terminal of the second P-type transistor is electrically connected to the drain terminal of the third N-type transistor, the first terminal of the first transistor is electrically connected between the drain terminal of the second P-type transistor and the drain terminal of the third N-type transistor, and the source terminal of the third N-type transistor is grounded.

[0034] In one possible design, the pull-down circuit includes: a second resistor, a delay device, a fourth N-type transistor, and a fifth N-type transistor;

[0035] The first end of the second resistor and the drain end of the fifth N-type transistor are both electrically connected to the gate end of the first P-type transistor, the second end of the second resistor is electrically connected to the drain end of the fourth N-type transistor, the gate end of the fourth N-type transistor and the input end of the delay device are both electrically connected to the output end of the indication signal output circuit, the output end of the delay device is electrically connected to the gate end of the fifth N-type transistor, and the source end of the fourth N-type transistor and the source end of the fifth N-type transistor are both grounded.

[0036] In a possible design, the first transistor, the fourth N-type transistor, and the fifth N-type transistor all have a breakdown voltage greater than a preset breakdown voltage.

[0037] In a possible design, the first transistor is an N-type transistor.

[0038] In a second aspect, the present application provides a boost converter, including: a driving circuit, a first P-type transistor, a high-side power transistor, a low-side power transistor, an inductor, an output capacitor, and the gate driving control circuit in the first aspect and possible designs of the first aspect.

[0039] The gate terminal of the first P-type transistor is electrically connected with the second terminal of the first transistor, the drain terminal of the P-type transistor is electrically connected with the first plate of the output capacitor, the drain terminal of the P-type transistor is further configured to output an output voltage of the boost converter, the source terminal of the first P-type transistor is electrically connected with the second terminal of the high-side power transistor, the control terminal of the high-side power transistor is electrically connected with the second output terminal of the driving circuit, the first terminal of the high-side power transistor is electrically connected with the second terminal of the low-side power transistor, the first terminal of the inductor is electrically connected between the first terminal of the high-side power transistor and the second terminal of the low-side power transistor, the second terminal of the inductor is configured to access an input voltage of the boost converter, the control terminal of the low-side power transistor is electrically connected with the first output terminal of the driving circuit, and the first terminal of the low-side power transistor and the second plate of the output capacitor are both grounded.

[0040] The boost converter in the second aspect and possible designs of the second aspect has the beneficial effects of the first aspect and possible designs of the first aspect, which will not be repeated here.

[0041] In a third aspect, the present application provides a chip, including: the gate driving control circuit in the first aspect and possible designs of the first aspect, and / or the boost converter in the second aspect.

[0042] In a fourth aspect, the present application provides an electronic device, including: the chip in the third aspect.

[0043] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 It is a structural diagram of a buck converter in the prior art;

[0046] Figure 2 It is a structural diagram of a boost converter in the prior art;

[0047] Figure 3 It is a structural diagram of another boost converter in the prior art;

[0048] Figure 4 A schematic structural diagram of a gate drive control circuit provided in one embodiment of the present application;

[0049] Figure 5 A schematic structural diagram of a gate drive control circuit in a step-down application provided by an embodiment of the present application;

[0050] Figure 6 A schematic structural diagram of a boost converter provided in one embodiment of the present application. DETAILED DESCRIPTION

[0051] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0052] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0053] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0054] Reference Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of a buck converter in the prior art. Figure 1 As shown, a buck converter (Buck) chip integrates a power-stage switch M1' (i.e., the upper switch) and a power-stage switch M2' (i.e., the lower switch). By connecting an inductor L0 and a capacitor Cout0 to a node SW0 between the source terminal of the power-stage switch M1' and the drain terminal of the power-stage switch M2' as outputs, a Buck converter is obtained.

[0055] When the input and output of the Buck converter are swapped, we can get Figure 2 The Boost converter shown, Figure 2 This is a schematic diagram of the structure of a boost converter in the prior art. When the output voltage VOUT0 of the boost converter is lower than the input voltage VIN0 and the output voltage VOUT0 starts from zero voltage, the input voltage VIN0 directly charges node SW0 through inductor L0, and the output voltage VOUT0 is charged through the body diode D1' of power stage switch M1'. This causes the output voltage VOUT0 to directly rise to the voltage difference between the input voltage VIN0 and the body diode voltage Vdio. Consequently, the output voltage VOUT0 does not undergo a soft-start process.

[0056] In addition, when the capacitance of the capacitor Cout0 is large, a large current will continue to flow through the body diode D1 ′, causing a risk of damaging the power stage switch M1 ′.

[0057] Buck converters are used in multi-cell battery applications, meaning their input voltage is provided by multiple battery cells. Boost converters are used in single-cell battery applications, meaning their input voltage is provided by a single battery cell and typically does not exceed 5V.

[0058] Therefore, refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of another structure of a boost converter in the prior art. Figure 3 As shown, a P-type transistor is required outside the Boost converter to prevent the conduction of body diode D1', allowing the output voltage VOUT0 to soft-start from zero voltage and avoid the risk of damage to power stage switch M1'. However, the conduction of the P-type transistor requires the gate drive control circuit PGATE CTRL.

[0059] Therefore, the present application provides a gate drive control circuit capable of controlling the conduction of a P-type transistor, so that the output voltage VOUT1 of the boost converter 1000 starts from zero voltage, i.e., a soft start process occurs. Consequently, the boost converter 1000 can complete startup in the step-down mode. The gate drive control circuit 100 provided in the present application is described below with reference to specific embodiments.

[0060] Reference Figure 4 , Figure 4 This is a schematic diagram of the structure of a gate drive control circuit provided by an embodiment of the present application. Figure 4 As shown, the gate drive control circuit 100 may include: an indication signal output circuit 110 , a pull-up circuit 120 , a capacitive drive circuit 130 and a first transistor N1 .

[0061] The first input terminal of the indication signal output circuit 110 is used to access the output voltage VOUT1 of the boost converter 1000, the second input terminal of the indication signal output circuit 110 is used to access the input voltage VIN1 of the boost converter 1000, the output terminal of the indication signal output circuit 110 is electrically connected to the control terminal of the pull-up circuit 120 and the first input terminal of the capacitive driving circuit 130 respectively, the second input terminal of the capacitive driving circuit 130 is electrically connected to the first output terminal of the driving circuit DRIVER1, the output terminal of the capacitive driving circuit 130 is electrically connected to the control terminal of the first transistor N1, the input terminal of the pull-up circuit 120 is used to access the power supply voltage VDD, the output terminal of the pull-up circuit 120 and the power supply terminal of the capacitive driving circuit 130 are both connected to the second output terminal of the first transistor N1 One end is electrically connected, the second end of the first transistor N1 is electrically connected to the gate end PGATE1 of the first P-type transistor M3, the drain end of the P-type transistor is used to output the output voltage VOUT1 of the boost converter 1000, the source end of the first P-type transistor is electrically connected to the second end of the high-side power transistor M1, the control end of the high-side power transistor M1 is electrically connected to the second output end of the drive circuit DRIVER1, the first end of the high-side power transistor M1 is electrically connected to the second end of the low-side power transistor M2, the first end of the inductor L1 is electrically connected between the first end of the high-side power transistor M1 and the second end of the low-side power transistor M2, the control end of the low-side power transistor M2 is electrically connected to the first output end of the drive circuit DRIVER1, and the first end of the low-side power transistor M2 is grounded.

[0062] Among them, the indication signal output circuit 110, the pull-up circuit 120, the capacitive driving circuit 130 and the first transistor N1 can be provided separately or integrated, and the embodiment of the present application does not specifically limit this.

[0063] In some examples, the first transistor N1 is an N-type transistor, wherein a first terminal of the first transistor N1 is a source terminal, a second terminal of the first transistor N1 is a drain terminal, and a control terminal of the first transistor N1 is a gate terminal.

[0064] In some examples, the indication signal output circuit 110 is a comparator DM comp, the positive input terminal of which is connected to the output voltage VOUT1 of the boost converter 1000 , and the negative input terminal of which is connected to the input voltage VIN1 of the boost converter 1000 .

[0065] When the boost converter 1000 is started, the indication signal output circuit 110 can transmit the first indication signal DM_OVER1 to the pull-up circuit 120 and the capacitive driving circuit 130 respectively according to the output voltage VOUT1 and the input voltage VIN1, so that the pull-up circuit 120 and the capacitive driving circuit 130 can obtain the first indication signal DM_OVER1.

[0066] The first indication signal DM_OVER1 is used to indicate that the output voltage VOUT1 is less than the input voltage VIN1. In other words, the first indication signal DM_OVER1 means that the boost converter 1000 is in the process of starting up in the down mode.

[0067] In this way, the pull-up circuit 120 can pull up the voltage VA at the first terminal of the first transistor N1 to the power supply voltage VDD according to the first indication signal DM_OVER1 .

[0068] Since the gate drive control circuit 100 is applied to the boost converter 1000 , the power supply voltage VDD is generally approximately equal to the input voltage VIN1 .

[0069] The capacitive driving circuit 130 can obtain a first driving signal LG1 from the driving circuit DRIVER1. Furthermore, the capacitive driving circuit 130 can drive the first transistor N1 to conduct based on the first driving signal LG1 and the first indication signal DM_OVER1, so that the conducted first transistor N1 can provide a pull-down force to keep the voltage at the gate terminal PGATE1 of the first P-type transistor M3 constant at the power supply voltage VDD, ensuring that the voltage at the gate terminal PGATE1 of the first P-type transistor M3 does not change with changes in the voltage VS1 at the source terminal of the first P-type transistor M3.

[0070] Furthermore, when inductor L1 charges the voltage VS1 at the source terminal of first P-type transistor M3 through high-side power transistor M1, causing the voltage VS1 at the source terminal of first P-type transistor M3 to increase, the gate-source voltage Vgs1 of first P-type transistor M3 increases because the voltage at gate terminal PGATE1 of first P-type transistor M3 is constant at power supply voltage VDD. Consequently, first P-type transistor M3 is turned on and in saturation, causing the voltage VS1 at the source terminal of first P-type transistor M3 to charge output voltage VOUT1 of boost converter 1000 through first P-type transistor M3. Consequently, output voltage VOUT1 of boost converter 1000 starts from zero voltage, enabling boost converter 1000 to complete startup in step-down mode.

[0071] The gate drive control circuit provided in the present application can, when the boost converter is in startup, transmit a first indication signal to the pull-up circuit and the capacitive drive circuit, respectively, based on the output voltage and the input voltage, indicating that the output voltage is less than the input voltage, so that the pull-up circuit and the capacitive drive circuit can obtain the first indication signal. In this way, the pull-up circuit can pull up the voltage at the first terminal of the first transistor to the power supply voltage based on the first indication signal. The capacitive drive circuit can obtain a first drive signal from the drive circuit and, based on the first drive signal and the first indication signal, drive the first transistor to conduct, so that the voltage at the gate terminal of the first P-type transistor is constant at the power supply voltage. Furthermore, when the inductor charges the voltage at the source terminal of the first P-type transistor through the high-side power transistor, causing the voltage at the source terminal of the first P-type transistor to increase, the gate-source voltage of the first P-type transistor increases because the voltage at the gate terminal of the first P-type transistor is constant at the power supply voltage. As a result, the first P-type transistor is turned on and in a saturation region, causing the voltage at the source terminal of the first P-type transistor to charge the output voltage of the boost converter through the first P-type transistor. Thus, the output voltage of the boost converter starts from zero voltage, so that the boost converter can complete startup in the buck mode.

[0072] Based on the description of the above embodiment, a possible implementation of the gate drive control circuit 100 is exemplified. Figure 4 As shown, the gate drive control circuit 100 may further include a pull-down circuit 150 and a switch turn-off circuit 160 .

[0073] The input end of the pull-down circuit 150 and the control end of the switch-off circuit 160 are both electrically connected to the output end of the indication signal output circuit 110, the output end of the pull-down circuit 150 is electrically connected to the gate end PGATE1 of the first P-type transistor M3, the second end of the switch-off circuit 160 is electrically connected to the control end of the first transistor N1, and the first end of the switch-off circuit 160 is grounded.

[0074] In some examples, the switch-off circuit 160 is a sixth N-type transistor MN6 . The gate terminal of the sixth N-type transistor MN6 serves as the control terminal of the switch-off circuit 160 , the drain terminal of the sixth N-type transistor MN6 serves as the second terminal of the switch-off circuit 160 , and the source terminal of the sixth N-type transistor MN6 serves as the first terminal of the switch-off circuit 160 .

[0075] The indication signal output circuit 110 can transmit the second indication signal DM_OVER2 to the pull-up circuit 120, the pull-down circuit 150, the switch-off circuit 160 and the capacitive driving circuit 130 respectively according to the output voltage VOUT1 and the input voltage VIN1, so that the pull-up circuit 120, the pull-down circuit 150, the switch-off circuit 160 and the capacitive driving circuit 130 can obtain the second indication signal DM_OVER2.

[0076] The second indication signal DM_OVER2 is used to indicate that the output voltage VOUT1 is equal to or greater than the input voltage VIN1. In other words, the second indication signal DM_OVER2 means that the boost converter 1000 has completed the startup of the down mode.

[0077] In this way, the pull-up circuit 120 may stop pulling up the voltage VA at the first end of the first transistor N1 according to the second indication signal DM_OVER2 .

[0078] When the voltage VA at the first terminal of the first transistor N1 stops being pulled up, the switch-off circuit 160 may turn off the first transistor N1 according to the second indication signal DM_OVER2 .

[0079] The capacitive driving circuit 130 may stop driving the first transistor N1 to turn on according to the second indication signal DM_OVER2 , so that the first transistor N1 is always turned off.

[0080] The pull-down circuit 150 can pull down the voltage of the gate terminal PGATE1 of the first P-type transistor M3 according to the second indication signal DM_OVER2, so that the voltage of the gate terminal PGATE1 of the first P-type transistor M3 is gradually pulled to zero voltage, so that the first P-type transistor M3 is turned on and is in the linear region.

[0081] Based on the description of the above embodiment, a possible implementation of the capacitive driving circuit 130 is exemplified. Figure 4 As shown, the capacitive driving circuit 130 may include: a control circuit 140 .

[0082] A first terminal of the control circuit 140 is electrically connected to the gate terminal PGATE1 of the first P-type transistor M3 , and a second terminal of the control circuit 140 is electrically connected to the source terminal of the first P-type transistor M3 .

[0083] In some examples, the control circuit 140 is a first resistor R1 , and the resistance of the first resistor R1 is greater than a preset resistance.

[0084] When the boost converter 1000 is before starting, that is, when the gate drive control circuit 100 is not working, the control circuit 140 can control the gate-source voltage Vgs2 of the first P-type transistor M3 to be equal to 0, so that the first P-type transistor M3 is turned off.

[0085] In addition, when the boost converter 1000 is started, since the resistance of the first resistor R1 is relatively large, the control circuit 140 can reduce the voltage at the gate terminal PGATE1 of the first P-type transistor M3 from changing with the voltage VS1 at the source terminal of the first P-type transistor M3, and reduce the quiescent current of the gate drive control circuit 100, thereby reducing the power consumption of the gate drive control circuit 100.

[0086] Among them, the quiescent current is usually tens of microamperes.

[0087] Based on the description of the above embodiment, a possible implementation of the capacitive driving circuit 130 is exemplified. Figure 4 As shown, the capacitive driving circuit 130 may include: a charge pump 131 , an OR gate OR, and a first inverter INV1 .

[0088] A first input terminal of the OR gate OR is electrically connected to a first output terminal of the driving circuit DRIVER1, a second input terminal of the OR gate OR is electrically connected to an output terminal of the indication signal output circuit 110, an output terminal of the OR gate OR is electrically connected to an input terminal of the first inverter INV1, an output terminal of the first inverter INV1 is electrically connected to an input terminal of the charge pump 131, a power supply terminal of the charge pump 131 is electrically connected to a first terminal of the first transistor N1, and an output terminal of the charge pump 131 is electrically connected to a control terminal of the first transistor N1.

[0089] Among them, the second input end of the OR gate OR is the first input end of the capacitive driving circuit 130, the first input end of the OR gate OR is the second input end of the capacitive driving circuit 130, the power supply end of the charge pump 131 is the power supply end of the capacitive driving circuit 130, and the output end of the charge pump 131 is the output end of the capacitive driving circuit 130.

[0090] The OR gate OR may perform a logic operation on the first indication signal DM_OVER1 and the first driving signal LG1 to obtain a first signal, and transmit the first signal to the first inverter INV1.

[0091] The logical operation refers to the logical operation of "OR".

[0092] The first inverter INV1 can change the level state of the first signal to obtain a second signal, and transmit the second signal to the charge pump 131 .

[0093] When the level of the first signal is high, the level of the second signal is low. When the level of the first signal is low, the level of the second signal is high.

[0094] The charge pump 131 may drive the first transistor N1 to turn on according to the second signal.

[0095] or,

[0096] The OR gate OR can perform a logic operation on the second indication signal DM_OVER2 and the first driving signal LG1 to obtain a third signal, and transmit the third signal to the first inverter INV1.

[0097] When the second indication signal DM_OVER2 is high, the third signal is always high regardless of whether the first driving signal LG1 is high or low. In other words, when the second indication signal DM_OVER2 is high, the first driving signal LG1 is shielded.

[0098] The first inverter INV1 can change the level state of the third signal to obtain a fourth signal, and transmit the fourth signal to the charge pump 131 .

[0099] The charge pump 131 may stop driving the first transistor N1 to turn on according to the fourth signal.

[0100] In some examples, the charge pump 131 may include a first N-type transistor MN1 , a second N-type transistor MN2 , a first capacitor C1 , a second capacitor C2 , and a second inverter INV2 .

[0101] An input terminal of the second inverter INV2 is electrically connected to the output terminal of the first inverter INV1. The output terminal of the second inverter INV2 is electrically connected to the second plate of the second capacitor C2. The first plate of the second capacitor C2 is electrically connected to the drain terminal of the second N-type transistor MN2. The source terminal of the second N-type transistor MN2 and the source terminal of the first N-type transistor MN1 are both electrically connected to the first terminal of the first transistor N1. The drain terminal of the first N-type transistor MN1 is electrically connected to the first plate of the first capacitor C1. The gate terminal of the first N-type transistor MN1 is electrically connected between the first plate of the second capacitor C2 and the drain terminal of the second N-type transistor MN2. The gate terminal of the second N-type transistor MN2 and the control terminal of the first transistor N1 are both electrically connected between the drain terminal of the first N-type transistor MN1 and the first plate of the first capacitor C1. The second plate of the first capacitor C1 is electrically connected between the input terminal of the second inverter INV2 and the output terminal of the first inverter INV1.

[0102] The source terminals of the second N-type transistor MN2 and the first N-type transistor MN1 are both power supply terminals of the charge pump 131 , the input terminal of the second inverter INV2 is the input terminal of the charge pump 131 , and the gate terminal of the second N-type transistor MN2 is the output terminal of the charge pump 131 .

[0103] Based on the description of the above embodiment, a possible implementation of the pull-up circuit 120 is exemplified. Figure 4As shown, the pull-up circuit 120 may include: a second P-type transistor MP1 and a third N-type transistor MN3.

[0104] The source terminal of the second P-type transistor MP1 is used to access the power supply voltage VDD, the gate terminal of the second P-type transistor MP1 and the gate terminal of the third N-type transistor MN3 are both electrically connected to the output terminal of the indication signal output circuit 110, the drain terminal of the second P-type transistor MP1 is electrically connected to the drain terminal of the third N-type transistor MN3, the first terminal of the first transistor N1 is electrically connected between the drain terminal of the second P-type transistor MP1 and the drain terminal of the third N-type transistor MN3, and the source terminal of the third N-type transistor MN3 is grounded.

[0105] Among them, the source end of the second P-type transistor MP1 is the input end of the pull-up circuit 120, the gate end of the second P-type transistor MP1 and the gate end of the third N-type transistor MN3 are both control ends of the pull-up circuit 120, and the output end of the pull-up circuit 120 is located between the drain end of the second P-type transistor MP1 and the drain end of the third N-type transistor MN3.

[0106] Based on the description of the above embodiment, a possible implementation of the pull-down circuit 150 is exemplified. Figure 4 As shown, the pull-down circuit 150 may include: a second resistor R2, a delay device Tdly, a fourth N-type transistor MN4 and a fifth N-type transistor MN5.

[0107] The first end of the second resistor R2 and the drain end of the fifth N-type transistor MN5 are electrically connected to the gate end PGATE1 of the first P-type transistor M3, the second end of the second resistor R2 is electrically connected to the drain end of the fourth N-type transistor MN4, the gate end of the fourth N-type transistor MN4 and the input end of the delay device Tdly are electrically connected to the output end of the indication signal output circuit 110, the output end of the delay device Tdly is electrically connected to the gate end of the fifth N-type transistor MN5, and the source end of the fourth N-type transistor MN4 and the source end of the fifth N-type transistor MN5 are both grounded.

[0108] The gate terminal of the fourth N-type transistor MN4 and the input terminal of the delay device Tdly are both input terminals of the pull-down circuit 150 , and the first terminal of the second resistor R2 and the drain terminal of the fifth N-type transistor MN5 are both output terminals of the pull-down circuit 150 .

[0109] In some examples, the withstand voltage of the first transistor N1, the fourth N-type transistor MN4, and the fifth N-type transistor MN5 are all greater than the preset withstand voltage. That is, the first transistor N1, the fourth N-type transistor MN4, and the fifth N-type transistor MN5 are all high-voltage devices.

[0110] Since the first transistor N1, the fourth N-type transistor MN4 and the fifth N-type transistor MN5 are all high-voltage devices, the gate drive control circuit 100 can be used in the following situations: Figure 5 The multi-cell battery shown works in BUCK application. Figure 5 , Figure 5 A schematic structural diagram of a gate drive control circuit in a step-down application is provided in one embodiment of the present application.

[0111] The preset withstand voltage value is usually determined by the number of cells in a multi-cell BUCK application, or by the maximum value of the input voltage VIN2 in a multi-cell BUCK application.

[0112] Figure 5 The drive circuit, high-side power transistor, low-side power transistor, inductor and output capacitor in Figure 6 The driving circuit DRIVER1, high-side power transistor M1, low-side power transistor M2, inductor L1 and output capacitor Cout1 in FIG can be the same type of devices. Therefore, the same reference numerals are used for the components. Figure 5 The middle drive circuit, high-side power transistor, low-side power transistor, inductor and output capacitor are schematically shown.

[0113] Reference Figure 6 , Figure 6 This is a schematic diagram of the structure of a boost converter provided in one embodiment of the present application. Figure 6 As shown, the boost converter 1000 may include: a driving circuit DRIVER1 , a first P-type transistor M3 , a high-side power transistor M1 , a low-side power transistor M2 , an inductor L1 , an output capacitor Cout1 and a gate drive control circuit 100 .

[0114] The gate terminal PGATE1 of the first P-type transistor M3 is electrically connected to the second terminal of the first transistor N1, the drain terminal of the P-type transistor is electrically connected to the first plate of the output capacitor Cout1, and the drain terminal of the P-type transistor is also used to output the output voltage VOUT1 of the boost converter 1000. The source terminal of the first P-type transistor is electrically connected to the second terminal of the high-side power transistor M1, the control terminal of the high-side power transistor M1 is electrically connected to the second output terminal of the drive circuit DRIVER1, the first terminal of the high-side power transistor M1 is electrically connected to the second terminal of the low-side power transistor M2, the first terminal of the inductor L1 is electrically connected between the first terminal of the high-side power transistor M1 and the second terminal of the low-side power transistor M2, the second end of the inductor L1 is used to access the input voltage VIN1 of the boost converter 1000, the control terminal of the low-side power transistor M2 is electrically connected to the first output terminal of the drive circuit DRIVER1, and the first terminal of the low-side power transistor M2 and the second plate of the output capacitor Cout1 are both grounded.

[0115] The high-side power transistor M1 is usually referred to as the upper transistor, and the low-side power transistor M2 is usually referred to as the lower transistor.

[0116] The high-side power transistor M1 and the low-side power transistor M2 can be field-effect transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), which include N-type metal oxide semiconductor field effect transistors (NMOSFETs or NMOS transistors) and P-type metal oxide semiconductor field effect transistors (PMOSFETs or PMOS transistors). To simplify the description, this embodiment uses an example in which both the high-side power transistor M1 and the low-side power transistor M2 are enhancement-mode NMOS transistors.

[0117] The second terminal of the high-side power transistor M1 is a drain terminal, the control terminal of the high-side power transistor M1 is a gate terminal, and the first terminal of the high-side power transistor M1 is a source terminal. The second terminal of the low-side power transistor M2 is a drain terminal, the control terminal of the low-side power transistor M2 is a gate terminal, and the first terminal of the low-side power transistor M2 is a source terminal.

[0118] After the boost converter 1000 is started, the driver circuit DRIVER1 can output a first drive signal LG1 and a second drive signal HG1 . Thus, the first drive signal LG1 can drive the low-side power transistor M2 to turn on or off, and the second drive signal HG1 can drive the high-side power transistor M1 to turn on or off.

[0119] The first driving signal LG1 is used to drive the low-side power transistor M2 to be turned on or off, and the second driving signal HG1 is used to drive the high-side power transistor M1 to be turned on or off.

[0120] When the boost converter 1000 operates in a multi-cell BUCK application, the gate drive control circuit 100 does not operate, leaving the gate terminal PGATE1 of the first P-type transistor M3 in a floating state. Since the voltage VS1 at the source terminal of the first P-type transistor M3 is equal to the input voltage VIN1, the voltage VS1 at the source terminal of the first P-type transistor M3 and the voltage at the gate terminal PGATE of the first P-type transistor M3 are both equal to the input voltage VIN1. Because the voltage in the multi-cell BUCK application is relatively high, the gate drive control circuit 100 is exposed to high voltage, namely, the first transistor N1, the fourth N-type transistor MN4, and the fifth N-type transistor MN5 are exposed to high voltage. Since the first transistor N1, the fourth N-type transistor MN4, and the fifth N-type transistor MN5 are all high-voltage devices, the gate drive control circuit 100 has no impact on the multi-cell BUCK application and does not generate static current. Therefore, the gate drive control circuit 100 provided in this application is compatible with both single-cell BOOST applications and multi-cell BUCK applications. Furthermore, it does not generate power consumption in multi-cell BUCK applications, nor does it affect the operation of single-cell BOOST applications.

[0121] When the boost converter 100 is powered on and the gate drive control circuit 100 is not operating, the voltage VS1 at the source of the first P-type transistor M3 is the voltage obtained by charging the input voltage VIN1 through the inductor L1 and the body diode D1. In other words, the voltage VS1 at the source of the first P-type transistor M3 is the difference between the input voltage VIN1 and the voltage drop Vdio across the body diode D1, i.e., VS1 = VIN1 - Vdio. Because the gate drive control circuit 100 is not operating, the first transistor N1, the fourth N-type transistor MN4, and the fifth N-type transistor MN5 are turned off. Therefore, no current flows through the first resistor R1, causing the voltage VS1 at the source of the first P-type transistor M3 to equal the voltage at the gate terminal PGATE1 of the first P-type transistor M3. Simultaneously, because the gate-source voltage Vgs2 of the first P-type transistor M3 = VPGATE1 - VS1 = 0, the first P-type transistor M3 is turned off. VPGATE1 is the voltage at the gate terminal PGATE1 of the first P-type transistor M3. Based on this, there is no charging path from the input voltage VIN1 to the output voltage VOUT1, so that the output voltage VOUT1 will not be charged.

[0122] The following describes in detail the working principle of the gate drive control circuit 100 when the boost converter 1000 is in startup, when the output voltage VOUT1 is less than the input voltage VIN1, and when the output voltage VOUT1 is equal to or greater than the input voltage VIN1.

[0123] When the output voltage VOUT1 is lower than the input voltage VIN1, the comparator DM comp outputs a first indication signal DM_OVER1 at a low level, turning on the second P-type transistor MP1 and turning off the third N-type transistor MN3, the fourth N-type transistor NM4, the fifth N-type transistor MN5, and the sixth N-type transistor MN6. The second P-type transistor MP1 can pull up the voltage VA at the first terminal of the first transistor N1 to the power supply voltage VDD.

[0124] When the first drive signal LG1 is high, the low-side power transistor M2 turns on, inductor L1 begins charging, and the current in inductor L1 increases. At this point, the second signal obtained after the first indication signal DM_OVER1 and the first drive signal LG1 pass through the OR gate OR and the first inverter INV1 is low. After passing through the second inverter INV2, the output signal of the second inverter INV2 is high. Thus, after the output signal of the second inverter INV2 turns high, it raises the voltage of the second capacitor C2, turning on the first N-type transistor MN1. In this way, the power supply voltage VDD charges the voltage on the first capacitor C1 to the power supply voltage VDD through the turned-on first N-type transistor.

[0125] After the low-side power transistor M2 is turned on for a period of time, the inductor L1 is fully charged, the first drive signal LG1 becomes low, and the low-side power transistor M2 is turned off. At this point, the second signal obtained after the first indication signal DM_OVER1 and the first drive signal LG1 pass through the OR gate OR and the first inverter INV1 is high. After passing through the second inverter INV2, the output signal of the second inverter INV2 is low. In this way, after the second signal output by the first inverter INV1 turns high, it raises the voltage of the first capacitor C1, turning on the second N-type transistor MN2 and the first transistor N1. After the output signal of the second inverter INV2 turns low, the power supply voltage VDD charges the second capacitor C2 to the power supply voltage VDD through the second N-type transistor MN2. After the first transistor N1 is turned on, the voltage at the gate terminal PGATE1 of the first P-type transistor M3 is equal to the power supply voltage VDD.

[0126] When the first drive signal LG1 transitions to a low level, the second drive signal HG transitions to a high level, turning on the high-side power transistor M1. This causes the inductor L1 to charge the voltage VS1 at the source terminal of the first P-type transistor M3 through the high-side power transistor M1, causing the voltage VS1 at the source terminal of the first P-type transistor M3 to increase. Due to the large resistance of the first resistor R1 and the gate-source capacitance Cgs of the first P-type transistor M3, the voltage at the gate terminal PGATE1 of the first P-type transistor M3 increases with the increase in the voltage VS1 at the source terminal of the first P-type transistor M3, preventing the gate-source voltage Vgs2 of the first P-type transistor M3 from increasing. Therefore, after the first transistor N1 is turned on, it provides a pull-down force to stabilize the voltage at the gate terminal PGATE1 of the first P-type transistor M3 at the power supply voltage VDD. This ensures that when the voltage VS1 at the source terminal of the first P-type transistor M3 increases, the voltage at the gate terminal PGATE1 of the first P-type transistor M3 does not increase with the increase in the voltage VS1 at the source terminal of the first P-type transistor M3.

[0127] Furthermore, the gate-source voltage Vgs of the first P-type transistor M3 increases, the first P-type transistor M3 is turned on, and is in the saturation region, so that the voltage VS1 at the source end of the first P-type transistor M3 is charged to the output capacitor Cout1 through the first P-type transistor M3, so that the boost converter 1000 can be started in the down mode.

[0128] Furthermore, because the power supply voltage VDD is equal to the input voltage VIN1, the voltage VS1 at the source of the first P-type transistor M3 is equal to the sum of the input voltage VIN1 and the gate-source voltage Vgs2 of the first P-type transistor M3, i.e., VS1 = VIN1 + Vgs2. Consequently, during the on-state of the high-side power transistor M1, the current in the inductor L1 decreases and completes charging of the output voltage VOUT1, ensuring that the current in the inductor L1 does not continue to increase during the soft-start process and cause an overcurrent.

[0129] When the second driving signal HG1 is at a low level, the first driving signal LG1 turns high again to complete the charging of the inductor L1 and the first capacitor C1 .

[0130] When the output voltage VOUT1 is equal to or greater than the input voltage VIN1, the second indication signal DM_OVER2 output by the comparator DM comp turns to high level, the second P-type transistor MP1 is closed, and the third N-type transistor MN3, the fourth N-type transistor MN4 and the sixth N-type transistor MN6 are all turned on. Under the action of the closed second P-type transistor MP1, the voltage VA at the first end of the first transistor N1 stops being pulled up, and under the action of the turned-on third N-type transistor MN3, the voltage VA at the first end of the first transistor N1 gradually decreases from the power supply voltage VDD to zero voltage. The sixth N-type transistor MN6 is turned on, so that the first transistor N1 is also closed. At this time, the second indication signal DM_OVER2 turns to high level, indicating that the boost converter 1000 completes the start of the down mode.

[0131] After the second indication signal DM_OVER2 turns to high level, the first drive signal LG1 can be shielded, so that the voltage of the first capacitor C1 and the voltage of the second capacitor C2 no longer alternate. In this way, the capacitive drive circuit 130 stops driving the first transistor N1 to be turned on, so that the first transistor N1 is always turned off.

[0132] After the second indication signal DM_OVER2 turns to high level, the fourth N-type transistor MN4 is first turned on, and the voltage at the gate end PGATE1 of the first P-type transistor M3 will be slowly discharged through the second resistor R2 and the fourth N-type transistor MN4, so that the first P-type transistor M3 is switched from the saturation region to the linear region more smoothly. After a delay of the delay timer Tdly, the fifth N-type transistor MN5 is turned on, and the voltage at the gate end PGATE1 of the first P-type transistor M3 is pulled to zero voltage, so as to ensure that the first P-type transistor M3 is completely turned on and works in the linear region. Thus, the gate drive control circuit 100 completes the start-up process of the multi-battery BOOST application.

[0133] At this time, the static current of the gate drive control circuit 100 is generated by the voltage VS1 at the source end of the first P-type transistor M3 through the first resistor R1 and the fifth N-type transistor MN5 to the ground. Generally, due to the large resistance value of the first resistor R1, the static current of the gate drive control circuit 100 is very small, usually tens of microamperes.

[0134] The boost converter provided by the embodiment of the present application has the same beneficial effects as the gate drive control circuit provided by the embodiment of the present application, which will not be described here.

[0135] The embodiment of the present application also provides a chip, comprising: Figure 4 The gate drive control circuit 100 provided by the embodiment, and / or Figure 5 The boost converter 1000 provided by the embodiment.

[0136] Among them, the gate drive control circuit and the boost converter can be integrated into one chip or into different chips, and the embodiments of the present application do not specifically limit this.

[0137] The chip provided in the embodiment of the present application has the same beneficial effects as the gate drive control circuit provided in the embodiment of the present application, which will not be repeated here.

[0138] An embodiment of the present application also provides an electronic device, including: a chip.

[0139] In this application, electronic devices may include but are not limited to: tablet computers, routers, industrial robots and televisions.

[0140] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be repeated here.

[0141] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A gate drive control circuit, characterized in that: The gate drive control circuit is applied to a boost converter, the boost converter comprising: a high-side power transistor, a low-side power transistor, an inductor, a drive circuit and a first P-type transistor; the gate drive control circuit comprises: an indication signal output circuit, a pull-up circuit, a capacitive drive circuit and a first transistor; The first input end of the indication signal output circuit is used to access the output voltage of the boost converter, the second input end of the indication signal output circuit is used to access the input voltage of the boost converter, the output end of the indication signal output circuit is electrically connected to the control end of the pull-up circuit and the first input end of the capacitive drive circuit respectively, the second input end of the capacitive drive circuit is electrically connected to the first output end of the drive circuit, the output end of the capacitive drive circuit is electrically connected to the control end of the first transistor, the input end of the pull-up circuit is used to access the power supply voltage, the output end of the pull-up circuit and the power supply end of the capacitive drive circuit are both electrically connected to the first end of the first transistor, The second end of the first transistor is electrically connected to the gate end of the first P-type transistor, the drain end of the first P-type transistor is used to output the output voltage of the boost converter, the source end of the first P-type transistor is electrically connected to the second end of the high-side power transistor, the control end of the high-side power transistor is electrically connected to the second output end of the drive circuit, the first end of the high-side power transistor is electrically connected to the second end of the low-side power transistor, the first end of the inductor is electrically connected between the first end of the high-side power transistor and the second end of the low-side power transistor, the control end of the low-side power transistor is electrically connected to the first output end of the drive circuit, and the first end of the low-side power transistor is grounded; The indication signal output circuit is configured to transmit a first indication signal to the pull-up circuit and the capacitive driving circuit respectively according to the output voltage and the input voltage when the boost converter is started, wherein the first indication signal is configured to indicate that the output voltage is less than the input voltage; The pull-up circuit is configured to pull up the voltage of the first terminal of the first transistor to the power supply voltage according to the first indication signal; The capacitive driving circuit is used to obtain a first driving signal from the driving circuit, and drive the first transistor to be turned on according to the first driving signal and the first indication signal, so that the voltage at the gate terminal of the first P-type transistor is constant to the power supply voltage, so that when the inductor charges the voltage at the source terminal of the first P-type transistor through the high-side power transistor, the first P-type transistor is turned on and is in a saturation region.

2. The circuit according to claim 1, wherein: The gate drive control circuit further includes: a pull-down circuit and a switch-off circuit; The input end of the pull-down circuit and the control end of the switch-off circuit are both electrically connected to the output end of the indication signal output circuit, the output end of the pull-down circuit is electrically connected to the gate end of the first P-type transistor, the second end of the switch-off circuit is electrically connected to the control end of the first transistor, and the first end of the switch-off circuit is grounded; The indication signal output circuit is further configured to transmit a second indication signal to the pull-up circuit, the pull-down circuit, the switch off circuit, and the capacitive driving circuit respectively according to the output voltage and the input voltage, wherein the second indication signal is configured to indicate that the output voltage is equal to or greater than the input voltage; The pull-up circuit is further configured to stop pulling up the voltage of the first end of the first transistor according to the second indication signal; The switch-off circuit is configured to turn off the first transistor according to the second indication signal when the voltage at the first end of the first transistor stops being pulled up; The capacitive driving circuit is further configured to stop driving the first transistor to be turned on according to the second indication signal, so that the first transistor is always turned off; The pull-down circuit is used to pull down the voltage at the gate terminal of the first P-type transistor according to the second indication signal, so that the first P-type transistor is turned on and is in a linear region.

3. The circuit according to claim 2, characterized in that The gate drive control circuit further includes: a control circuit; A first terminal of the control circuit is electrically connected to the gate terminal of the first P-type transistor, and a second terminal of the control circuit is electrically connected to the source terminal of the first P-type transistor; The control circuit is used to control the first P-type transistor to be turned off when the boost converter is before starting.

4. The circuit according to claim 3, characterized in that The control circuit is a first resistor, and the resistance of the first resistor is greater than a preset resistance.

5. The circuit according to claim 2, characterized in that The capacitive driving circuit includes: a charge pump, an OR gate, and a first inverter; The first input terminal of the OR gate is electrically connected to the first output terminal of the drive circuit, the second input terminal of the OR gate is electrically connected to the output terminal of the indication signal output circuit, the output terminal of the OR gate is electrically connected to the input terminal of the first inverter, the output terminal of the first inverter is electrically connected to the input terminal of the charge pump, the power supply terminal of the charge pump is electrically connected to the first terminal of the first transistor, and the output terminal of the charge pump is electrically connected to the control terminal of the first transistor; The OR gate is configured to perform a logic operation on the first indication signal and the first drive signal to obtain a first signal, and transmit the first signal to the first inverter; The first inverter is configured to change the level state of the first signal to obtain a second signal, and transmit the second signal to the charge pump; The charge pump is configured to drive the first transistor to turn on according to the second signal; or, The OR gate is configured to perform a logic operation on the second indication signal and the first drive signal to obtain a third signal, and transmit the third signal to the first inverter; The first inverter is configured to change the level state of the third signal to obtain a fourth signal, and transmit the fourth signal to the charge pump; The charge pump is configured to stop driving the first transistor to be turned on according to the fourth signal.

6. The circuit according to claim 5, characterized in that The charge pump includes: a first N-type transistor, a second N-type transistor, a first capacitor, a second capacitor and a second inverter; An input terminal of the second inverter is electrically connected to an output terminal of the first inverter, an output terminal of the second inverter is electrically connected to a second plate of the second capacitor, a first plate of the second capacitor is electrically connected to a drain terminal of the second N-type transistor, a source terminal of the second N-type transistor and a source terminal of the first N-type transistor are both electrically connected to a first terminal of the first transistor, a drain terminal of the first N-type transistor is electrically connected to a first plate of the first capacitor, a gate terminal of the first N-type transistor is electrically connected between the first plate of the second capacitor and the drain terminal of the second N-type transistor, a gate terminal of the second N-type transistor and a control terminal of the first transistor are both electrically connected between the drain terminal of the first N-type transistor and the first plate of the first capacitor, and a second plate of the first capacitor is electrically connected between an input terminal of the second inverter and an output terminal of the first inverter.

7. The circuit according to claim 2, characterized in that The pull-up circuit includes: a second P-type transistor and a third N-type transistor; The source terminal of the second P-type transistor is used to access the power supply voltage, the gate terminal of the second P-type transistor and the gate terminal of the third N-type transistor are both electrically connected to the output terminal of the indication signal output circuit, the drain terminal of the second P-type transistor is electrically connected to the drain terminal of the third N-type transistor, the first terminal of the first transistor is electrically connected between the drain terminal of the second P-type transistor and the drain terminal of the third N-type transistor, and the source terminal of the third N-type transistor is grounded.

8. The circuit according to any one of claims 2 to 7, characterized in that: The pull-down circuit includes: a second resistor, a delay device, a fourth N-type transistor and a fifth N-type transistor; The first end of the second resistor and the drain end of the fifth N-type transistor are both electrically connected to the gate end of the first P-type transistor, the second end of the second resistor is electrically connected to the drain end of the fourth N-type transistor, the gate end of the fourth N-type transistor and the input end of the delay device are both electrically connected to the output end of the indication signal output circuit, the output end of the delay device is electrically connected to the gate end of the fifth N-type transistor, and the source end of the fourth N-type transistor and the source end of the fifth N-type transistor are both grounded.

9. The circuit according to claim 8, characterized in that The withstand voltage value of the first transistor, the withstand voltage value of the fourth N-type transistor, and the withstand voltage value of the fifth N-type transistor are all greater than a preset withstand voltage value.

10. The circuit according to any one of claims 1 to 7, characterized in that: The first transistor is an N-type transistor.

11. A boost converter, characterized in that: The boost converter comprises: a driving circuit, a first P-type transistor, a high-side power transistor, a low-side power transistor, an inductor, an output capacitor, and a gate drive control circuit according to any one of claims 1 to 10; The gate terminal of the first P-type transistor is electrically connected to the second terminal of the first transistor, the drain terminal of the P-type transistor is electrically connected to the first plate of the output capacitor, the drain terminal of the P-type transistor is also used to output the output voltage of the boost converter, the source terminal of the first P-type transistor is electrically connected to the second terminal of the high-side power transistor, the control terminal of the high-side power transistor is electrically connected to the second output terminal of the drive circuit, the first terminal of the high-side power transistor is electrically connected to the second terminal of the low-side power transistor, the first terminal of the inductor is electrically connected between the first terminal of the high-side power transistor and the second terminal of the low-side power transistor, the second terminal of the inductor is used to access the input voltage of the boost converter, the control terminal of the low-side power transistor is electrically connected to the first output terminal of the drive circuit, and the first terminal of the low-side power transistor and the second plate of the output capacitor are both grounded.

12. A chip, characterized in that: include: The gate drive control circuit according to any one of claims 1 to 10, and / or the boost converter according to claim 11.

13. An electronic device, characterized in that: include: The chip as claimed in claim 12.

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