Dead time adjusting method, adaptive ZVS control method and switching power supply

Abstract

The invention provides a dead time adjusting method, a self-adaptive ZVS control method and a switching power supply, and the method comprises the steps: 11) obtaining a first time length, collecting a second time length of a current period, and comparing the first time length with the second time length; step 12) if the first duration is greater than the second duration, reducing the conduction time of the clamping tube by a preset duration in the next period; if the first duration is smaller than the second duration, increasing the conduction time of the clamping tube by a preset duration in the next period; if the first duration is equal to the second duration, the conduction time of the clamping tube is kept in the next period; and (13) returning to the step (11) to sequentially adjust the dead time between the clamping tube and the main switch in each period. According to the invention, self-adaptive control in a dead time full-load range between the upper clamping tube and the main switching tube can be accurately realized, the safety is high, the loss of the main switching tube is small, the system efficiency is high, and the application range is wide.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a dead time adjustment method, an adaptive ZVS control method and a switching power supply. Background Art

[0002] In transformer-based switching power supplies, due to the presence of transformer leakage inductance, the drain end of the primary power switch tube is subjected to great switching stress. For this reason, leakage inductance absorption circuits are often used in engineering to recover the energy in the leakage inductance and reduce the switching stress borne by the drain end of the power switch tube. Commonly used leakage inductance recovery circuits include RCD (resistance, capacitance, diode) clamping circuits, LCD (inductance, capacitance, diode) clamping circuits, and active clamping circuits. Among them, the active clamping circuit uses active components with lower on-resistance and better switching characteristics to recover leakage inductance energy, reduce the stress of the main power tube, and further reduce the loss of the clamping circuit. Therefore, compared with passive clamping switching power supplies, active clamping switching power supplies can achieve higher efficiency and higher switching frequency; because the energy in the leakage inductance is absorbed, there is no leakage inductance spike during the main power tube startup process, the input voltage range is wider, and the EMI noise is smaller; in addition, the widespread application of third-generation GaN semiconductor power devices has also prompted ACF switching power supplies to develop in the direction of smaller volume and higher power density.

[0003] However, the dead time between the clamping tube and the main switch tube is fixed and not adjustable, which easily causes the system to fail to achieve ZVS (zero voltage start) control within the full load range, resulting in energy loss of the switch tube. In the prior art, the dead time is adjusted and calculated based on the input and output voltages and parasitic capacitance. Due to the particularity and complexity of the parasitic capacitance, the specific capacitance value cannot be accurately obtained. Therefore, the calculated dead time is not very accurate, and there is a risk that the clamping tube and the main switch tube are turned on at the same time.

[0004] Therefore, how to reduce the energy loss of the switch tube and improve the accuracy of zero voltage turn-on control has become one of the problems that technical personnel in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a dead time adjustment method, an adaptive ZVS control method and a switching power supply, which are used to solve the problems in the prior art that the dead time cannot be accurately controlled, and the adjustable range of the dead time is too narrow, resulting in the inability to achieve ZVS conduction control in the full load range. As the system operating frequency increases, the main switch tube loses more, the system efficiency does not reach the ideal value, and the development of active clamping zero voltage turn-on is restricted.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a dead time adjustment method, which is applied to an active clamp converter. The dead time adjustment method at least comprises:

[0008] Step 11) obtaining the calculated first duration, collecting the second duration of the current cycle, and comparing the first duration with the second duration; the first duration is the preset dead zone duration from the closing of the clamping tube to the opening of the main switch tube in the active clamping converter, and the second duration is the duration from the closing of the clamping tube to the complete release of the secondary inductor current of the transformer;

[0009] Step 12) if the first time length is greater than the second time length, then in the next cycle, the on-time of the clamp tube is reduced by a preset time length; if the first time length is less than the second time length, then in the next cycle, the on-time of the clamp tube is increased by a preset time length; if the first time length is equal to the second time length, then in the next cycle, the on-time of the clamp tube is maintained;

[0010] Step 13) Return to step 11) and sequentially adjust the dead time between the clamping tube and the main switch in each cycle.

[0011] Optionally, a turn-off moment of the clamp tube is acquired based on a driving signal of the clamp tube, and a first timing end signal is triggered when the turn-off time of the clamp tube reaches the first time.

[0012] Optionally, the turn-off moment of the clamp tube is obtained based on the driving signal of the clamp tube, and when the zero current detection signal is valid, it is determined that the secondary inductance current of the transformer is completely released, and a second timing end signal is triggered.

[0013] More optionally, the order in which the first timing end signal and the second timing end signal arrive is determined to determine the magnitude relationship between the first duration and the second duration.

[0014] To achieve the above objectives and other related objectives, the present invention further provides an adaptive ZVS control method, which at least includes:

[0015] Step 21) The circuit is soft-started, and the on-off of the main switch tube and the clamp tube is controlled based on the feedback signal of the active clamp converter, and the main switch tube and the clamp tube are complementary to each other;

[0016] Step 22) After the soft start is completed, the conduction time of the clamp tube is adjusted based on the above-mentioned dead time adjustment method, and then the first duration is adaptively adjusted to achieve adaptive zero voltage start control; wherein, when the turn-off time of the clamp tube in the current cycle reaches the set first duration and the zero voltage detection signal is valid, the main switch tube is turned on.

[0017] Optionally, when the output voltage of the active clamp converter is stable, it is determined that the soft start is ended.

[0018] Optionally, when the output current of the active clamp converter reaches a defined threshold, the main switch tube is driven to be turned off.

[0019] More optionally, after the main switch tube is turned off for a set time, the clamp tube is driven to be turned on.

[0020] To achieve the above object and other related objects, the present invention further provides a switching power supply, which includes: an active clamping converter, and the active clamping converter adopts the above dead time adjustment method to realize adaptive zero voltage turn-on control.

[0021] Optionally, the active clamp converter is a flyback topology structure or a forward topology structure.

[0022] As described above, the dead time adjustment method, adaptive ZVS control method and switching power supply of the present invention have the following beneficial effects:

[0023] 1. The dead time adjustment method, adaptive ZVS control method and switching power supply of the present invention can accurately realize the adaptive control of the dead time between the upper clamping tube and the main switch tube, so that the main switch tube can realize adaptive ZVS control, and the dead time has a wider adjustable range, realizing the adaptive adjustment of ZVS of the system within the full load range, with high safety, small loss of the main switch tube and high system efficiency.

[0024] 2. The dead time adjustment method and the adaptive ZVS control method of the present invention are applicable to flyback and forward active clamp converters and have a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a structural schematic diagram of an active clamp flyback converter.

[0026] Figure 2 Shown is the control operation waveform of the active clamp flyback converter.

[0027] Figure 3 It is a schematic flow chart of the dead time adjustment method of the present invention.

[0028] Figure 4 Shown is a structural schematic diagram of the adaptive zero voltage turn-on control module of the present invention.

[0029] Figure 5 Shown is a specific circuit diagram of the adaptive zero voltage turn-on control module of the present invention.

[0030] Figure 6 It is a schematic flow chart of the adaptive ZVS control method of the present invention.

[0031] Figure 7 Shown is a schematic diagram of key node waveforms of the adaptive ZVS control method of the present invention.

[0032] Figure 8 Shown is a schematic structural diagram of the driving circuit of the present invention.

[0033] Component number description

[0034] 1 Active Clamp Flyback Converter

[0035] 2. Driving circuit

[0036] 21 Adaptive zero voltage start control module

[0037] 211 Timing Unit

[0038] 212 Duration Collection Unit

[0039] 212a Controller

[0040] 212b Crossover

[0041] 212c Counter

[0042] 213 Comparison unit

[0043] 213a Comparison subunit

[0044] 214 Dead time adjustment unit

[0045] 214a Adjustment subunit

[0046] 22 Power-on reset module

[0047] 23 Logic control module

[0048] 24 Oscillator DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] See also Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0051] like Figure 1 The schematic diagram of the active clamp flyback converter 1 is shown, where Nc is the clamping tube, N 0 The main switch tube, R 1 is the clamping resistor, C RD is the clamping capacitor, T is the transformer, Rs is the sampling resistor, Do is the secondary rectifier diode, R L is the load, Co is the output capacitance, Ceq is the drain-source equivalent capacitance of the main switch tube, Coss is the parasitic capacitance of the main switch tube, C 3 is the parasitic capacitance of the clamp tube; to achieve ZVS control, the main switch tube N is usually used 0 The control mode of complementary conduction with the clamp tube Nc is as follows: Figure 2 FIG. 1 is a control operation waveform diagram of the active clamp flyback converter 1. In the active clamp flyback converter, the main switch tube N 0 According to its drain-source voltage V DS The output power is turned on and off by the main switch N 0 After turning on, the transformer primary inductor current i m Flowing through the main switch tube N 0 (denoted as I P ), showing a linear increase trend; when the output current sampling signal reaches the preset reference value (the preset reference value is adjustable, and different stages correspond to different values), the control system turns the main switch tube N 0 Turn off, transformer primary inductance L M The stored energy is instantly coupled to the secondary side, and at the same time the clamping tube Nc is connected to the main switch tube N 0 After being turned off, it is turned on after a delay of TDP_C (at this time, the main switch tube N 0 The drain-source voltage V DS=Vin+mVo, where Vin is the input voltage, Vo is the output voltage, and m is the turns ratio of the primary winding to the secondary winding in the transformer. After the clamp tube Nc is turned on, the energy in the leakage inductance can be transferred through the clamp resistor R 1 and clamping capacitor C RD To achieve energy recovery, the primary inductance of the transformer L M The current flows through the clamp tube Nc, and the primary inductance current of the transformer is recorded as i clamp , since the clamp tube Nc is opened, the transformer primary inductor current i m The momentary sag, but the main switch tube N 0 The parasitic capacitance between the drain and source, the transformer capacitance, and the capacitance of the secondary rectifier diode Do cause the transformer primary inductor current i m There will be an increasing process. According to the above analysis, in order to achieve ZVS control, the following zero voltage start-up conditions need to be met:

[0052]

[0053] Among them, i clamp- Direction and i clamp The specified currents are opposite in direction and equal in magnitude; i m- Direction and i m The specified currents are opposite in direction and equal in magnitude; due to the leakage inductance L K is very small, and part of the leakage inductance energy has been recovered, so formula (1) no longer considers the leakage inductance energy. From the above formula, it can be seen that the main switch tube N 0 Drain-source equivalent capacitance Ceq, clamping capacitance C RD The parasitic capacitance between the drain and source of the clamp tube Nc is discharged until the ZVS signal is detected. Therefore, in order to achieve ZVS control, the clamp tube Nc needs to be C The on-time of the clamping tube is continuously and adaptively adjusted, thereby adjusting the dead time between the closing of the clamping tube and the opening of the main switch tube (other active clamping converters also have the above problems).

[0054] like Figure 3 As shown, the present invention provides a dead time adjustment method, which is applied to an active clamp converter and is used to adjust the dead time between a clamp tube and a main switch tube. The dead time adjustment method includes:

[0055] Step 11) Obtain the calculated first time length T1, and collect the second time length t2 of the current cycle, and compare the first time length T1 with the second time length t2. The first time length T1 is obtained from the clamping transistor N in the active clamping converter. C Turn off to the main switch N 0The preset dead zone time between the opening and closing of the clamping tube N C The time from shutdown to complete release of the transformer secondary inductor current.

[0056] Step 12) If the first time length T1 is greater than the second time length t2, then in the next cycle, the conduction time T of the clamping tube Nc is reduced to H_ON If the first time length T1 is less than the second time length t2, the conduction time T of the clamp tube Nc is reduced in the next cycle. H_ON Increase the preset time length Δt. If the first time length T1 is equal to the second time length t2, then the conduction time T of the clamp tube Nc is maintained in the next cycle. H_ON .

[0057] Step 13) Return to step 11) and sequentially adjust the clamping tube Nc and the main switch N in each cycle. 0 The dead time between.

[0058] Specifically, the first duration T1 of the current cycle is obtained by calculation before the clamp tube Nc of the current cycle is turned off, and the actual dead zone duration of the current cycle must be greater than the calculated first duration T1 (i.e., the preset dead zone duration); as an example, in the initial state, the first duration T1 is determined according to the actual dead zone time of the previous cycle, and the first duration T1 (i.e., the preset dead zone duration) corresponding to each cycle is continuously adjusted through step 2) in each subsequent cycle. In this embodiment, the turn-off moment of the clamp tube Nc is obtained based on the drive signal PWM_C of the clamp tube Nc, that is, when the drive signal PWM_C of the clamp tube Nc jumps to a low level, a timing start signal is triggered to start timing the first duration T1; when the turn-off duration of the clamp tube Nc reaches the (preset) first duration T1, a first timing end signal is triggered.

[0059] Specifically, the second duration t2 of the current cycle is acquired in real time through the acquisition circuit. In this embodiment, the turn-off moment of the clamp tube Nc is acquired based on the drive signal of the clamp tube Nc. As above, when the drive signal PWM_C of the clamp tube Nc jumps to a low level, a timing start signal is triggered to start timing the second duration t2; when the zero current detection signal ZCD is valid, it is determined that the secondary inductance current of the transformer is completely released, and the second timing end signal is triggered. The zero current detection signal ZCD can be detected by the auxiliary winding ( Figure 1 The voltage on the output port (not shown) is detected; details are not described here.

[0060] It should be noted that any method (signal basis) that can obtain the first duration and the second duration is applicable to the present invention, and is not limited to this embodiment; including but not limited to converting the time signal into a voltage signal, and representing the length of time by the amplitude of the voltage, which will not be elaborated here.

[0061] Specifically, in this embodiment, the order of arrival of the first timing end signal and the second timing end signal is determined to determine the size relationship between the first duration T1 and the second duration t2. If the first timing end signal arrives before the second timing end signal, it means that the first duration T1 is less than the second duration t2; if the first timing end signal arrives after the second timing end signal, it means that the first duration T1 is greater than the second duration t2; if the first timing end signal and the second timing end signal arrive at the same time, it means that the first duration T1 is equal to the second duration t2. In actual use, any method that can determine the size relationship between the first duration T1 and the second duration t2 is applicable, and it is not repeated here; if the zero current detection signal ZCD is sampled within the first duration T1, it is determined that the first duration T1 is greater than the second duration t2, if the zero current detection signal ZCD is not sampled within the first duration T1, it is determined that the first duration T1 is less than the second duration t2, and if the zero current detection signal ZCD is sampled at the end of the first duration T1, it is determined that the first duration T1 is equal to the second duration t2.

[0062] Specifically, based on the comparison result of the current cycle, the clamping tube conduction time T of the next cycle is adjusted. H_ON , satisfying the following relationship:

[0063]

[0064] Among them, T H_ON (n+1) is the clamping tube conduction time of the (n+1)th cycle, T H_ON (n) is the clamp tube conduction time of the nth cycle. It should be noted that the preset time length Δt is not greater than the clamp tube conduction time. If the accuracy of regulation is to be improved, the preset time length Δt is set to a smaller value. If the efficiency of regulation is to be improved, the preset time length Δt is set to a larger value. The specific value of the preset time length Δt is set according to actual design needs, and can achieve adaptive changes in the dead time of each cycle; as an example, the preset time length Δt is configured as n working clock cycles, and n is a natural number greater than or equal to 1, including but not limited to 1 to 10.

[0065] like Figure 4As shown, in this embodiment, the dead time adjustment method of the present invention is implemented based on an adaptive zero voltage start control module 21, and the adaptive zero voltage start control module 21 includes:

[0066] A timing unit 211 , a duration collecting unit 212 , a comparing unit 213 and a dead time adjusting unit 214 .

[0067] like Figure 4 As shown, the timing unit 211 is connected to the output end of the dead time adjustment unit 214 , and times the first duration T1 provided by the dead time adjustment unit 214 .

[0068] Specifically, in the initial state, the timing unit 211 obtains the first duration T1 based on the zero voltage detection signal ZVS. At this time, the first duration T1 is the duration from the clamp tube being turned off to the main switch tube being turned on (actual measurement value). Subsequently, the timing unit 211 obtains the continuously updated first duration T1 (calculated preset value) based on the dead time adjustment unit 214. In this embodiment, the timing unit 211 is implemented by a timer, and the count value of the timer is set based on the first duration T1. The timer starts timing from the clamp tube being turned off. When the count value is reached, it is determined that the timing of the first duration T1 is ended, and a corresponding count end signal (as an example, high level is valid) is output; as the dead time adjustment unit 214 continuously adjusts the first duration T1, the set count value of the timer is also continuously updated.

[0069] It should be noted that any circuit structure that can time the first duration T1 and output a corresponding signal is applicable to the present invention, and is not limited to this embodiment.

[0070] like Figure 4 As shown, the duration acquisition unit 212 acquires the duration from the closing of the clamping tube in the active clamping converter to the complete release of the transformer secondary inductor current to obtain a second duration t2. Figure 5 As shown, in this embodiment, the duration acquisition unit 212 includes a controller 212a, a frequency divider 212b and a counter 212c.

[0071] Specifically, Figure 5As shown, in this embodiment, the controller 212a receives the driving signal PWM_C and the zero current detection signal ZCD of the clamp tube, triggers the timing start signal when the clamp tube is turned off, and triggers the timing end signal when the zero current detection signal ZCD is valid. As an example, the controller 212a is implemented by an RS trigger, the set end s of the RS trigger is connected to the driving signal PWM_C of the clamp tube, the reset end is connected to the zero current detection signal ZCD, and outputs the control signal of the timing start and end. When the driving signal PWM_C of the clamp tube jumps to a low level, the output signal CTR of the RS trigger jumps to a high level (i.e., the timing start signal), and when the zero current detection signal ZCD is valid at a high level, the output signal CTR of the RS trigger jumps to a low level (i.e., the timing end signal); in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0072] Specifically, Figure 5 As shown, in this embodiment, the frequency divider 212b is connected to the output end of the controller 212a and receives the working clock OSC. When the timing start signal is valid, the working clock OSC is divided into two parts in sequence. i times the frequency to obtain a counting clock; wherein, i=1, 2…n, n is the number of bits of the output signal of the duration acquisition unit 212, which is set to a natural number greater than 2. In actual use, the corresponding value can be set as needed. As an example, the frequency divider 212b includes n stages of D flip-flops cascaded in sequence, the data input terminal D of each D flip-flop is connected to the inverting output terminal Q-, and the positive output terminal Q+ outputs the divided frequency signal, wherein the first stage D flip-flop outputs a two-frequency divided signal 2clk, the second stage D flip-flop outputs a four-frequency divided signal 4clk, and so on, the nth stage D flip-flop outputs 2clk. n Frequency division signal 2 n clk; the clock terminal clk of the first-stage D flip-flop is connected to the working clock OSC, and the clock terminal clk of the subsequent-stage D flip-flop is connected to the inverting output terminal Q- of the previous-stage D flip-flop; the asynchronous reset terminal Clr of the first-stage D flip-flop is connected to the output terminal of the controller 212a, and the asynchronous reset terminal Clr of the second to n-th stage D flip-flops is connected to the inverting signal ZCD_N of the zero current detection signal; when the output signal CTR of the RS flip-flop jumps to a high level and the inverting signal ZCD_N of the zero current detection signal is a high level, the divider 212b starts frequency division; when the output signal CTR of the RS flip-flop jumps to a low level and the inverting signal ZCD_N of the zero current detection signal is a low level, the divider 212b is reset; in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0073] Specifically, Figure 5 As shown, in this embodiment, the counter 212c is connected to the output end of the controller 212a and the frequency divider 212b, and when the timing start signal is valid, timing is performed based on the counting clock, and when the timing end signal is valid, timing is stopped. As an example, the counter 212c includes n stages of D flip-flops cascaded in sequence, the asynchronous reset end Clr of each D flip-flop is connected to the delay signal CTR_D of the controller output signal, and the clock end of the i-th stage D flip-flop is connected to 2 i The counting clock with multiple frequency division (that is, the clock end of the first-stage D flip-flop receives the two-frequency division signal 2clk, the clock end of the second-stage D flip-flop receives the four-frequency division signal 4clk, and so on. The clock end of the n-th stage D flip-flop receives the 2 n Frequency division signal 2 n clk); the data input terminal D of the first-stage D flip-flop is connected to the preset voltage LV, and the data input terminal D of the subsequent D flip-flop is connected to the positive phase output terminal Q+ of the previous D flip-flop; the negative phase output terminal Q- of each D flip-flop outputs the timing result, and each D flip-flop outputs a one-bit signal (t 2_DET1 ,t 2_DET2 …t 2_DETn ), the n-bit signal constitutes the timing result (as an example, the high level is valid); when the delay signal CTR_D of the controller output signal jumps to a high level and receives the corresponding counting clock, the counter 212c starts counting; when the delay signal CTR_D of the controller output signal jumps to a low level or does not receive the corresponding counting clock, the counter 212c stops working; in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0074] like Figure 4 As shown, the comparison unit 213 is connected to the output ends of the timing unit 211 and the duration acquisition unit 212, and compares the first duration T1 with the second duration t2.

[0075] Specifically, Figure 5 As shown, in this embodiment, the comparison unit 213 includes n comparison subunits 213a, each comparison subunit 213a includes an exclusive OR gate XOR, a first NAND gate nand1, a second NAND gate nand2 and a third NAND gate nand3. The input end of the exclusive OR gate XOR is respectively connected to the output signal of the timing unit 211 and the corresponding bit output signal of the timer 212c (respectively denoted as t 2_DET1 ,t 2_DET2 …t 2_DETn), the input ends of the first NAND gate nand1 are respectively connected to the corresponding bit output signal of the timer 212c and the output signal of the XOR gate XOR, and output the first comparison result (respectively recorded as P11, P12...P1n); the input ends of the second NAND gate nand2 are respectively connected to the output signal of the timing unit 211 and the output signal of the XOR gate XOR, and output the second comparison result (respectively recorded as P21, P22...P2n); the input ends of the third NAND gate nand3 are respectively connected to the output signal of the timing unit 211 and the corresponding bit output signal of the timer, and output the third comparison result (respectively recorded as P31, P32...P3n); Among them, when the duration represented by the corresponding bit output signal of the timer 212c is less than the first duration T1, the first comparison result of the corresponding comparison subunit 213a jumps to a low level; when the duration represented by the corresponding bit output signal of the timer 212c is greater than the first duration T1, the second comparison result of the corresponding comparison subunit 213a jumps to a low level; when the duration represented by the corresponding bit output signal of the timer 212c is equal to the first duration T1, the third comparison result of the corresponding comparison subunit 213a jumps to a low level; in this example, taking the nth comparison unit 213a as an example, the first duration T1 is equal to the nth bit output signal t1 of the timer 212c. 2_DETn The one with high level, that is, the one that arrives first, is the one with shorter time. Combining the comparison results P11, P12...P1n, P21, P22...P2n, P31, P32...P3n, it can be known which one is longer between the first time length T1 and the second time length t2. The corresponding truth table is as follows:

[0076] T1 <![CDATA[t 2_DETn ]]> XOR Output P1n P2n P3n 0 0 0 1 1 1 0 1 1 0 1 1 <![CDATA[T1>t 2_DETn ]]> 1 0 1 1 0 1 <![CDATA[T1<t 2DETn ]]> 1 1 0 0 0 1 <![CDATA[T1=t 2DETn ]]>

[0077] In actual use, any circuit structure that can compare two signals representing durations and obtain a comparison result is applicable to the present invention, and is not limited to this embodiment.

[0078] like Figure 4 As shown, the dead time adjustment unit 214 is connected to the output end of the comparison unit 213, and adjusts the conduction time of the clamp tube and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero voltage turn-on control.

[0079] Specifically, Figure 5As shown, in this embodiment, the dead time adjustment unit 214 includes a time adjustment subunit 214b and n control subunits 214a, and each control subunit 214a is connected to the output end of each comparison subunit 213a in a one-to-one correspondence. Each control subunit 214a includes a first enabling transistor M1, a second enabling transistor M2, a third enabling transistor M3, a first transistor M4, a second transistor M5, and a third transistor M6. One end of each enabling transistor is connected to a preset voltage LV, and the other end is connected to the control end of each transistor. When the enable signal T SSE When invalid, each enabling tube is turned on to control each transistor to be turned off; wherein, the first enabling tube M1 is connected to the control end of the first transistor M4, the second enabling tube M2 is connected to the control end of the second transistor M5, and the third enabling tube M3 is connected to the control end of the third transistor M6. As an example, each enabling tube and transistor is a PMOS tube. When the enabling signal T SSE When the enable signal T is changed to low level (invalid), each enable transistor is turned on, so that the control end of each transistor is connected to the preset voltage LV (high level) and turned off. At this time, the dead time adjustment unit 214 does not work; when the enable signal T SSE When it jumps to high level (valid), each enabling tube is turned off, and the control end of each transistor is connected to the corresponding comparison result. At this time, the dead time adjustment unit 214 is in working state. One end of the first transistor M4 is connected to the preset voltage LV, the control end is connected to the corresponding first comparison result, and the other end generates a voltage to reduce the conduction time T of the clamping tube. H_ON One end of the second transistor M5 is connected to the preset voltage LV, the control end is connected to the corresponding second comparison result, and the other end generates a signal to increase the conduction time T of the clamp tube. H_ON One end of the third transistor M6 is connected to the preset voltage LV, the control end is connected to the corresponding third comparison result, and the other end generates a voltage to maintain the clamping tube conduction time T H_ON When the corresponding comparison result jumps to a low level, the corresponding transistor is turned on and a control signal for adjusting the on-time of the clamping tube is output. The time adjustment subunit 214b is connected to the output end of each control subunit 214a, and receives the working clock OSC. According to the control signal output by each control subunit 214a, the working clock OSC is used to generate a counting time, thereby realizing the on-time T of the clamping tube. H_ON adjustments.

[0080] It should be noted that, in this embodiment, when the circuit is in the startup phase, the enable signal T SSE Invalid, the adaptive zero voltage start control module 21 does not work; when the circuit is started, the enable signal T SSEThe jump becomes valid, and the adaptive zero voltage turn-on control module 21 starts to work. In addition, any circuit structure that can adjust the conduction time of the clamp tube and the first duration based on the output signal of the comparison unit 213 is applicable to the present invention, and is not limited to this embodiment.

[0081] like Figure 6 As shown, the present invention also provides an adaptive ZVS control method, the adaptive ZVS control method comprising:

[0082] Step 21) The circuit is soft-started, and the on-off of the main switch tube and the clamp tube is controlled based on the feedback signal of the active clamp converter, and the main switch tube and the clamp tube are complementary to each other.

[0083] Specifically, the circuit (i.e., the active clamp converter) is powered on and started, and the on and off moments of the main switch tube and the clamp tube are adjusted based on the feedback signal collected in real time. In this embodiment, the feedback signal includes but is not limited to the current sampling signal Vcs and the zero voltage detection signal ZVS of the main switch tube; wherein, the main switch tube N is turned on based on the zero voltage detection signal ZVS. 0 As the circuit starts, the current sampling signal Vcs of the main switch tube increases slowly, and the opening time of the main switch tube is gradually adjusted based on the comparison result of the current sampling signal Vcs of the main switch tube and a preset value (as an example, the preset value is set as the over-current protection point OCP), and the opening time of the main switch tube N is gradually adjusted. 0 After the fixed time is turned off, the clamp tube Nc is turned on. In actual use, any signal and control logic that can reflect the working state of the active clamp converter and can control the complementary conduction of the main switch tube and the clamp tube through feedback are applicable to the present invention, and are not limited to this embodiment. It should be noted that the complementary conduction mentioned in the present invention means that the main switch tube and the clamp tube are not turned on at the same time, and there is a dead time.

[0084] Specifically, in this embodiment, when the output voltage of the active clamp converter is stable, the soft start is determined to be finished; in actual use, any method that can reflect the completion of the power-on of the active clamp converter can be used to determine the end of the soft start.

[0085] Step 22) After the soft start is completed, the conduction time T of the clamp tube Nc is adjusted based on the dead time adjustment method. H_ON The first time length T1 is adjusted to realize adaptive zero voltage turn-on control; wherein, after the off time of the clamp tube Nc in the current cycle reaches the set first time length T1 and the zero voltage detection signal ZVS is valid, the main switch tube Nc 0 Turn on.

[0086] Specifically, Figure 7As shown, in this embodiment, when the off time of the clamp tube Nc in the current cycle reaches the set first time length T1 and the zero voltage detection signal ZVS is valid, the main switch tube Nc 0 If the zero voltage detection signal ZVS is detected within the first time length T1, the main switch tube N must be turned on after the first time length T1 ends. 0 If the zero voltage detection signal ZVS is not detected within the first time length T1, the main switch tube N is turned on after the zero voltage detection signal ZVS is detected. 0 If the zero voltage detection signal ZVS is detected at the end of the first time length T1, the main switch tube N is turned on when both conditions are met at the same time. 0 When the output current of the active clamp converter reaches the defined threshold value (as an example, in the circuit startup stage, when the output current sampling signal Vcs reaches the overcurrent protection point, it is determined that the output current has reached the defined threshold value; after the circuit is started, when the output current sampling signal Vcs reaches the preset reference value, it is determined that the output current has reached the defined threshold value, at which time, the output current sampling signal Vcs reaches the maximum value Vcsmax; the values ​​of the defined threshold values ​​in the two stages are different and are set as needed), the main switch tube N is driven. 0 The main switch tube N 0 After the set time is turned off, the clamp tube Nc is turned on. When the on time of the clamp tube Nc reaches the time obtained by the dead time adjustment method of the present invention, the clamp tube Nc is turned off. The first time length T1 and the second time length t2 are timed at the falling edge of the clamp tube Nc being turned off, wherein the first time length T1 is determined based on the on time of the clamp tube Nc in the previous cycle, that is, for the current cycle, the first time length T1 is equivalent to the set value, and the first timing end signal T1_end is obtained by counting to the set value; the second time length t2 is a real-time collected signal, and the timing of the second time length t2 ends when the zero current detection signal ZCD (equivalent to the second timing end signal) is valid in the current cycle. Based on the comparison result of the first time length T1 and the second time length t2, the on time of the clamp tube Nc in the next cycle is adjusted, and the first time length T1 corresponding to the next cycle is also adjusted accordingly, thereby realizing the adaptive zero voltage turn-on control of the main switch tube. For the specific adjustment relationship, please refer to the above, which will not be repeated here. In this example, it is assumed that the zero voltage detection signal ZVS, the zero current detection signal ZCD and the first timing end signal T1_end are all high level valid, and in actual use, they can also be set to low level valid, which is not limited to this embodiment.

[0087] like Figure 8As shown, in this embodiment, the adaptive ZVS control method of the present invention is implemented based on the driving circuit 2 of the present invention, and the driving circuit 2 includes: an adaptive zero voltage start-up control module 21, a power-on reset module 22 and a logic control module 23.

[0088] like Figure 8 As shown, the adaptive zero voltage turn-on control module 21 generates and adjusts the dead time between the closing of the clamp tube and the opening of the main switch tube in the next cycle based on the driving signal PWM_C of the clamp tube and the zero current detection signal ZCD. The structure and working principle of the adaptive zero voltage turn-on control module 21 are as mentioned above, and will not be described in detail here.

[0089] like Figure 8 As shown, the power-on reset module 22 is used to reset the logic control module 23 when the active clamp converter is powered on.

[0090] like Figure 8 As shown, the logic control module 23 is connected to the output ends of the adaptive zero voltage turn-on control module 21 and the power-on reset module 22, and receives the zero voltage detection signal ZVS and the output current sampling signal Vcs of the active clamp converter, and is used to generate the driving signal PWM_C of the clamp tube and the driving signal PWM_P of the main switch tube. The logic control module 23 can control the switching of the clamp tube and the main switch tube according to different strategies combined with various feedback signals of the active clamp converter, which will not be described one by one here.

[0091] like Figure 8 As shown, as another implementation of the present invention, the driving circuit 2 also includes an oscillator 24, which provides a working clock for the driving circuit 2 (including a clock with at least one frequency, and clocks with different frequencies can meet the needs of different circuits). The uses of the working clock include but are not limited to counting, adjusting the conduction time of the clamp tube and adjusting the first duration. The clock signals required in the driving circuit 2 can all be provided by the oscillator 24, which will not be elaborated here.

[0092] The present invention also provides a switching power supply, wherein the active clamped flyback converter adopts the dead time adjustment method of the present invention to realize adaptive zero voltage turn-on control. The active clamped converter includes but is not limited to a flyback topology structure and a forward topology structure, and any active clamped converter structure is applicable, which will not be described in detail here; as an example, when the active clamped converter is a flyback topology structure, it can be used Figure 1 The circuit structure shown.

[0093] In summary, the present invention provides a dead time adjustment method, an adaptive ZVS control method and a switching power supply, comprising: step 11) obtaining a calculated first time length, collecting a second time length of the current cycle, and comparing the first time length with the second time length; the first time length is a preset dead time length from the closing of the clamp tube in the active clamp converter to the opening of the main switch tube, and the second time length is a time length from the closing of the clamp tube to the complete release of the secondary inductor current of the transformer; step 12) if the first time length is greater than the second time length, then reducing the on-time of the clamp tube by a preset time length in the next cycle; if the first time length is less than the second time length, then increasing the on-time of the clamp tube by a preset time length in the next cycle; if the first time length is equal to the second time length, then maintaining the on-time of the clamp tube in the next cycle; step 13) returning to step 11) to sequentially adjust the dead time between the clamp tube and the main switch in each cycle. The dead time adjustment method, adaptive ZVS control method and switching power supply of the present invention can accurately realize the adaptive control of the dead time between the upper clamping tube and the main switch tube, so that the main switch tube can realize adaptive ZVS control, and the dead time has a wider adjustable range, realizing the adaptive adjustment of ZVS of the system within the full load range, with high safety, low loss of the main switch tube and high system efficiency; and the dead time adjustment method and adaptive ZVS control method of the present invention are suitable for flyback and forward active clamping converters, and have a wide range of applications. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A dead time adjustment method, applied to an active clamp converter, characterized in that: The dead time adjustment method at least comprises: Step 11) obtaining the calculated first duration, collecting the second duration of the current cycle, and comparing the first duration with the second duration; the first duration is the preset dead zone duration from the closing of the clamping tube to the opening of the main switch tube in the active clamping converter, and the second duration is the duration from the closing of the clamping tube to the complete release of the secondary inductor current of the transformer; Step 12) if the first time length is greater than the second time length, then in the next cycle, the on-time of the clamp tube is reduced by a preset time length; if the first time length is less than the second time length, then in the next cycle, the on-time of the clamp tube is increased by a preset time length; if the first time length is equal to the second time length, then in the next cycle, the on-time of the clamp tube is maintained; Step 13) Return to step 11) and sequentially adjust the dead time between the clamping tube and the main switch in each cycle.

2. The dead time adjustment method according to claim 1, characterized in that: The turn-off moment of the clamp tube is acquired based on the driving signal of the clamp tube, and the first timing end signal is triggered when the turn-off time of the clamp tube reaches the first time.

3. The dead time adjustment method according to claim 2, characterized in that: The turn-off moment of the clamp tube is obtained based on the driving signal of the clamp tube, and when the zero current detection signal is valid, it is determined that the secondary inductance current of the transformer is completely released, and a second timing end signal is triggered.

4. The dead time adjustment method according to claim 4, characterized in that: The order in which the first timing end signal and the second timing end signal arrive is determined to determine the magnitude relationship between the first duration and the second duration.

5. An adaptive ZVS control method, characterized in that: The adaptive ZVS control method at least comprises: Step 21) The circuit is soft-started, and the on-off of the main switch tube and the clamp tube is controlled based on the feedback signal of the active clamp converter, and the main switch tube and the clamp tube are complementary to each other; Step 22) After the soft start is completed, the conduction time of the clamp tube is adjusted based on the dead time adjustment method as described in any one of claims 1 to 4, and then the first duration is adaptively adjusted to achieve adaptive zero voltage start control; wherein, when the turn-off time of the clamp tube in the current cycle reaches the set first duration and the zero voltage detection signal is valid, the main switch tube is turned on.

6. The adaptive ZVS control method according to claim 5, characterized in that: When the output voltage of the active clamp converter is stable, it is determined that the soft start is ended.

7. The adaptive ZVS control method according to claim 5, characterized in that: When the output current of the active clamp converter reaches a defined threshold, the main switch tube is driven to be turned off.

8. The adaptive ZVS control method according to claim 5 or 7, characterized in that: After the main switch tube is turned off for a set time, the clamp tube is driven to be turned on.

9. A switching power supply, characterized in that: The switching power supply comprises: an active clamped converter, wherein the active clamped converter adopts the dead time adjustment method as described in any one of claims 1 to 4 to realize adaptive zero voltage turn-on control.

10. The switching power supply according to claim 9, characterized in that: The active clamp converter is a flyback topology structure or a forward topology structure.

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