Ring oscillator

Abstract

The present invention discloses a ring oscillator, which includes a bias module and an oscillation module. The bias module includes a current unit and a conversion unit connected to each other. The current unit is configured to generate a first current and a second current based on a reference current. The conversion unit is configured to generate a bias voltage based on the second current or generate a bias voltage based on the current difference between the first current and the second current, and generate a drive current based on the current difference between the first current and the second current. The oscillation module is connected to the bias module to receive the bias voltage and the drive current, and generate an oscillation signal based on the bias voltage and the drive current. The ring oscillator of the present invention obtains a stable bias voltage as the operating voltage of the oscillation module through two currents generated by the bias module based on one reference current, and obtains the drive current of the oscillation module based on the difference current between the two currents. This current has good temperature stability, thereby ensuring the oscillation accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and particularly relates to a ring oscillator. Background Art

[0002] As an important part of an integrated circuit system, an oscillator provides a stable clock signal for the system to ensure the normal operation of the chip. Among them, the ring oscillator is widely used due to its advantages such as low cost, simple structure, and small area.

[0003] The structure of a traditional ring oscillator is as Figure 1 shown. It is a cascade of an odd number (greater than or equal to 3 stages) of inverters. When the condition of "Barkhausen criterion" (loop gain greater than or equal to 1, phase shift 180 deg) is met, it will start to oscillate and output a clock signal with a frequency of f:

[0004]

[0005] Among them, is the number of cascaded inverters, is the delay of a single-stage inverter. For a long-channel circuit:

[0006]

[0007] Among them, are the rising delay and falling delay of the inverter respectively, is the equivalent capacitance of the input and output nodes of the inverter, , is a parameter related to the process material, are the width-to-length ratios of PMOS and NMOS respectively. are the threshold voltages of PMOS and NMOS. is the gate-source voltage of the MOS transistor.

[0008] Assuming , it can be obtained that:

[0009]

[0010] It can be seen from the above formula that the frequency output by the ring oscillator is sensitive to the power supply voltage, temperature, and process parameters. During the actual operation of the chip, due to the influence of signal coupling, noise, chip self-heating, etc., these parameters will inevitably change, which will cause the output clock frequency to shift, resulting in the unstable operation of the chip. Therefore, the application range of traditional ring oscillators is very limited and can only be applied to occasions where the frequency stability is not sensitive.

[0011] The information disclosed in this background section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of implication that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0012] An object of the present invention is to provide a ring oscillator that can ensure a stable signal frequency.

[0013] To achieve the above object, the technical solution provided by a specific embodiment of the present invention is as follows:

[0014] A ring oscillator includes: a bias module and an oscillation module; the bias module includes a current unit and a conversion unit connected to each other. The current unit is configured to generate a first current and a second current based on a reference current, and the conversion unit is configured to generate a bias voltage based on the second current or generate a bias voltage based on the current difference between the first current and the second current, and generate a driving current based on the current difference between the first current and the second current. The oscillation module is connected to the bias module to receive the bias voltage and the driving current, and generate an oscillation signal based on the bias voltage and the driving current.

[0015] In one or more embodiments of the present invention, the conversion unit includes a first load unit, and both ends of the first load unit are connected to the current unit. The current unit is configured to inject the first current into the first load unit and extract the second current from the first load unit to generate a bias voltage and a driving current at one end of the first load unit; or the conversion unit includes a current generation unit and a second load unit. The current generation unit is connected to the current unit to generate a third current based on the current difference between the first current and the second current. The first end of the second load unit is connected to the current generation unit to generate a bias voltage and a driving current based on the third current, and the second end of the second load unit is connected to the ground voltage; or the conversion unit includes a current generation unit, a second load unit, and a buffer. The current generation unit is connected to the current unit to generate a third current based on the current difference between the first current and the second current. The first end of the second load unit is connected to the current generation unit to generate a conversion voltage based on the third current. The second end of the second load unit is connected to the ground voltage. The input end of the buffer is connected to the first end of the second load unit to receive the conversion voltage, and the output end of the buffer is configured to output a bias voltage and a driving current.

[0016] In one or more embodiments of the present invention, the ring oscillator further includes a control module connected to the oscillation module and a signal processing module connected to the control module. The signal processing module is configured to perform signal processing on an enable signal to generate a control signal, and the control module is configured to control the operating state of the oscillation module based on the control signal.

[0017] In one or more embodiments of the present invention, the control module includes an OR gate. A first input terminal of the OR gate is connected to a signal processing module to receive a control signal. A second input terminal of the OR gate is connected to an input terminal of an oscillation module. An output terminal of the OR gate is connected to an output terminal of the oscillation module.

[0018] In one or more embodiments of the present invention, the signal processing module includes a capacitor and a delay inverter. A first end of the capacitor is connected to an input terminal of the delay inverter and is configured to receive a first enable signal. An output terminal of the delay inverter is configured to generate a control signal; or the signal processing module includes a capacitor, a delay inverter, and a first switching transistor. A first end of the capacitor is connected to an input terminal of the delay inverter and is configured to receive a first enable signal. An output terminal of the delay inverter is configured to generate a control signal. A first end and a second end of the first switching transistor are respectively connected to two ends of the capacitor. A control terminal of the first switching transistor is configured to receive a second enable signal; or the signal processing module includes a capacitor, a delay inverter, and a second switching transistor. A first end of the capacitor is connected to an input terminal of the delay inverter and is configured to receive a first enable signal. An output terminal of the delay inverter is configured to generate a control signal. A first end of the second switching transistor is connected to a reference voltage. A second end of the second switching transistor is connected to the input terminal of the delay inverter. A control terminal of the second switching transistor is connected to the output terminal of the delay inverter; or the signal processing module includes a capacitor, a delay inverter, a first switching transistor, and a second switching transistor. A first end of the capacitor is connected to an input terminal of the delay inverter and is configured to receive a first enable signal. An output terminal of the delay inverter is configured to generate a control signal. A first end and a second end of the first switching transistor are respectively connected to two ends of the capacitor. A control terminal of the first switching transistor is configured to receive a second enable signal. A first end of the second switching transistor is connected to a reference voltage. A second end of the second switching transistor is connected to the input terminal of the delay inverter. A control terminal of the second switching transistor is connected to the output terminal of the delay inverter; or the signal processing module includes a first inverting unit configured to invert an initial enable signal to generate a control signal.

[0019] In one or more embodiments of the present invention, the ring oscillator further includes a first level converter and a second inverting unit. The second inverting unit is connected to the signal processing module to invert a control signal to generate a first inverted signal. The first level converter is connected to the second inverting unit to receive the first inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the first inverted signal; or the ring oscillator further includes a first level converter, a second inverting unit, and a Schmitt trigger. The second inverting unit is connected to the signal processing module to invert a control signal to generate a first inverted signal. The first level converter is connected to the second inverting unit to receive the first inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the first inverted signal. The input terminal of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output terminal of the Schmitt trigger is used to generate a clock signal; or the ring oscillator further includes a first level converter, a second level converter, and a second inverting unit. The second inverting unit is connected to the signal processing module to invert a control signal to generate a first inverted signal. The second level converter is connected to the second inverting unit to convert the first inverted signal into a second inverted signal. The first level converter is connected to the second level converter to receive the second inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the second inverted signal; or the ring oscillator further includes a first level converter, a second level converter, a second inverting unit, and a Schmitt trigger. The second inverting unit is connected to the signal processing module to invert a control signal to generate a first inverted signal. The second level converter is connected to the second inverting unit to convert the first inverted signal into a second inverted signal. The first level converter is connected to the second level converter to receive the second inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the second inverted signal. The input terminal of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output terminal of the Schmitt trigger is used to generate a clock signal.

[0020] In one or more embodiments of the present invention, the oscillation module includes a plurality of first inverters and a loop control unit. The loop control unit includes a plurality of loop control subunits. Each of the loop control subunits and each first inverter form a plurality of oscillation loops. The loop control unit controls each loop control subunit based on an adjustment signal to select one of the oscillation loops to generate an oscillation signal.

[0021] In one or more embodiments of the present invention, the loop control subunit includes a second inverter. Each of the second inverters and at least two first inverters form an oscillation loop.

[0022] In one or more embodiments of the present invention, an even number of the first inverters that correspondingly form two branches constitute a group of inverter groups. The inverter groups are connected in sequence to form two branches, and each of the second inverters is respectively connected between the first inverters of each inverter group and forms an oscillation loop with one or more groups of inverter groups.

[0023] In one or more embodiments of the present invention, the ring oscillator further includes a decoder connected to each loop control sub-unit. The decoder is configured to decode an adjustment value to generate an adjustment signal to control each loop control sub-unit to select one of the oscillation loops to generate an oscillation signal; or the ring oscillator further includes a decoder and a logic unit. The decoder is connected to each loop control sub-unit, and the logic unit is connected to the decoder and each first inverter. The decoder is configured to decode an adjustment value to generate an adjustment signal to control each loop control sub-unit, and the logic unit is configured to perform a logic operation on the adjustment signal, or perform logic operations on the adjustment signal and a bias voltage respectively to generate corresponding logic signals to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logic signal.

[0024] Compared with the prior art, the ring oscillator of the present invention obtains a stable bias voltage as the operating voltage of the oscillation module through two currents generated by the bias module based on a reference current, and at the same time obtains the drive current of the oscillation module based on the differential current of the two currents. This current has good temperature stability, so as to ensure the oscillation accuracy. At the same time, this current can also be maintained at a relatively low level, which is suitable for generating oscillation signals with a relatively low frequency. Finally, the ring oscillator can output a stable and low-frequency clock signal.

[0025] Meanwhile, by adding a signal processing module and a control module, the enable signal can be delayed to be stable and then control the oscillation module to oscillate, thereby filtering out the situation of unstable frequency at the initial stage of the circuit operation.

[0026] Moreover, a plurality of oscillation loops are formed in the oscillation module, and the corresponding oscillation loop can be selected according to actual needs to oscillate and generate an oscillation signal with a target frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is the circuit schematic diagram of the ring oscillator in the prior art.

[0029] Figure 2 It is the structural schematic diagram of the ring oscillator in an embodiment of the present invention.

[0030] Figure 3 It is the circuit schematic diagram of the current unit in an embodiment of the present invention.

[0031] Figure 4 It is the circuit schematic diagram of the conversion unit in an embodiment of the present invention.

[0032] Figure 5 It is the circuit schematic diagram of the control module, signal processing module, and oscillation module in an embodiment of the present invention.

[0033] Figure 6 It is the circuit schematic diagram of the decoder in an embodiment of the present invention.

[0034] Figure 7 It is the circuit schematic diagram of the logic unit in an embodiment of the present invention.

[0035] Figure 8 It is the calibration step diagram of the ring oscillator under different process corners in an embodiment of the present invention.

[0036] Figure 9 It is the temperature characteristic diagram of the ring oscillator in an embodiment of the present invention.

[0037] Figure 10 It is the circuit schematic diagram of the conversion unit in another embodiment of the present invention.

[0038] Figure 11 It is the circuit schematic diagram of the signal processing module in another embodiment of the present invention.

[0039] Figure 12 It is the circuit schematic diagram of the oscillation module in another embodiment of the present invention. Detailed implementation manners

[0040] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0041] The terms "coupled", "connected", or "linked" in the specification include both direct connections and indirect connections. An indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; an indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches, follower circuits, etc. Additionally, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0042] In the detailed description of the specification, reference is made to the accompanying drawings that form a part thereof, in which like reference numerals always refer to like components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. Therefore, the following detailed description should not be taken as limiting.

[0043] The various operations in the specification can be described as a number of discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-related. Specifically, these operations can be performed in an order different from the presented order. The described operations can be performed in an order different from the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0044] For the purposes of the present application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present application, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0045] Various components and devices can be referred to or shown in the singular form herein (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular form can include multiple such elements in accordance with the teachings herein.

[0046] The specification describes the use of the phrase "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present application are synonymous.

[0047] Embodiment 1

[0048] As Figure 2As shown, the ring oscillator in the first embodiment of the present invention includes a bias module 10, an oscillation module 20, a control module 30, and a signal processing module 40.

[0049] Combined Figure 3 with Figure 4 As shown, the bias module 10 includes a connected current unit 11 and a conversion unit 12. The current unit 11 is used to generate a first current Ib1 and a second current Ib2 based on a reference current Isink, and the conversion unit 12 is used to generate a bias voltage VH based on the second current Ib2, and generate a drive current Ic based on the current difference between the first current Ib1 and the second current Ib2.

[0050] The oscillation module 20 is connected to the bias module 10 to receive the bias voltage VH and the drive current Ic, and generate an oscillation signal based on the bias voltage VH and the drive current Ic.

[0051] The control module 30 is connected to the oscillation module 20 and the signal processing module 40. The signal processing module 40 is used to perform signal processing on an enable signal to generate a control signal OSC_CON, and the control module 30 is used to control the operating state of the oscillation module 20 based on the control signal OSC_CON.

[0052] As Figure 3 shown, the current unit 11 is used to mirror the reference current Isink to generate a first current Ib1 and a second current Ib2.

[0053] Specifically, the current unit 11 includes an input unit, a first mirror output unit, and a second mirror output unit. Among them, the input unit is used to receive the reference current Isink, the first mirror output unit is connected to the input unit to mirror the reference current Isink to generate a first current Ib1, and the second mirror output unit is connected to the input unit and mirrors the reference current Isink to generate a second current Ib2.

[0054] In one embodiment, the reference current Isink is generated by a bandgap reference circuit, and the reference current Isink has a positive temperature coefficient.

[0055] Furthermore, the input unit includes a resistor R, a transistor Mn3, and a transistor Mn4. The first end of the resistor R is connected to the bandgap reference circuit to receive the reference current Isink, the second end of the resistor R is connected to the second end of the transistor Mn3, the first end of the transistor Mn3 is connected to the second end of the transistor Mn4, and the first end of the transistor Mn4 is connected to the ground voltage GND. The control end of the transistor Mn3 is connected to the first end of the resistor R, and the control end of the transistor Mn4 is connected to the second end of the resistor R.

[0056] The first mirror output unit includes transistor Mn5, transistor Mn6, transistor Mn7, transistor Mn8, transistor Mp3, transistor Mp4, transistor Mp5, transistor Mp6, and transistor Mp7.

[0057] The control terminals of transistor Mn5 and transistor Mn7 are connected to the first end of resistor R, and the control terminals of transistor Mn6 and transistor Mn8 are connected to the second end of resistor R. The first ends of transistor Mn6 and transistor Mn8 are connected to the ground voltage GND. The second end of transistor Mn6 is connected to the first end of transistor Mn5, the second end of transistor Mn8 is connected to the first end of transistor Mn7, the second end of transistor Mn5 is connected to the second end of transistor Mp3, the control terminal of transistor Mp3, the control terminal of transistor Mp4, and the control terminal of transistor Mp7. The second end of transistor Mn7 is connected to the second end of transistor Mp4, the control terminal of transistor Mp5, and the control terminal of transistor Mp6. The first ends of transistor Mp3, transistor Mp5, and transistor Mp6 are connected to the power supply voltage. The first end of transistor Mp4 is connected to the second end of transistor Mp5. The second end of transistor Mp6 is connected to the first end of transistor Mp7. The second end of transistor Mp7 is used to generate the first current Ib1.

[0058] The second mirror output unit includes transistor Mn9 and transistor Mn10. The control terminal of transistor Mn9 is connected to the first end of resistor R, the control terminal of transistor Mn10 is connected to the second end of resistor R. The first end of transistor Mn10 is connected to the ground voltage GND. The second end of transistor Mn10 is connected to the first end of transistor Mn9. The second end of transistor Mn9 is used to generate the second current Ib2.

[0059] Since the reference current Isink has a positive temperature coefficient, and both the first current Ib1 and the second current Ib2 are generated by mirroring the reference current Isink, the first current Ib1 and the second current Ib2 also have a positive temperature coefficient. By changing the sizes of the transistors in the input unit, the first mirror output unit, and the second mirror output unit, the magnitudes of the first current Ib1 and the second current Ib2 can be changed. In one embodiment, the first current Ib1 is greater than the second current Ib2.

[0060] In other embodiments, the current unit 11 can also sample other forms of current mirror circuits to mirror the reference current Isink to generate the first current Ib1 and the second current Ib2.

[0061] Such as Figure 4As shown, the conversion unit 12 includes a first load unit. Both ends of the first load unit are connected to the current unit 11, and the current unit 11 is configured to inject a first current Ib1 into the first load unit and extract a second current Ib2 from the first load unit to generate a bias voltage VH and a drive current Ic at one end of the first load unit.

[0062] Specifically, the first load unit may include a transistor Mp1 and a transistor Mn1. The first end of the transistor Mp1 is connected to the second end of the transistor Mp7 and forms the first end of the first load unit, receiving the injected first current Ib1. The control end of the transistor Mp1, the second end of the transistor Mp1, the second end of the transistor Mn1, and the control end of the transistor Mn1 are connected. The first end of the transistor Mn1 is connected to the second end of the transistor Mn9 and forms the second end of the first load unit, from which the second current Ib2 is extracted. The first end of the first load unit is connected to the oscillation module 20 to output the bias voltage VH and the drive current Ic.

[0063] By injecting the first current Ib1 into the first end of the transistor Mp1 and extracting the second current Ib2 from the first end of the transistor Mn1, the magnitude of the drive current Ic flowing out from the first end of the transistor Mp1 is Ib1 - Ib2. Since both the first current Ib1 and the second current Ib2 are positive temperature coefficient currents, their current difference can cancel out the temperature coefficient with each other, making the drive current Ic less affected by temperature and having good stability.

[0064] This drive current Ic ultimately provides the current required for the operation of the oscillation module 20, thereby ensuring that while the oscillation module 20 has a stable bias voltage VH, the current it consumes is also at a stable level, making the output frequency more stable. At the same time, the drive current Ic can be controlled to a relatively small current value, which is beneficial for the oscillation module 20 to generate a low-frequency oscillation signal.

[0065] In other embodiments, the first load unit may also include one or more resistors or other devices connected between the second end of the transistor Mp7 and the second end of the transistor Mn9, and multiple such devices may be connected in series, in parallel, or in other connection manners.

[0066] As Figure 5 shown, the control module 30 may include an OR gate OR. The first input terminal of the OR gate OR is connected to the signal processing module 40 to receive a control signal OSC_CON. The second input terminal of the OR gate OR is connected to the input terminal of the oscillation module 20. The output terminal of the OR gate OR is connected to the output terminal of the oscillation module 20.

[0067] In a specific embodiment, for the ring oscillator, the oscillation module 20 generally includes an inverter oscillation loop formed by connecting an odd number of inverters in series. The input end and the output end of the oscillation module 20 can be the connection nodes of any two inverters in the oscillation loop. Among them, the output end of the previous inverter can be used as the input end of the oscillation module 20 and connected to the second input end of the OR gate OR, and the input end of the subsequent inverter can be used as the output end of the oscillation module 20 and connected to the output end of the OR gate OR. At this time, when the first input end of the OR gate OR receives a high level, the output of the OR gate OR is also controlled to be at a high level, so the oscillation module 20 does not oscillate and maintains a high-level output; when the first input end of the OR gate OR receives a low level, the output of the OR gate OR will follow the level on the second input end of the OR gate OR, so the oscillation module 20 can normally oscillate and output an oscillation signal.

[0068] In other embodiments, the OR gate OR can also be connected to the oscillation module 20 according to the specific form of the oscillation module 20, so that the OR gate OR can control the oscillation module 20 to oscillate. The control module 30 can also include a switch or other devices connected between the input end and the output end of the oscillation module 20. These devices can control their own opening and closing based on the control signal OSC_CON, and control the oscillation module 20 to oscillate based on their own opening and closing.

[0069] As Figure 5 shown, the signal processing module 40 includes a capacitor C1, a delay inverter Nlc, a first switching transistor Mn2, and a second switching transistor Mp2.

[0070] Among them, the first end of the capacitor C1 is connected to the input end of the delay inverter Nlc and is used to receive the first enable signal EN. The output end of the delay inverter Nlc is used to generate the control signal OSC_CON. The first end and the second end of the first switching transistor Mn2 are respectively connected to both ends of the capacitor C1. The control end of the first switching transistor Mn2 is used to receive the second enable signal ENB. The first end of the second switching transistor Mp2 is connected to the reference voltage. The second end of the second switching transistor Mp2 is connected to the input end of the delay inverter Nlc. The control end of the second switching transistor Mp2 is connected to the output end of the delay inverter Nlc.

[0071] In one embodiment, the initial enable signal OSC_EN is inverted by the inverter N1 to obtain the second enable signal ENB, and the second enable signal ENB is inverted by the inverter N2 to obtain the first enable signal EN. In other embodiments, the first enable signal EN and the second enable signal ENB can also be set as other signals according to needs.

[0072] In one embodiment, the reference voltage is the bias voltage VH. In other embodiments, the reference voltage can also be set as other voltages according to needs.

[0073] When the initial enable signal OSC_EN is at a low level, the second enable signal ENB is at a high level, and the first enable signal EN is at a low level. The first switching transistor Mn2 is turned on, both ends of the capacitor C1 are at a low level, and the control signal OSC_CON generated by the delay inverter Nlc is at a high level, and the second switching transistor Mp2 is turned off.

[0074] At this time, the OR gate OR always receives a high-level signal, and the output is also at a high level. The oscillation module 20 continuously outputs a high level and does not oscillate.

[0075] When the initial enable signal OSC_EN becomes high, the second enable signal ENB is low, and the first enable signal EN is high. The first switching transistor Mn2 is turned off, and the capacitor C1 starts to charge. The voltage at the first end of the capacitor C1 gradually rises to a high level. After a certain period of delay by the delay inverter Nlc, the control signal OSC_CON flips low. The second switching transistor Mp2 is turned on, pulling up the voltage at the input end of the delay inverter Nlc, locking the control signal OSC_CON at a low level.

[0076] At this time, the first input terminal of the OR gate OR is at a low level, and the level of the output terminal of the OR gate OR is the same as the level of the second input terminal of the OR gate OR, and the oscillation module 20 starts to oscillate.

[0077] The signal processing module 40 delays the initial enable signal OSC_EN to generate a control signal OSC_CON, and controls the oscillation module 20 to oscillate based on the control signal OSC_CON, which can filter out a period of time with unstable frequency when the initial enable signal OSC_EN just flips high.

[0078] In other embodiments, the first switching transistor Mn2 and / or the second switching transistor Mp2 may not be provided in the signal processing module 40. When the first switching transistor Mn2 is not provided, the second end of the capacitor C1 can be connected to the ground voltage GND or other voltages as needed.

[0079] As Figure 5 shown, in one embodiment, the ring oscillator may further include a first level converter LS1, a second level converter LS2, a second inverter unit N3, and a Schmitt trigger SMT.

[0080] Among them, the input end of the second inverting unit N3 is connected to the output end of the delay inverter N1c to receive the control signal OSC_CON. The second inverting unit N3 is used to invert the control signal OSC_CON to generate a first inverted signal. The input end of the second level converter LS2 is connected to the output end of the second inverting unit N3 to receive the first inverted signal. The second level converter LS2 is used to convert the first inverted signal into a second inverted signal EN_Delay. The enable end of the first level converter LS1 is connected to the output end of the second level converter LS2 to receive the second inverted signal EN_Delay. The input end of the first level converter LS1 is connected to the output end of the oscillation module 20 to receive the oscillation signal. The first level converter LS1 is used to convert the oscillation signal into an output signal based on the control of the second inverted signal EN_Delay. The input end of the Schmitt trigger SMT is connected to the output end of the first level converter LS1 to receive the output signal. The output end of the Schmitt trigger SMT is used to generate the clock signal OSC_OUT.

[0081] Before the control signal OSC_CON changes from high level to low level, the first inverted signal generated by the second inverting unit remains low level. The enable end of the second level converter LS2 can receive the initial enable signal OSC_EN or the power supply voltage. At this time, regardless of whether the second level converter LS2 works properly, the second inverted signal EN_Delay also remains low level all the time. The first level converter LS1 does not work, and the clock signal OSC_OUT output by the Schmitt trigger SMT is a constant 0 or 1.

[0082] When the control signal OSC_CON changes to low level, the oscillation module 20 starts to oscillate, and the first inverted signal is high level. At this time, the second level converter LS2 has worked properly. The second level converter LS2 converts the first inverted signal into a second inverted signal EN_Delay with appropriate voltage. The first level converter LS1 starts to work normally based on the second inverted signal EN_Delay, and performs level conversion on the oscillation signal to output an output signal in the specified voltage domain. Finally, the Schmitt trigger SMT shapes the output signal again to obtain a clock signal OSC_OUT with stable frequency.

[0083] In other embodiments, the second level converter LS2 and / or the Schmitt trigger SMT may not be provided. When the second level converter LS2 is not provided, the enable end of the first level converter LS1 can be directly connected to the output end of the second inverting unit to receive the first inverted signal, and convert the oscillation signal into an output signal based on the control of the first inverted signal. When the Schmitt trigger SMT is not provided, the output signal generated by the first level converter LS1 is directly used as the output signal of the entire ring oscillator.

[0084] Such asFigure 5 As shown in Figure 5 , the oscillation module 20 includes a plurality of first inverters and a loop control unit. The loop control unit includes a plurality of loop control sub-units, and each loop control sub-unit and each first inverter form a plurality of oscillation loops. The loop control unit controls each loop control sub-unit based on an adjustment signal to select one of the oscillation loops to generate an oscillation signal.

[0085] In one embodiment, there are 2N first inverters, namely the first inverter Na1 to the first inverter NaN, and the first inverter Nb1 to the first inverter NbN, where N≥2. In other embodiments, the number of first inverters can also be set to other values.

[0086] Specifically, the loop control sub-unit may include a second inverter, and each second inverter and at least two first inverters form an oscillation loop.

[0087] In one embodiment, there are N second inverters, namely the second inverter Nc1 to the second inverter NcN. In other embodiments, the number of second inverters can also be set to other values.

[0088] The adjustment signal can be used as the enable signal of the second inverter, and each second inverter can be turned on or off based on the adjustment signal. When the second inverter is turned on, the oscillation loop formed by the second inverter is conducted and starts to oscillate. When the second inverter is turned off, the oscillation loop formed by the second inverter is disconnected and does not oscillate.

[0089] In one embodiment, an even number of first inverters that form two branches correspondingly form a group of inverter groups. The inverter groups are connected in sequence to form two branches, and each second inverter is respectively connected between the first inverters of each inverter group and forms an oscillation loop with one or more groups of inverter groups.

[0090] As Figure 5 shown, in a specific embodiment, a group of inverter groups can be formed by the first inverter Nai and the first inverter Nbi, where 1≤i≤N. These inverter groups are connected in sequence to form two branches, namely the first branch formed by the first inverter Na1 to the first inverter NaN, and the second branch formed by the first inverter Nb1 to the first inverter NbN.

[0091] Among them, the input terminal of the first inverter Na1 is the output terminal of the oscillation module 20 and is connected to the output terminal of the OR gate OR. The output terminal of the first inverter Nb1 is the input terminal of the oscillation module 20 and is connected to the second input terminal of the OR gate OR.

[0092] The input terminal of the second inverter Nci can be connected to the output terminal of the first inverter Nai, and the output terminal of the second inverter Nci can be connected to the input terminal of the first inverter Nbi. At this time, the second inverter Nci and the first inverters Na1 to Nai, and the first inverters Nb1 to Nbi form an oscillation loop, and a total of 2i + 1 inverters are connected to this loop. Only when the second inverter Nci is turned on, this oscillation loop can conduct and oscillate, and when the second inverter Nci is turned off, this oscillation loop is turned off.

[0093] In other embodiments, an inverter group can also be formed by other first inverters, and the second inverters connected between the inverter groups can also be other odd numbers.

[0094] Such as Figure 6 and Figure 7 As shown, the ring oscillator in this embodiment may further include a decoder 50 and a logic unit 60.

[0095] The decoder 50 is connected to each loop control subunit, and the logic unit 60 is connected to the decoder 50 and each first inverter. The decoder 50 is used to decode the adjustment value to generate an adjustment signal to control each loop control subunit. The logic unit 60 is used to perform logical operations on the adjustment signal and the bias voltage VH respectively to generate corresponding logical signals to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logical signal.

[0096] Specifically, as shown in Figure 5 , Figure 6 and Figure 7 The decoder 50 is connected to the enable terminal of each second inverter. The decoder 50 decodes the adjustment value to generate adjustment signals SW1 to SWN, and conveys the adjustment signals SW1 to SWN to the corresponding second inverters Nc1 to NcN to control the second inverters to turn on or off. In this embodiment, only one second inverter is turned on by the adjustment signal at the same time, that is, only one adjustment signal is at a high level at the same time, and the others are at a low level.

[0097] The logic unit 60 is connected to the enable terminal of each first inverter. The logic unit 60 performs logical operations on the adjustment signals SW1 to SWN and the bias voltage VH respectively to generate corresponding logical signals: logical signals SW1a to SWNa, and conveys the logical signals to the enable terminals of the corresponding first inverters, that is, conveys the logical signal SWia to the enable terminals of the first inverter Nai and the first inverter Nbi to control each first inverter.

[0098] In this embodiment, when the second inverter Nci is turned on, the logic unit 60 controls the first inverters Na1 to Nai and the first inverters Nb1 to Nbi to also turn on, and other first inverters to turn off, so that the oscillation loop formed by the second inverter Nci and the first inverters Na1 to Nai and the first inverters Nb1 to Nbi is all turned on and starts to oscillate, while other oscillation loops do not work.

[0099] In a specific embodiment, N is 16, and the decoder 50 can be a 4-16 decoder, that is, it can decode the 4-bit binary adjustment values DEC0, DEC1, DEC2, and DEC3 and output 16 independent adjustment signals: adjustment signals SW1 to SW16. The 4-16 decoding can be implemented by existing technologies and will not be elaborated here. In other embodiments, other decoders can also be selected according to the form of the adjustment value and the actual needs of the adjustment signal.

[0100] The logic unit 60 includes 16 logic sub-units, namely the first logic sub-unit 61 to the sixteenth logic sub-unit 616.

[0101] Among them, the first logic sub-unit 61 includes two serially connected inverters. The first logic sub-unit 61 is used to invert the bias voltage VH twice to generate a logic signal SW1a. The logic signal SW1a is always at a high level, controlling the first inverters Na1 and Nb1 to always be turned on.

[0102] The second logic sub-unit 62 includes three serially connected inverters. The second logic sub-unit 62 is used to invert the adjustment signal SW1 to generate a logic signal SW2a. The logic signal SW2a is at a low level only when the adjustment signal SW1 is at a high level, that is, when the second inverter Nc1 is turned on, and is at a high level otherwise, controlling the first inverters Na2 and Nb2 to turn off when the second inverter Nc1 is turned on and to turn on at other times.

[0103] The third logic sub-unit 63 includes three inverters and a NOR gate. The input terminal of the first inverter is connected to the output terminal of the first inverter in the second logic sub-unit 62, and the output terminal is connected to the first input terminal of the NOR gate. The second input terminal of the NOR gate is used to receive the adjustment signal SW2. The output terminal of the NOR gate is connected to the second and third serially connected inverters, and finally generates a logic signal SW3a that is in phase with the output signal of the NOR gate.

[0104] Specifically, the two input terminals of the NOR gate respectively receive the adjustment signal SW2 and the signal in phase with the adjustment signal SW1. That is, only when both the adjustment signal SW2 and the adjustment signal SW1 are at low level, the output of the exclusive-OR gate OR is at high level; otherwise, it is at low level. Therefore, it can be regarded that only when the second inverter Nc1 is turned on and the second inverter Nc2 is turned off, the logic signal SW3a is at high level and controls the first inverter Na3 and the first inverter Nb3 to be turned on.

[0105] The structures and working principles of the fourth logic subunit 64 to the sixteenth logic subunit 616 are similar to those of the third logic subunit 63, and will not be elaborated here.

[0106] In other embodiments, the first logic subunit 61 can also generate a logic signal SW1a at high level based on other voltages, so that the first inverter Na1 and the first inverter Nb1 are in a normally open state. It is also possible not to provide the first logic subunit 61 and directly place the first inverter Na1 and the first inverter Nb1 in a normally open state. At this time, the logic unit 60 is used to only perform logical operations on the adjustment signal to generate corresponding logic signals to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logic signal.

[0107] In other embodiments, the specific structure and working principle of the logic unit 60 can be adjusted according to the specific form of the adjustment signal and the oscillation module 20.

[0108] In one embodiment, the power supply terminals of all the first inverters and second inverters in the oscillation module 20 are connected to the first end of the transistor Mp1 in the bias module 10 to obtain the bias voltage VH as the working voltage and the drive current Ic as the working current. Thanks to the good stability of the drive current Ic and the bias voltage VH, the output frequency of the oscillation loop composed of the first inverter and the second inverter is less affected by temperature, process corner, etc., and the stability is significantly improved.

[0109] The signal processing module 40, the control module 30, the decoder 50, the logic unit 60, etc. in the ring oscillator can also use the bias voltage VH as the working voltage, and at the same time provide the working current through the drive current Ic, or other power supply voltages can also be used. The voltage division of these circuit parts will not affect the working characteristics of the oscillation loop.

[0110] In one embodiment, the transistors and switching transistors mentioned in the present application are all MOS transistors. The first ends of the transistors and switching transistors are all source electrodes, the second ends of the transistors and switching transistors are all drain electrodes, and the control ends of the transistors and switching transistors are all gate electrodes. In other embodiments, other devices may also be used for the transistors and switching transistors. Each P-type transistor may be replaced with an N-type transistor, and each N-type transistor may be replaced with a P-type transistor. Then, the connection and control methods only need to be adjusted adaptively.

[0111] During the actual working process, first, the bias module 10 generates a first current Ib1 and a second current Ib2 based on the reference current Isink, and then generates a bias voltage VH and a drive current Ic provided to the oscillation module 20 based on the first current Ib1 and the second current Ib2. Since both the bias voltage VH and the drive current Ic have good stability, the output frequency of the oscillation module 20 is more stable. At the same time, since the drive current Ic can be controlled to a relatively small current value, it is also beneficial to control the oscillation module 20 to generate a low-frequency oscillation signal.

[0112] Next, after the initial enable signal OSC_EN goes high, the signal processing module 40 delays it to generate a control signal OSC_CON, and then controls the oscillation module 20 to oscillate based on the control signal OSC_CON, so that the oscillation module 20 starts to oscillate later than the rising edge of the initial enable signal OSC_EN. Thus, a period of time with unstable frequency at the beginning of the operation of the ring oscillator can be filtered out, ensuring that the frequency of the oscillation signal is always stable.

[0113] Finally, the oscillation signal generated by the oscillation module 20 can also be processed by the first level converter LS1 and the Schmitt trigger SMT to finally generate a clock signal within the target range.

[0114] When the oscillation module 20 oscillates to generate an oscillation signal, an adjustment value can be set, and a corresponding adjustment signal and logic signal are generated based on the adjustment value to select a specified oscillation loop for oscillation, thereby changing the number of inverters connected to the oscillation loop. By increasing / decreasing the number of inverters in the oscillation loop, frequency calibration can be achieved, and further, the frequency deviation under different process corners can be calibrated, enabling it to more accurately reach the target frequency without introducing other errors when adjusting the frequency.

[0115] Figure 8 The calibration step sizes under different process corners are shown. It can be seen that the maximum calibration step size is 3.4%, which means that the output frequency accuracy of the system after calibration can be within ±1.7%.

[0116] Figure 9As shown after calibration, when the temperature changes from -40°C to 125°C, the output frequency of the ring oscillator changes. It can be seen that the output frequency offset is between -7% and 5%. Compared with existing ring oscillator products, the stability has been effectively improved.

[0117] Embodiment 2

[0118] As Figure 10 shown, the ring oscillator in this embodiment is only different from that in Embodiment 1 in the conversion unit 12, and the structures and working principles of other modules are the same as those in Embodiment 1. Only the conversion unit 12 will be described below, and other aspects will not be elaborated too much.

[0119] In this embodiment, the conversion unit 12 of the ring oscillator includes a current generation unit, a second load unit, and a buffer.

[0120] Among them, the current generation unit is connected to the current unit 11 to generate a third current I3 based on the current difference between the first current Ib1 and the second current Ib2. The first end of the second load unit is connected to the current generation unit to generate a conversion voltage VHa based on the third current I3. The second end of the second load unit is connected to the ground voltage GND. The input end of the buffer B1 is connected to the first end of the second load unit to receive the conversion voltage VHa, and the output end of the buffer B1 is used to output a bias voltage VH and a drive current Ic.

[0121] Specifically, the current generation unit may include a current mirror, and the current mirror is connected to the second end of the transistor Mp7 and the second end of the transistor Mn9. The current mirror is used to mirror the current difference between the first current Ib1 and the second current Ib2 to generate a third current.

[0122] In one embodiment, the current mirror may include a transistor Mn21, a transistor Mn22, a transistor Mp21, and a transistor Mp22.

[0123] Among them, the control end of the transistor Mn21, the second end of the transistor Mn21, and the control end of the transistor Mn22 are connected to the second end of the transistor Mp7 and the second end of the transistor Mn9. The first end of the transistor Mn21 and the first end of the transistor Mn22 are connected to the ground voltage GND. The second end of the transistor Mn22 is connected to the control end of the transistor Mp21, the second end of the transistor Mp21, and the control end of the transistor Mp22. The first end of the transistor Mp21 and the first end of the transistor Mp22 are connected to the power supply voltage. The second end of the transistor Mp22 is connected to the first end of the second load unit to generate a third current I3.

[0124] In one embodiment, the second load unit may include a transistor Mn23. The second end of the transistor Mn23 and the control end of the transistor Mn23 are connected to the second end of the transistor Mp22 in the current mirror to generate a conversion voltage VHa, and the first end of the transistor Mn21 is connected to the ground voltage GND.

[0125] In other embodiments, the second load unit may include one or more resistors or other devices connected between the second end of the transistor Mp22 and the ground voltage, and multiple such devices may be connected in series, parallel, or other connection manners.

[0126] In other embodiments, the buffer B1 may not be provided, and the first end of the second load unit is connected to the current generation unit to directly generate a bias voltage VH and a drive current Ic based on the third current I3.

[0127] In this embodiment, the power supply terminals of the first inverter and the second inverter may be connected to the output terminal of the buffer B1 to obtain the bias voltage VH as the operating voltage and the drive current Ic as the operating current.

[0128] In this embodiment, the third current I3 is obtained by mirroring the difference current between the first current Ib1 and the second current Ib2, and then the third current I3 is converted by the second load unit to obtain the conversion voltage VH, so that the conversion voltage VH also has the characteristics of stability and easy control.

[0129] Then, the conversion voltage VH is buffered by the buffer B1, so that the output bias voltage VH and drive current Ic inherit the above characteristics. Thereby, the output frequency of the oscillation module 20 can be made more stable, and it is also beneficial to control the oscillation module 20 to generate a low-frequency oscillation signal.

[0130] Embodiment Three

[0131] As Figure 11 shown, the ring oscillator in this embodiment is only different from that in Embodiment One in the signal processing module 40, and the structures and working principles of other modules are the same as those in Embodiment One. Only the signal processing module 40 will be described below, and other aspects will not be elaborated too much.

[0132] In this embodiment, the signal processing module 40 of the ring oscillator includes a first inverting unit for inverting the initial enable signal OSC_EN to generate a control signal OSC_CON. Specifically, the first inverting unit may include one or more serially connected inverters, and the number of inverters is an odd number.

[0133] Different from Embodiment One, the signal processing module 40 in this embodiment does not have the function of delaying, but except for this, other control functions are the same as those in Embodiment One.

[0134] Embodiment 4

[0135] As Figure 12 shown, the ring oscillator in this embodiment is only different from that in Embodiment 1 in the oscillation module 20, and the structures and working principles of other modules are the same as those in Embodiment 1. Only the oscillation module 20 will be described below, and other aspects will not be elaborated too much.

[0136] In this embodiment, the oscillation module 20 includes a plurality of first inverters and a loop control unit. The loop control unit includes a plurality of loop control sub-units. Each loop control sub-unit and each first inverter form a plurality of oscillation loops. The loop control unit controls each loop control sub-unit based on an adjustment signal to select one of the oscillation loops to generate an oscillation signal.

[0137] Among them, a plurality of first inverters are connected in series to form a group of inverter groups. The output ends of each inverter group are connected together to form the input end of the oscillation module 20 and are connected to the second input end of the OR gate. The input ends of each inverter group are connected together to form the output end of the oscillation module 20 and are connected to the output end of the OR gate.

[0138] In one embodiment, the first inverters are divided into N groups. The i-th group of first inverters is denoted as the first inverter Nai, where 1 ≤ i ≤ N. Each group of first inverters is connected in series with each other to form a group of inverter groups. The number of first inverters in each group is an even number.

[0139] In one embodiment, the loop control sub-unit includes a second inverter. Each second inverter and at least two first inverters form an oscillation loop.

[0140] Specifically, there are N second inverters, which are respectively the second inverter Nc1 to the second inverter NcN. The second inverter Nci is connected to the i-th group of inverter groups and forms an oscillation loop with this i-th group of inverter groups. At this time, each oscillation loop includes at least two first inverters and one second inverter, and the total number of first inverters and second inverters is an odd number.

[0141] In other embodiments, other numbers of first inverters and second inverters can also be set, and the numbers of first inverters and second inverters in each inverter group can also be changed, as long as it is ensured that the total number of first inverters and second inverters in each oscillation loop is an odd number.

[0142] The adjustment signal can be used as the enable signal of the second inverter. Each second inverter can be turned on or off based on the adjustment signal, and the second inverters located in the same oscillation loop receive the same adjustment signal. When the second inverter is turned on, the oscillation loop formed by this second inverter is conducted and starts to oscillate. When the second inverter is turned off, the oscillation loop formed by this second inverter is disconnected and does not oscillate.

[0143] The decoder 50 in this embodiment may be the same as the decoder 50 in the first embodiment, and the generated adjustment signal may be transmitted to the second inverter in the corresponding oscillation loop.

[0144] In this embodiment, the logic unit 60 may not be provided, and the selection of the oscillation loop can be achieved only by gating the second inverter.

[0145] In other specific embodiments, the second inverter in the loop control sub-unit may also be replaced by a switch or other device. Specifically, the switch or other device may be connected to the inverter group and form an oscillation loop with this group of inverters. The switch or other device may control its own on-off based on the adjustment signal to control the oscillation loop to oscillate. At this time, the number of first inverters in each oscillation loop is odd.

[0146] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0147] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A ring oscillator, characterized in that, Comprising: A bias module and an oscillation module; The bias module includes a current unit and a conversion unit connected to each other. The current unit is configured to generate a first current and a second current based on a reference current. The conversion unit is configured to generate a bias voltage based on the second current or generate a bias voltage based on a current difference between the first current and the second current, and generate a drive current based on the current difference between the first current and the second current. The oscillation module is connected to the bias module to receive the bias voltage and the drive current, and generate an oscillation signal based on the bias voltage and the drive current; Wherein, the conversion unit includes a current generation unit and a second load unit. The current generation unit is connected to the current unit to generate a third current based on the current difference between the first current and the second current. The first end of the second load unit is connected to the current generation unit to generate a bias voltage and a drive current based on the third current. The second end of the second load unit is connected to a ground voltage; Or The conversion unit includes a current generation unit, a second load unit and a buffer. The current generation unit is connected to the current unit to generate a third current based on the current difference between the first current and the second current. The first end of the second load unit is connected to the current generation unit to generate a conversion voltage based on the third current. The second end of the second load unit is connected to a ground voltage. The input end of the buffer is connected to the first end of the second load unit to receive the conversion voltage. The output end of the buffer is configured to output a bias voltage and a drive current.

2. The ring oscillator according to claim 1, wherein The conversion unit includes a first load unit. Both ends of the first load unit are connected to the current unit. The current unit is configured to inject a first current into the first load unit and extract a second current from the first load unit to generate a bias voltage and a drive current at one end of the first load unit.

3. The ring oscillator according to claim 1, characterized in that The ring oscillator further includes a control module connected to the oscillation module and a signal processing module connected to the control module. The signal processing module is configured to perform signal processing on an enable signal to generate a control signal. The control module is configured to control the working state of the oscillation module based on the control signal.

4. The ring oscillator according to claim 3, wherein The control module includes an OR gate. The first input end of the OR gate is connected to the signal processing module to receive the control signal. The second input end of the OR gate is connected to the input end of the oscillation module. The output end of the OR gate is connected to the output end of the oscillation module.

5. The ring oscillator according to claim 3, characterized in that, The signal processing module includes a capacitor and a delay inverter. The first end of the capacitor is connected to the input end of the delay inverter and is configured to receive a first enable signal. The output end of the delay inverter is configured to generate a control signal; or The signal processing module includes a capacitor, a delay inverter and a first switching transistor. The first end of the capacitor is connected to the input end of the delay inverter and is configured to receive a first enable signal. The output end of the delay inverter is configured to generate a control signal. The first end and the second end of the first switching transistor are respectively connected to both ends of the capacitor. The control end of the first switching transistor is configured to receive a second enable signal; The signal processing module includes a capacitor, a delay inverter, and a second switching transistor. A first end of the capacitor is connected to an input end of the delay inverter and is used for receiving a first enable signal. An output end of the delay inverter is used for generating a control signal. A first end of the second switching transistor is connected to a reference voltage. A second end of the second switching transistor is connected to the input end of the delay inverter. A control end of the second switching transistor is connected to the output end of the delay inverter; or The signal processing module includes a capacitor, a delay inverter, a first switching transistor, and a second switching transistor. A first end of the capacitor is connected to an input end of the delay inverter and is used for receiving a first enable signal. An output end of the delay inverter is used for generating a control signal. A first end and a second end of the first switching transistor are respectively connected to two ends of the capacitor. A control end of the first switching transistor is used for receiving a second enable signal. A first end of the second switching transistor is connected to a reference voltage. A second end of the second switching transistor is connected to the input end of the delay inverter. A control end of the second switching transistor is connected to the output end of the delay inverter; or The signal processing module includes a first inverting unit configured to invert an initial enable signal to generate a control signal.

6. The ring oscillator according to claim 3, wherein The ring oscillator further includes a first level converter and a second inverting unit. The second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal. The first level converter is connected to the second inverting unit to receive the first inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the first inverted signal; or The ring oscillator further includes a first level converter, a second inverting unit, and a Schmitt trigger. The second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal. The first level converter is connected to the second inverting unit to receive the first inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the first inverted signal. An input end of the Schmitt trigger is connected to the first level converter to receive the output signal. An output end of the Schmitt trigger is used for generating a clock signal; or The ring oscillator further includes a first level converter, a second level converter, and a second inverting unit. The second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal. The second level converter is connected to the second inverting unit to convert the first inverted signal into a second inverted signal. The first level converter is connected to the second level converter to receive the second inverted signal. The first level converter is connected to the oscillation module to convert an oscillation signal into an output signal based on the control of the second inverted signal; or The ring oscillator further includes a first level converter, a second level converter, a second inverter unit, and a Schmitt trigger. The second inverter unit is connected to the signal processing module to invert the control signal to generate a first inverted signal. The second level converter is connected to the second inverter unit to convert the first inverted signal into a second inverted signal. The first level converter is connected to the second level converter to receive the second inverted signal. The first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the second inverted signal. The input terminal of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output terminal of the Schmitt trigger is used to generate a clock signal.

7. The ring oscillator according to claim 1, characterized in that The oscillation module includes a plurality of first inverters and a loop control unit. The loop control unit includes a plurality of loop control sub-units. Each of the loop control sub-units and each first inverter form a plurality of oscillation loops. The loop control unit controls each loop control sub-unit based on an adjustment signal to select one of the oscillation loops to generate an oscillation signal.

8. The ring oscillator according to claim 7, characterized in that, The loop control sub-unit includes a second inverter. Each of the second inverters and at least two first inverters form an oscillation loop.

9. The ring oscillator according to claim 8, wherein An even number of the first inverters that form two corresponding branches constitute a group of inverter groups. The inverter groups are connected in sequence to form two branches. Each of the second inverters is respectively connected between the first inverters of each inverter group and forms an oscillation loop with one or more groups of inverter groups.

10. The ring oscillator according to any one of claims 7, 8, and 9, characterized in that The ring oscillator further includes a decoder connected to each loop control sub-unit. The decoder is used to decode the adjustment value to generate an adjustment signal to control each loop control sub-unit to select one of the oscillation loops to generate an oscillation signal. Or The ring oscillator further includes a decoder and a logic unit. The decoder is connected to each loop control sub-unit. The logic unit is connected to the decoder and each first inverter. The decoder is used to decode the adjustment value to generate an adjustment signal to control each loop control sub-unit. The logic unit is used to perform a logical operation on the adjustment signal, or perform logical operations on the adjustment signal and the bias voltage respectively to generate corresponding logical signals to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logical signal.

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