A DAC gain modulation circuit

Abstract

The application discloses a DAC gain modulation circuit, which can realize flexible adjustment of the output gain of a multi-channel DAC, each channel can be adjusted by using an independent resistor or a single resistor. Compared with a conventional DAC circuit using a single resistor, the circuit can independently adjust the output amplitude of the multi-channel DAC, reduces the need of a user for an additional external channel gain adjustment device, and facilitates switching use in various application modes such as interleaving, independence and modulation. Meanwhile, by adjusting the internal resistance ratio, the output current ratio of each channel can be flexibly adjusted, and the circuit has the characteristics of simple structure, low channel error and flexible modulation, and can be applied to the design of high-precision multi-channel current type DACs, DDSs and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a DAC gain modulation circuit. BACKGROUND

[0002] DAC (Digital Analog Converter) is a kind of digital analog signal conversion circuit, which is divided into voltage type and current type according to output, among which the current type is mostly used in high-precision application, and in the field of signal modulation application, usually two-channel, four-channel and other multi-channel products are needed, and strict requirements are put forward for channel gain consistency and flexible adjustment. In order to solve this problem, a band gap reference is usually used in the circuit to do multi-channel current mirroring for the channel, and the mirror current is controlled for independent adjustment, but the channel matching precision is poor, and the current total output range cannot be adjusted independently when the channel is used independently, which has great limitations. SUMMARY

[0003] The purpose of the present application is to provide a DAC gain modulation circuit to solve the problems in the background art.

[0004] In order to solve the above technical problems, the present application provides a DAC gain modulation circuit, which comprises:

[0005] The first operational amplifier, the second operational amplifier, the third operational amplifier, the first PMOS tube 11, the second PMOS tube 12, the third PMOS tube 13, the fourth PMOS tube 14, the fifth PMOS tube 21, the sixth PMOS tube 22, the seventh PMOS tube 23, the eighth PMOS tube 24, the ninth PMOS tube 30, the tenth PMOS tube 31, the first NMOS tube 34, the second NMOS tube 36, the third NMOS tube 37, the first resistor 15, the second resistor 25, the third resistor 32, and the fourth resistor 35.

[0006] The positive input end of the first operational amplifier is connected with a reference voltage Vref, the negative input end is connected with the first end of the first resistor, and the output end outputs a bias voltage bias1 to the gate end of the first PMOS tube, the gate end of the second PMOS tube and the gate end of the ninth PMOS tube.

[0007] The positive input end of the second operational amplifier is connected with a reference signal Vref, the negative input end is connected with the first end of the second resistor, and the output end outputs a bias voltage bias3 to the gate end of the fifth PMOS tube and the gate end of the sixth PMOS tube.

[0008] The positive input end of the third operational amplifier is connected with a reference voltage Vref, the negative input end is connected with the first end of the third resistor, and the output end is connected with the gate end of the first NMOS tube and the gate end of the second NMOS tube at the same time; Vref is a reference voltage provided by a reference circuit.

[0009] The source end of the first PMOS is connected with VDD, and the drain end is connected with the source end of the third PMOS; the source end of the second PMOS is connected with VDD, and the drain end is connected with the source end of the fourth PMOS; the drain end of the third PMOS is connected with the first end of the first resistance, and the drain end of the fourth PMOS outputs a reference current Iref1; the gate end of the third PMOS and the gate end of the fourth PMOS are both connected with a bias voltage bias2, and the second end of the first resistance is connected with GND.

[0010] The source end of the fifth PMOS is connected with VDD, and the drain end is connected with the source end of the seventh PMOS; the source end of the sixth PMOS is connected with VDD, and the drain end is connected with the source end of the eighth PMOS; the drain end of the seventh PMOS is connected with the first end of the second resistance, and the drain end of the eighth PMOS outputs a reference current Iref2; the gate end of the seventh PMOS and the gate end of the eighth PMOS are connected with a bias voltage bias2, and the second end of the second resistance is connected with GND; bias2 is a bias voltage provided by a reference circuit.

[0011] The source end of the ninth PMOS is connected with VDD, and the drain end is connected with the source end of the tenth PMOS, and the drain end of the tenth PMOS is connected with the first end of the third resistance; the source end of the first NMOS is connected with GND, and the drain end is connected with the second end of the third resistance; the source end of the second NMOS is connected with GND, and the drain end is connected with the second end of the fourth resistance, and the first end of the fourth resistance is connected with the drain end of the seventh PMOS.

[0012] The source end of the third NMOS is connected with GND, the drain end is connected with the output end of the third operational amplifier, and the gate end is connected with a signal sel.

[0013] In an embodiment, the first resistance and the second resistance are modulation resistances externally connected to a device, the first operational amplifier and the second operational amplifier are respectively used for converting reference voltages of the first channel and the second channel into reference currents, when the gains of the channels are independently modulated, the function selection signal sel is 1, at this time, the third NMOS is turned on, the second NMOS is turned off, there is no current path on the fourth resistance, and the gains of the channels are independently modulated according to the externally connected resistances, Iref1 of the first channel = Vref / R15, and Iref2 of the second channel = Vref / R25; R15 is the resistance value of the first resistance, and R25 is the resistance value of the second resistance.

[0014] In an embodiment, when the function selection signal sel is 0, the external port B selects the second resistance, the gain modulation circuit works, the third operational amplifier embeds the voltage of the node C and the external port B to the voltage Vref, the currents on the second PMOS, the fourth PMOS and the sixth PMOS, the eighth PMOS are the same, at this time, Iref1 = Iref2 = Vref / R15, the gains of the first channel and the second channel are adjusted by the first resistance; wherein the external port B is the common connection end of the negative input end of the second operational amplifier, the drain end of the seventh PMOS and the first end of the fourth resistance, the node C is the common connection point of the drain end of the tenth PMOS, the negative input end of the third operational amplifier and the first end of the third resistance.

[0015] In an embodiment, when the single resistance is adjusted, the first NMOS and the second NMOS adjust the proportional range in the range of the saturation region of the transistor, at this time, the resistance value R32 of the third resistance and the resistance value R35 of the fourth resistance need to be changed at the same time, so that the ratio of Iref1 and Iref2 is equal to R32 / R35.

[0016] In an embodiment, the sizes of the first PMOS, the second PMOS, the ninth PMOS, the fifth sixth PMOS and the sixth PMOS need to be consistent, the sizes of the third PMOS, the fourth PMOS, the tenth PMOS, the seventh PMOS and the eighth PMOS need to be consistent, and the sizes of the third resistance and the fourth resistance need to be consistent.

[0017] The DAC gain modulation circuit provided by the application can select the independent external resistance to adjust the gain of each channel or select the single resistance to adjust the gain of all channels through the switch control, and can also realize the rapid adjustment of the total current ratio of different channels by numerically controlling or adjusting the internal resistance ratio, has the characteristics of simple structure, convenient use and adjustment precision, can be flexibly switched between the interlaced or independent channel mode, and can be applied to the design of high-precision multi-channel current type DAC, DDS and other devices. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is the functional principle diagram of the DAC device;

[0019] Figure 2 is the schematic diagram of the DAC gain modulation circuit. DETAILED DESCRIPTION

[0020] The DAC gain modulation circuit provided by the present application is described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of describing the embodiments of the present application.

[0021] Figure 1 Fig. 1 is a functional schematic diagram of a DAC device used in the specific implementation of the present application. The device is a typical current steering digital-to-analog converter, which includes an interface circuit, frequency multiplication and clock distribution, a data buffer stage, a decoding circuit, a reference circuit and a current source array, etc. The digital signal data_in is input by the interface circuit, and is changed into a switching signal by the data buffer stage and the decoding circuit, which is used to control the opening and closing of the current source array, so as to output a corresponding analog current signal. The current source reference current is generated by the reference circuit and the gain control circuit, and is adjusted according to the required current value. The current adjustment resistor can be integrated internally or externally.

[0022] Figure 2 Fig. 2 is a schematic diagram of the DAC gain modulation circuit provided by the present application. The DAC gain modulation circuit includes an operational amplifier 10, an operational amplifier 20, an operational amplifier 33, a PMOS transistor 11, a PMOS transistor 12, a PMOS transistor 13, a PMOS transistor 14, a PMOS transistor 21, a PMOS transistor 22, a PMOS transistor 23, a PMOS transistor 24, a PMOS transistor 30, a PMOS transistor 31, an NMOS transistor 34, an NMOS transistor 36, an NMOS transistor 37, a resistor 15, a resistor 25, a resistor 32, and a resistor 35.

[0023] The positive input terminal of the operational amplifier 10 is connected with a reference voltage Vref, the negative input terminal is connected with the first terminal of the resistor 15, and the output terminal outputs a bias voltage bias1 to the gate terminal of the PMOS transistor 11, the gate terminal of the PMOS transistor 12 and the gate terminal of the PMOS transistor 30. The positive input terminal of the operational amplifier 20 is connected with a reference signal Vref, the negative input terminal is connected with the first terminal of the resistor 25, and the output terminal outputs a bias voltage bias3 to the gate terminal of the PMOS transistor 21 and the gate terminal of the PMOS transistor 22. The positive input terminal of the operational amplifier 33 is connected with a reference voltage Vref, the negative input terminal is connected with the first terminal of the resistor 32, and the output terminal is connected with the gate terminal of the NMOS transistor 34 and the gate terminal of the NMOS transistor 36.

[0024] The source terminal of the PMOS transistor 11 is connected with VDD, and the drain terminal is connected with the source terminal of the PMOS transistor 13. The source terminal of the PMOS transistor 12 is connected with VDD, and the drain terminal is connected with the source terminal of the PMOS transistor 14. The drain terminal of the PMOS transistor 13 is connected with the first terminal of the resistor 15, the drain terminal of the PMOS transistor 14 outputs a reference current Iref1, the gate terminal of the PMOS transistor 13 and the gate terminal of the PMOS transistor 14 are both connected with a bias voltage bias2, and the second terminal of the resistor 15 is connected with GND.

[0025] The source terminal of the PMOS transistor 21 is connected to VDD, and the drain terminal is connected to the source terminal of the PMOS transistor 23; the source terminal of the PMOS transistor 22 is connected to VDD, and the drain terminal is connected to the source terminal of the PMOS transistor 24; the drain terminal of the PMOS transistor 23 is connected to the first terminal of the resistor 25, and the drain terminal of the PMOS transistor 24 outputs a reference current Iref2; the gate terminal of the PMOS transistor 23 and the gate terminal of the PMOS transistor 24 are connected to a bias voltage bias2, and the second terminal of the resistor 25 is connected to GND.

[0026] The source terminal of the PMOS transistor 30 is connected to VDD, and the drain terminal is connected to the source terminal of the PMOS transistor 31; the drain terminal of the PMOS transistor 31 is connected to the first terminal of the resistor 32; the source terminal of the NMOS transistor 34 is connected to GND, and the drain terminal is connected to the second terminal of the resistor 32; the source terminal of the NMOS transistor 36 is connected to GND, and the drain terminal is connected to the second terminal of the resistor 35; the first terminal of the resistor 35 is connected to the drain terminal of the PMOS transistor 23.

[0027] The source terminal of the NMOS transistor 37 is connected to GND, the drain terminal is connected to the output terminal of the operational amplifier 33, and the gate terminal is connected to a signal sel; Vref is a reference voltage provided by a reference circuit; bias2 is a bias voltage provided by the reference circuit; Iref1 is a reference current provided by a DAC channel 1; and Iref2 is a reference current provided by a DAC channel 2.

[0028] The resistors 15 and 25 are modulation resistors connected externally to the device; the resistor 15 has a resistance R15, and the resistor 25 has a resistance R25; the operational amplifier 10 and the operational amplifier 20 are respectively used for converting a reference voltage to a reference current for a channel 1 and a channel 2; when the gain of each channel is independently modulated, the function selection signal sel is 1, at this time, the NMOS transistor 37 is turned on, the NMOS transistor 36 is turned off, and there is no current path on the resistor 35; the gain of each channel is independently modulated according to the externally connected resistor; Iref1 of the channel 1 = Vref / R15, and Iref2 of the channel 2 = Vref / R25.

[0029] When the function selection signal sel is 0, the external port B selects a resistor 25 which is not connected, and the gain modulation circuit works; the operational amplifier 33 embeds the voltage of the node C and the external port B to the voltage Vref; the currents on the common-source common-gate circuits PMOS transistor 12, PMOS transistor 14 and PMOS transistor 22, PMOS transistor 24 are the same; at this time, Iref1 = Iref2 = Vref / R15; the gain of the channel 1 and the channel 2 is adjusted through the resistor 15.

[0030] It needs to be specially noted that, in order to ensure the matching degree, the sizes of the PMOS tube 11, the PMOS tube 12, the PMOS tube 30, the PMOS tube 21 and the PMOS tube 22 need to be consistent, the sizes of the PMOS tube 13, the PMOS tube 14, the PMOS tube 31, the PMOS tube 23 and the PMOS tube 24 need to be consistent, and the sizes of the resistor 32 and the resistor 35 need to be consistent. When the single resistance is adjusted, the NMOS tube 34 and the NMOS tube 36 can be adjusted in the proportional range in the saturation region of the transistor, at this time, the resistance value R32 of the resistor 32 and the resistance value R35 of the resistor 35 need to be changed at the same time, so that the ratio of Iref1 and Iref2 is equal to R32 / R35.

[0031] The DAC gain modulation circuit provided by the application can select independent external resistance to adjust the gain of each channel or use single resistance to adjust the gain of all channels, and has the functions of current proportion adjustment, simple structure, convenient use, high adjustment precision and the like, and can be applied to the design of multi-channel current type DAC and similar devices.

[0032] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application. Any modification and change made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A DAC gain modulation circuit, characterized by, Comprise: The first operational amplifier, the second operational amplifier, the third operational amplifier, the first PMOS tube 11, the second PMOS tube 12, the third PMOS tube 13, the fourth PMOS tube 14, the fifth PMOS tube 21, the sixth PMOS tube 22, the seventh PMOS tube 23, the eighth PMOS tube 24, the ninth PMOS tube 30, the tenth PMOS tube 31, the first NMOS tube 34, the second NMOS tube 36, the third NMOS tube 37, the first resistance 15, the second resistance 25, the third resistance 32, the fourth resistance 35; The positive input end of the first operational amplifier is connected with reference voltage Vref, the negative input end is connected with the first end of the first resistance, and the output end outputs bias voltage bias1 to the gate end of the first PMOS tube, the gate end of the second PMOS tube and the gate end of the ninth PMOS tube; The positive input end of the second operational amplifier is connected with reference signal Vref, the negative input end is connected with the first end of the second resistance, and the output end outputs bias voltage bias3 to the gate end of the fifth PMOS tube and the gate end of the sixth PMOS tube; The positive input end of the third operational amplifier is connected with reference voltage Vref, the negative input end is connected with the first end of the third resistance, and the output end is connected with the gate end of the first NMOS tube and the gate end of the second NMOS tube simultaneously; Vref is the reference voltage provided by the reference circuit; The source end of the first PMOS tube is connected with VDD, the drain end is connected with the source end of the third PMOS tube; The source end of the second PMOS tube is connected with VDD, the drain end is connected with the source end of the fourth PMOS tube; The drain end of the third PMOS tube is connected with the first end of the first resistance, the drain end of the fourth PMOS tube outputs reference current Iref1, the gate end of the third PMOS tube and the gate end of the fourth PMOS tube are connected with bias voltage bias2, and the second end of the first resistance is connected with GND; The source end of the fifth PMOS tube is connected with VDD, the drain end is connected with the source end of the seventh PMOS tube; The source end of the sixth PMOS tube is connected with VDD, the drain end is connected with the source end of the eighth PMOS tube; The drain end of the seventh PMOS tube is connected with the first end of the second resistance, the drain end of the eighth PMOS tube outputs reference current Iref2, the gate end of the seventh PMOS tube and the gate end of the eighth PMOS tube are connected with bias voltage bias2, and the second end of the second resistance is connected with GND; bias2 is the bias voltage provided by the reference circuit; The source end of the ninth PMOS tube is connected with VDD, the drain end is connected with the source end of the tenth PMOS tube, and the drain end of the tenth PMOS tube is connected with the first end of the third resistance; The source end of the first NMOS tube is connected with GND, and the drain end is connected with the second end of the third resistance; The source end of the second NMOS tube is connected with GND, the drain end is connected with the second end of the fourth resistance, and the first end of the fourth resistance is connected with the drain end of the seventh PMOS tube; The source end of the third NMOS tube is connected with GND, the drain end is connected with the output end of the third operational amplifier, and the gate end is connected with signal sel.

2. The DAC gain modulation circuit of claim 1, wherein, The first resistance and the second resistance are external modulation resistances of the device, the first operational amplifier and the second operational amplifier are respectively used for converting the reference voltage to the reference current of the first channel and the second channel, when the gain of each channel is independently modulated, the function selection signal sel is 1, at this time, the third NMOS tube is opened, the second NMOS tube is turned off, there is no current path on the fourth resistance, the gain of each channel is independently modulated according to the external resistance, Iref1 of the first channel = Vref / R15, Iref2 of the second channel = Vref / R25; R15 is the resistance value of the first resistance, and R25 is the resistance value of the second resistance.

3. The DAC gain modulation circuit of claim 2, wherein, When the function selection signal sel is 0, the external port B selects to be not connected to the second resistance, the gain modulation circuit works, the third operational amplifier embeds the voltage of the node C and the external port B to the voltage Vref, the currents on the second PMOS tube, the fourth PMOS tube and the sixth PMOS tube and the eighth PMOS tube are the same, at this time, Iref1 = Iref2 = Vref / R15, the gains of the first channel and the second channel are adjusted through the first resistance; wherein the external port B is a common connection end of the negative input end of the second operational amplifier, the drain end of the seventh PMOS tube and the first end of the fourth resistance, the node C is a common connection point of the drain end of the tenth PMOS tube, the negative input end of the third operational amplifier and the first end of the third resistance.

4. The DAC gain modulation circuit of claim 3, wherein, When a single resistance is adjusted, the first NMOS tube and the second NMOS tube adjust the proportional range in the saturation region of the transistor, at this time, the resistance value R32 of the third resistance and the resistance value R35 of the fourth resistance need to be changed at the same time, so that the ratio of Iref1 and Iref2 is equal to R32 / R35.

5. The DAC gain modulation circuit of claim 1, wherein, The sizes of the first PMOS tube, the second PMOS tube, the ninth PMOS tube, the fifth sixth PMOS tube and the sixth PMOS tube need to be consistent, the sizes of the third PMOS tube, the fourth PMOS tube, the tenth PMOS tube, the seventh PMOS tube and the eighth PMOS tube need to be consistent, and the sizes of the third resistance and the fourth resistance need to be consistent.

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