LDPC Code Encoding Circuit for Improving Coding Efficiency Based on 5G Communication System

Abstract

The present invention relates to the field of LDPC code encoding technology, specifically, to an LDPC code encoding circuit for improving coding efficiency based on a 5G communication system, comprising: a processing unit for obtaining a check matrix of a cyclic LDPC code, obtaining a generator matrix based on the check matrix, and splitting the generator matrix; a computing unit for receiving information input requiring verification calculation to generate currents of different magnitudes and aggregating the currents of each column unit; a comparing unit for comparing the aggregating current with a reference current to generate a 0 / 1 output; and an accumulating unit for performing exclusive-or accumulation on the calculation results of a parallel computing array. In the present invention, a memristor array can be dynamically adjusted according to demand, has higher computing performance and area advantages, improves computing efficiency through concurrent computing, and adopts a grouping method to avoid interference from latent channel currents in a large computing array.

Description

Technical Field

[0001] The present invention relates to the field of LDPC code encoding technology, and in particular to an LDPC code encoding circuit for improving coding efficiency based on a 5G communication system. Background Art

[0002] LDPC codes, as efficient error-correcting codes, have a wide range of uses and remarkable characteristics. In the field of communications, LDPC codes are widely used in wireless communication standards such as 5G, Wi-Fi, and satellite communications. Due to their performance close to the Shannon limit, they can significantly improve the reliability of data transmission. In addition, LDPC codes also play an important role in fiber-optic communications and digital video broadcasting, enhancing the anti-interference capability of communication systems by improving signal transmission quality. In storage systems, LDPC codes reduce data transmission errors by improving the reliability and density of data storage, thereby optimizing the performance of storage devices. Its characteristics include a sparse parity check matrix, which makes LDPC codes easy to implement in hardware and has low computational complexity.

[0003] In traditional circuits, for the calculation of sparse check matrices, the hardware implementation of LDPC coding circuits needs to consider how to efficiently implement encoding and decoding algorithms. However, as the code length of LDPC coding continues to increase, the cost of hardware resources is also increasing. Summary of the Invention

[0004] The purpose of the present invention is to provide an LDPC code encoding circuit based on a 5G communication system to improve coding efficiency, so as to solve the problems raised in the above background technology.

[0005] To solve the above technical problems, the present invention aims to provide an LDPC code encoding circuit for improving coding efficiency based on a 5G communication system, comprising:

[0006] Processing unit: used to obtain the check matrix of the cyclic LDPC code, then obtain the generator matrix based on the check matrix, and split the generator matrix;

[0007] Calculation unit: used to receive information input that needs to be verified and calculated, generate currents of different sizes, and aggregate the currents of each column unit;

[0008] Comparison unit: used to compare the collected current with the reference current and generate 0 / 1 output;

[0009] Accumulation unit: used to perform XOR accumulation on the calculation results of the parallel calculation array.

[0010] As a further improvement of the present technical solution, the processing unit obtains the check matrix H according to the check basis matrix S and the identity matrix I0.

[0011] As a further improvement of this technical solution, the specific steps for the processing unit to obtain the generator matrix according to the parity-check matrix are as follows:

[0012] Divide the codeword and the parity-check matrix into two parts, c 1×n =c=[s 1×k |p 1×m =[s|p], c 1×n and c both represent n-bit codewords, s 1×k and s both represent k-bit information bits, p 1×m and p both represent m-bit parity bits, H m×n and H both represent the m×n parity-check matrix, and H s both represent the systematic part in the parity-check matrix, and H p both represent the parity-check part in the parity-check matrix, and there is:

[0013]

[0014] H s s T +H p p T =0 m×1

[0015] All of the above are calculated in modulo 2 arithmetic, then:

[0016] H s s T =H p p T

[0017]

[0018] Divide the generator matrix into two parts, G k×n =G=[I k×k |P k×(n-k) =[I|P], G k×n and G both represent the k×n generator matrix, I k×k and I both represent the k×k identity matrix, P k×(n-k) and P both represent the k×(n - k) cyclic permutation matrix,

[0019] c = sG = s[I|P] = [s|sP] = [s|p]

[0020]

[0021] where T represents transpose, is the transpose matrix of c 1×n sT is the transpose matrix of s, p T is the transpose matrix of p, 0 m×1 is a zero matrix of m rows and 1 column, is the inverse matrix of H p ;

[0022]

[0023] wherein, I0 is an identity matrix of b×b, 0 is a zero matrix of b×b, G i,j is a cyclic submatrix, 1≤i≤k, 1≤j≤n - k, i and j represent the positions of the cyclic submatrix in the cyclic permutation matrix, ∣ only represents division for easy distinction and does not need to be written during actual input and calculation.

[0024] As a further improvement of this technical solution, the information that needs to be verified and calculated in the calculation unit is used as the input, and the input information bit data is converted into column information. The 1 and 0 in the input information bit data respectively correspond to high level and low level.

[0025] As a further improvement of this technical solution, the calculation unit includes a plurality of juxtaposed memristor arrays. The memristor array includes a plurality of memristors distributed in an array. For the memristors in the same row, their first ends are connected to each other. The first end of the memristor is connected to the column information corresponding to the conversion of the information bit data. For the memristors in the same column, their second ends are connected to each other.

[0026] As a further improvement of this technical solution, the memristor arrays correspond one by one to the cyclic submatrices. When the unit data in the cyclic submatrix is 0, the corresponding memristor in the memristor array is written with high resistance. When the unit data in the cyclic submatrix is 1, the corresponding memristor in the memristor array is written with low resistance.

[0027] As a further improvement of this technical solution, the rule for the memristors in the memristor array to generate different magnitudes of current is: when the column information converted from the input information bit data is at high level and the memristor is at low resistance, a larger current is generated on this memristor; otherwise, a smaller current or no current is generated on this memristor.

[0028] As a further improvement of this technical solution, the comparison unit includes a plurality of comparison circuits. The comparison circuit includes an operational amplifier and a sampling resistor. The first end of the sampling resistor accesses the current collected by the memristors in each column. The first end of the sampling resistor is also connected to the non-inverting input terminal of the operational amplifier. The second end of the sampling resistor is grounded. The inverting input terminal of the operational amplifier is connected to a reference voltage. The output terminal of the operational amplifier generates a 0 / 1 output, and the 0 / 1 output generated by the output terminal of the operational amplifier represents the data of the codeword.

[0029] As a further improvement of the technical solution, the accumulation unit performs an exclusive OR operation on the output results of the comparison circuits in each column.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows: In the LDPC code encoding circuit for improving the encoding efficiency based on a 5G communication system, since the memristor is configurable, the memristor array can be dynamically adjusted according to requirements, avoiding the sharp increase in circuit scale caused by flexible configuration in the traditional implementation using CMOS. It has higher computing efficiency and area advantages, improves the computing efficiency through concurrent computing, and also adopts a grouping method to avoid the interference of sneak path current in a large computing array. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is the overall structure diagram of the present invention;

[0032] Figure 2 is the schematic structural diagram of the computing unit and the comparison unit in the present invention;

[0033] Figure 3 is the circuit diagram of the comparison circuit in the present invention;

[0034] Figure 4 is a partial schematic diagram of Embodiment 1 of the present invention;

[0035] Figure 5 is a partial schematic diagram of Embodiment 2 of the present invention;

[0036] The meanings of the various marks in the figure are as follows:

[0037] 10. Processing unit;

[0038] 20. Computing unit; 200. Memristor array;

[0039] 30. Comparison unit; 300. Comparison circuit;

[0040] 40. Accumulation unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0042] Embodiment 1

[0043] As Figures 1 - 4 shown, this embodiment provides an LDPC code encoding circuit for improving the encoding efficiency based on a 5G communication system, including:

[0044] Processing unit 10: used to obtain the parity-check matrix of the cyclic LDPC code, then obtain the generator matrix according to the parity-check matrix, and split the generator matrix;

[0045] Calculation unit 20: used to receive the information input that needs to be verified and calculated to generate currents of different sizes, and converge the column unit currents;

[0046] Comparison unit 30: used to compare the converged current with the reference current to generate a 0 / 1 output;

[0047] Accumulation unit 40: used to perform exclusive-OR accumulation on the calculation results of the parallel calculation array.

[0048] The 5G communication system requires high-rate, low-latency, and highly reliable data transmission. The low-complexity encoding and decoding characteristics of the quasi-cyclic LDPC code enable it to effectively reduce the processing delay while meeting the error correction performance requirements, and adapt to the needs of high-speed data processing in 5G communication. The parity-check matrix H of the quasi-cyclic LDPC code has a quasi-cyclic characteristic. This special structure makes the parity-check matrix H have a certain regularity and sparsity. Sparsity helps reduce the computational complexity in the encoding and decoding processes, while regularity provides convenience for hardware implementation.

[0049] In this embodiment, the processing unit 10 obtains the parity-check matrix H according to the parity-check base matrix S and the identity matrix I0. Assume that the parity-check base matrix S is a two-row and three-column matrix, and the order of the identity matrix I0 is three. There is:

[0050]

[0051] Then:

[0052]

[0053] -1 in the parity-check base matrix S is represented as a third-order all-zero matrix, 0 in the parity-check base matrix S is represented as a third-order all-zero matrix, 1 in the parity-check base matrix S is represented as a matrix obtained by cyclically shifting the third-order identity matrix I0 one bit to the right, and 2 in the parity-check base matrix S is represented as a matrix obtained by cyclically shifting the third-order identity matrix I0 two bits to the right.

[0054] Further, the specific steps for the processing unit 10 to obtain the generator matrix according to the parity-check matrix are:

[0055] Divide the codeword and the parity-check matrix into two parts, c 1×n = c = [s 1×k | p 1×m ] = [s | p], c 1×n and c both represent n-bit codewords, s 1×k and s both represent k-bit information bits, p 1×mBoth and p represent m-bit check bits. H m×n Both and H represent an m×n check matrix. and H s Both represent the systematic part in the check matrix. and H p Both represent the check-bit part in the check matrix, and there is:

[0056]

[0057] H s s T +H p p T =0 m×1

[0058] All of the above are calculated in modulo-2 arithmetic. GF(2) is a binary Galois field that contains only two elements, namely 0 and 1. The addition operation is modulo-2 addition, and the rules are: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 0. The multiplication operation is a conventional multiplication operation. The subtraction operation is similar to the previous addition operation, and the rules are: 1 - 1 = 0, 0 - 0 = 0, 1 - 0 = 1, 0 - 1 = 1. Then:

[0059] H s s T =H p p T

[0060]

[0061] Divide the generator matrix into two parts, G k×n =G=[I k×k |P k×(n-k) =[I|P], G k×n Both and G represent a k×n generator matrix, I k×k Both and I represent a k×k identity matrix, P k×(n-k) Both and P represent a k×(n - k) cyclic permutation matrix;

[0062] Suppose the information to be transmitted is the number 6, then s = [1 1 0],

[0063]

[0064] c = sG = s[I|P] = [s|sP] = [s|p]

[0065]

[0066]

[0067] All of the above operations are performed modulo 2, so -1 in the matrix can be replaced by 1,

[0068]

[0069] where T represents transpose, is the transpose matrix of c 1×n , s T is the transpose matrix of s, p T is the transpose matrix of p, 0 m×1 is a matrix of all zeros with m rows and 1 column, is the inverse matrix of H p ;

[0070]

[0071] where I0 is an identity matrix of b×b, 0 is a matrix of all zeros of b×b, G i,j is a cyclic submatrix, 1≤i≤k, 1≤j≤n - k, i and j represent the positions of the cyclic submatrix in the cyclic permutation matrix, ∣ only represents division for easy distinction and does not need to be written during actual input and calculation;

[0072] Calculate the codeword c and the parity bit p for subsequent verification:

[0073]

[0074] The parity bit p = [0 1 1 1 0 1] and the codeword c = [1 1 0 0 1 1 1 0 1] can be obtained.

[0075] In this embodiment, the calculation unit 20 takes the information that needs to be verified as input, converts the input information bit data into column information. The 1 and 0 in the input information bit data correspond to high and low levels respectively, s = [1 1 0], and it can be converted into

[0076] Furthermore, the calculation unit 20 includes a plurality of parallel memristor arrays 200. The memristor array 200 includes a plurality of memristors distributed in an array. A memristor is a special type of electronic component with memory and variable resistance properties. A memristor can change its resistance value under the action of an applied voltage or current and can maintain this resistance value after power-off, that is, it has non-volatility. For the memristors in the same row, their first ends are connected to each other. The first end of the memristor is connected to the column information converted from the corresponding information bit data, that is, each row of memristors receives the column information converted from the same information bit data. For the memristors in the same column, their second ends are connected to each other, that is, the current generated by each column of memristors can be aggregated.

[0077] Furthermore, the memristor array 200 corresponds to the circulant submatrix one-to-one. When the cell data in the circulant submatrix is 0, the corresponding memristor in the memristor array 200 is written with high resistance. When the cell data in the circulant submatrix is 1, the corresponding memristor in the memristor array is written with low resistance. Then:

[0078]

[0079] The computing unit 20 corresponds to three memristor arrays 200, which correspond to three circulant sub-matrices from front to back. The first circulant sub-matrix is a 3×3 unit matrix, and the following two circulant sub-matrices are obtained by cyclic shift of the first circulant sub-matrix. There is only one 1 in each row or column of the matrix. The current result in this circuit does not need to be multi-bit quantized, but only needs to be binarized.

[0080] Furthermore, the rule for the memristors in the memristor array 200 to generate currents of different magnitudes is as follows: when the column information converted from the input information bit data is at a high level and the memristor is at a low resistance, a large current is generated on the memristor; conversely, a small current or no current is generated on the memristor. By combining the column information and the memristor array 200, we can obtain:

[0081]

[0082] Then we can get the current on the memristor:

[0083]

[0084] In this embodiment, the comparison unit 30 includes a plurality of comparison circuits 300. The comparison circuits 300 include an operational amplifier and a sampling resistor. The first end of the sampling resistor is connected to the current collected by each column of memristors. The first end of the sampling resistor is also connected to the non-inverting input of the operational amplifier. The second end of the sampling resistor is grounded. The inverting input of the operational amplifier is connected to a reference voltage. The current is converted into a voltage through the sampling resistor and then compared with the reference voltage. A 0 / 1 output is then generated at the output of the operational amplifier. The 0 / 1 output generated at the output of the operational amplifier represents the data of the codeword. The three memristor arrays 200 correspond to nine comparison circuits 300. After collecting the current on each column, the following is obtained:

[0085] [Big, small, big, big, big, big]

[0086] The result is c = [1 1 0 0 1 1 1 0 1], which is the same as the result calculated previously. Because the memristor is configurable, the calculation matrix can be dynamically adjusted according to demand, avoiding the sharp increase in circuit scale caused by flexible configuration in traditional CMOS implementations, and has higher computing efficiency and area advantages.

[0087] Example 2

[0088] As shown Figure 5 in the figure, let the check base matrix S be a one-row and three-column matrix, the order of the identity matrix I0 be three, s = [1 1 1 1 1 1], then there is:

[0089] S = [1 1 2]

[0090]

[0091] Then:

[0092]

[0093] All of the above operations are performed in modulo-2 arithmetic, so the 2 in the p matrix can be replaced with 0, and we can get p = [0 0 0];

[0094]

[0095] We can get the check bit p = [0 0 0] and the codeword c = [1 1 1 1 1 1 0 0 0];

[0096] The input information bit data is converted into column information, s = [1 1 1 1 1 1], and it can be converted into The writing relationship of the memristor array 200 is:

[0097]

[0098] The computing unit 20 corresponds to six memristor arrays 200, which respectively correspond to six 3×3 cyclic submatrices in sequence; furthermore, the current situation on the memristors can be obtained:

[0099]

[0100] The results generated by the eighteen comparison circuits 300 corresponding to the six memristor arrays 200 are:

[0101]

[0102] In this embodiment, the accumulator unit 40 performs an exclusive OR operation on the output results of the comparison circuits 300 on each column, improves the computing efficiency through concurrent computing, and at the same time, adopts a grouping method to avoid the interference of the sneak path current in the large computing array, and the final result can be obtained:

[0103] [Big Big Big Big Big Big Small Small Small]

[0104] Thus, c = [1 1 1 1 1 1 0 0 0] is obtained, which is the same as the previously calculated result.

[0105] The foregoing has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only preferred examples of the present invention and are not used to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. An LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system, characterized in that Including: Processing unit (10): configured to obtain a parity-check matrix of a cyclic LDPC code, then obtain a generator matrix according to the parity-check matrix, and split the generator matrix; Calculation unit (20): configured to receive information to be checked and calculated to generate currents of different magnitudes, and converge the unit currents of each column; Comparison unit (30): configured to compare the converged current with a reference current to generate a 0 / 1 output; Accumulation unit (40): configured to perform exclusive-OR accumulation on the calculation results of the parallel calculation array; The processing unit (10) obtains a parity check matrix according to a parity check basis matrix and an identity matrix ; ; The specific steps for the processing unit (10) to obtain the generator matrix according to the parity-check matrix are as follows: Divide the codeword and the parity-check matrix into two parts, , and both represent -bit codewords, and both represent -bit information bits, and both represent -bit parity bits, , and both represent -row -column parity-check matrix, and both represent the systematic-bit part in the parity-check matrix, and both represent the parity-bit part in the parity-check matrix, and there is: ； ； ； All of the above are calculated in modulo-2 arithmetic, then: ； ； Divide the generating matrix into two parts, , and both represent row column generating matrix, and both represent row column identity matrix, and both represent row column cyclic permutation matrix, ； ； ； ； Among them, represents transpose, is the transpose matrix of, is the transpose matrix of, is the transpose matrix of, is a zero matrix with 1 row and 1 column, is the inverse matrix of; ； Among them, is the identity matrix of, is the all-zero matrix of, is a cyclic submatrix, , , and represent the positions of the cyclic submatrices in the cyclic permutation matrix, only represents the division for convenience of distinction and does not need to be written during actual input and calculation.

2. The LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system according to claim 1, characterized in that: In the calculation unit (20), the information to be checked and calculated is used as an input, the input information bit data is converted into column information, and 1 and 0 in the input information bit data correspond to high level and low level respectively.

3. The LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system according to claim 2, wherein: The calculation unit (20) includes a plurality of parallel memristor arrays (200). The memristor arrays (200) include a plurality of memristors distributed in an array. For the memristors in the same row, their first ends are connected to each other. The first end of the memristor is connected to the column information converted from the corresponding information bit data. For the memristors in the same column, their second ends are connected to each other.

4. The LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system according to claim 3, characterized in that: The memristor arrays (200) correspond to cyclic sub-matrices one by one. When the unit data in the cyclic sub-matrix is 0, the corresponding memristors in the memristor arrays (200) are written with high resistance. When the unit data in the cyclic sub-matrix is 1, the corresponding memristors in the memristor arrays are written with low resistance.

5. The LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system according to claim 4, wherein The rule for the memristors in the memristor arrays (200) to generate currents of different magnitudes is: when the column information converted from the input information bit data is high level and the memristor is of low resistance, a larger current is generated on the memristor; otherwise, a smaller current or no current is generated on the memristor.

6. The LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system according to claim 5, characterized in that: The comparison unit (30) includes a plurality of comparison circuits (300). The comparison circuits (300) include operational amplifiers and sampling resistors. The first end of the sampling resistor is connected to the current converged by the memristors of each column. The first end of the sampling resistor is also connected to the non-inverting input terminal of the operational amplifier. The second end of the sampling resistor is grounded. The inverting input terminal of the operational amplifier is connected to a reference voltage. The output terminal of the operational amplifier generates a 0 / 1 output. The 0 / 1 output generated by the output terminal of the operational amplifier represents the data of the codeword.

7. The LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system according to claim 6, characterized in that: The accumulation unit (40) performs an exclusive-OR operation on the output results of the comparison circuits (300) in each column.

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