Data processing device and method based on FC multichannel multiplexing

Abstract

The invention belongs to the technical field of optical fiber communication, and particularly discloses a data processing device and method based on FC multichannel multiplexing. The device comprises a data processing unit, a frame header information multiplexing unit and a data sending unit which are connected in sequence, the data sending unit comprises a plurality of sub-sending units; each sub-sending unit is provided with an IP core; the data processing unit is used for processing a plurality of received data packets into a plurality of first FC data packets with the same length; the frame header information multiplexing unit is used for processing each first FC data packet into a second FC data packet with the same frame header information; and each sub-sending unit is used for calling the respective IP core to perform data framing on the respective received second FC data packet to obtain a corresponding FC data frame, and converting the corresponding FC data frame into high-speed serial data to be sent. According to the invention, the processing flow of FC data can be effectively simplified, and the utilization rate and information transmission efficiency of a high-speed serial channel of the system are improved.

Description

Technical Field

[0001] The present application belongs to the technical field of FC data processing, and more specifically, relates to a data processing device and method based on FC multi-channel multiplexing. Background Art

[0002] With the continuous development of communication technology, Fibre Channel (FC) data transmission technology has become an important pillar in the current communication field, with advantages such as high transmission speed, high reliability, strong adaptability and easy and flexible configuration. On the one hand, FC data transmission technology can ensure the security and stable transmission of data, and on the other hand, it also meets the technical performance requirements of higher bandwidth data transmission. It has been widely used in many fields such as computing systems, telecommunications industry, storage networks, and even military, medical, aerospace, etc. FC data transmission technology is developing in a more efficient and faster direction. With the increase of system functions and the continuous improvement of complexity, the information transmission capability of FC signal processing equipment is also increasingly required. As a bridge for information connection between FC and other data or between FC data, FC signal processing equipment is an important guarantee for the stable and reliable operation of communication networks. How to enhance the information transmission efficiency of FC signal processing equipment, improve the utilization of system resources, and increase the data transmission speed under the limited hardware resources of existing equipment is of great research significance to meet the growing information transmission needs of FC communication.

[0003] However, in the existing FC data transmission technology, due to the complex and cumbersome internal FC data processing process, the processor is often restricted by the limited number of physical ports of its own internal high-speed data channel and the inability to fully utilize the existing ports, which ultimately leads to low utilization of the system's high-speed serial channels and low system information transmission efficiency.

[0004] Therefore, how to better realize FC data transmission has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] In view of the defects of the prior art, the purpose of this application is to better realize the transmission of FC data, aiming to solve the problems of low utilization rate of system high-speed serial channels and low system information transmission efficiency in the existing FC data transmission technology.

[0006] To achieve the above objectives, in a first aspect, the present application provides a data processing device based on FC multi-channel multiplexing, comprising: A data processing unit, a frame header information multiplexing unit and a data sending unit connected in sequence; the data sending unit includes a plurality of sub-sending units; each of the sub-sending units is configured with an IP core; The data processing unit is used for processing the received multiple data packets into multiple first FC data packets of the same length; The frame header information multiplexing unit is used for processing each of the first FC data packets into a second FC data packet with the same frame header information; Each of the sub-transmitting units is used to call its own IP core to perform data framing on the second FC data packets received by it to obtain corresponding FC data frames, and convert the corresponding FC data frames into high-speed serial data for transmission.

[0007] Optionally, the frame header information multiplexing unit includes a framing subunit and an ID identifier configuration subunit; The framing subunit is used to add the same optional header field of the FC protocol and the same frame header field of the FC protocol to the data field of each of the first FC data packets, so as to obtain each of the first FC data packets having the same frame header; The ID identifier configuration subunit is used to configure a corresponding ID identifier for each of the first FC data packets having the same frame header, so as to obtain each of the second FC data packets.

[0008] Optionally, the data processing unit includes a data length processing subunit and an FC timing control subunit; The data length processing subunit is used for processing the multiple data packets into multiple data packets with the same length; The FC timing control subunit is used to generate a plurality of first FC data packets conforming to the FC timing format based on the plurality of data packets with the same length.

[0009] Optionally, the data length processing subunit is specifically used for: Writing the multiple data packets into a data cache; Reading each of the data packets from the data buffer with a target length until the last data packet of each of the data packets is read; If it is determined that the length of the last data packet is equal to the target length, reading the last data packet; If it is determined that the length of the last data packet is less than the target length, the end of the last data packet is padded with zeros until the length of the last data packet after the zero padding is equal to the target length, and the last data packet after the zero padding is read.

[0010] Optionally, each of the sub-transmission units comprises a data transmission management module and a high-speed serial channel connected in sequence; the data transmission management module comprises a frame management sub-unit and a credit detection sub-unit; The frame management subunit is used to add a frame start and a frame end to the corresponding second FC data packet to obtain a corresponding FC data frame, and convert the corresponding FC data frame into high-speed serial data; The credit detection subunit is used to verify the corresponding FC data frame to obtain a FC data frame that passes the verification; The high-speed serial channel is used to send the high-speed serial data corresponding to the FC data frame that has passed the inspection.

[0011] Optionally, the device further comprises a management clock multiplexing unit; The management clock multiplexing unit includes a master clock unit and a plurality of slave clock units; The master clock unit is used to simultaneously control each of the slave clock units to generate a channel clock signal synchronized with itself, and distribute each channel clock signal to the high-speed serial channel in the corresponding IP core; the clock signal of the master clock unit is determined based on an external reference clock; each of the IP cores is placed in the same QUAD.

[0012] In a second aspect, the present application provides a data processing method applied to a data processing device based on FC multi-channel multiplexing as described in any one of the above, comprising: Processing the received multiple data packets into multiple first FC data packets with the same length; Performing frame header information configuration on each of the first FC data packets, so as to process each of the first FC data packets into a second FC data packet with the same frame header information; Perform data framing on each of the second FC data packets to obtain FC data frames corresponding to each of the second FC data packets, and convert each of the FC data frames into high-speed serial data for transmission.

[0013] Optionally, the processing of each of the first FC data packets into a second FC data packet with the same frame header information includes: Adding the same optional header field of the FC protocol and the same frame header field of the FC protocol to the data field of each of the first FC data packets to obtain first FC data packets having the same frame header; A corresponding ID identifier is configured for each of the first FC data packets having the same frame header to obtain each of the second FC data packets.

[0014] Optionally, the processing of the received multiple data packets into multiple first FC data packets of the same length includes: Processing the multiple data packets into multiple data packets of the same length; Based on the multiple data packets with the same length, multiple first FC data packets conforming to the FC timing format are generated.

[0015] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0016] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0017] In a fifth aspect, the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0018] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0019] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art: The present application provides a data processing device and method based on FC multi-channel multiplexing. By optimizing the FC protocol specification, multiple received data packets are processed into multiple FC data packets with the same length, and the frame header information multiplexing unit is used to multiplex the FC data frame header information, and the FC data packets are processed into FC data packets with the same frame header information. Each sub-transmission unit performs data framing on the FC data packets with the same frame header information received by each sub-transmission unit, and the obtained FC data frames are converted into high-speed serial data for transmission. The FC data processing flow can be effectively simplified, and while ensuring the efficient and fast transmission of FC data communication information, the utilization rate of the system's high-speed serial channel is improved, hardware resources are saved, and the information transmission efficiency of the system is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is one of the structural schematic diagrams of a data processing device based on FC multi-channel multiplexing provided in an embodiment of the present application; Figure 2 This is the second structural schematic diagram of the data processing device based on FC multi-channel multiplexing provided in the embodiment of the present application; Figure 3 It is a flowchart of a data length processing method provided in an embodiment of the present application; Figure 4 It is a schematic diagram of FC protocol frame header optimization provided by an embodiment of the present application; Figure 5It is a schematic diagram of the structure of a traditional FC data processing device; Figure 6 is a structural diagram of a device management clock multiplexing system provided in an embodiment of the present application; Figure 7 This is the third structural diagram of the data processing device based on FC multi-channel multiplexing provided in the embodiment of the present application; Figure 8 It is a flow chart of a data processing method based on FC multi-channel multiplexing provided in an embodiment of the present application; Fig. 9 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] The terms "first" and "second" in the specification and claims of this application are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first FC data packet and a second FC data packet are used to distinguish different FC data packets rather than to describe a specific order of the FC data packets.

[0023] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0024] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple sub-sending units refer to two or more sub-sending units, etc.; multiple data packets refer to two or more data packets, etc.

[0025] In the prior art, traditional FC data processing methods generally target hardware terminals such as high-speed serial channels or communication ports, and most research related to FC information transmission and data processing directly adopts existing mature IP core solutions, and there is no research on methods for optimizing processing from within the IP core or even at the FC protocol level.

[0026] To this end, the present application provides a data processing device and method based on FC multi-channel multiplexing.

[0027] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0028] Figure 1 is one of the structural schematic diagrams of the data processing device based on FC multi-channel multiplexing provided in the embodiment of the present application, such as Figure 1 As shown, including: A data processing unit 1, a frame header information multiplexing unit 2 and a data sending unit 3 are connected in sequence; the data sending unit 3 includes a plurality of sub-sending units 31; each sub-sending unit 31 is configured with an IP core; The data processing unit 1 is used for processing the received multiple data packets into multiple first FC data packets of the same length; The frame header information multiplexing unit 2 is used for processing each first FC data packet into a second FC data packet with the same frame header information; Each sub-transmitting unit 31 is used to call its own IP core to perform data framing on its received second FC data packets to obtain corresponding FC data frames, and convert the corresponding FC data frames into high-speed serial data for transmission.

[0029] Specifically, the first FC data packet described in the embodiment of the present application refers to data packets obtained by processing a data stream including multiple data packets and processing the data lengths of the respective data packets therein to be the same length.

[0030] The second FC data packet described in the embodiment of the present application refers to a data packet obtained by processing the frame header information of each first FC data packet into the same information.

[0031] The IP core described in the embodiment of the present application is a module that encapsulates the underlying details of the Fibre Channel and provides a specific interface to the user, which can implement the main functions of the Fibre Channel protocol, including data transmission, reception, and frame parsing. In the embodiment of the present application, it can also be described as an FC IP core.

[0032] It should be noted that, in the embodiments of the present application, an IP core generally includes a clock management module, a data transmission management module and two high-speed serial channel driver modules, wherein the data transmission management module serves as the core module of each sub-transmission unit and is used to perform data framing on the second FC data packets received by each.

[0033] In the embodiment of the present application, the structure of the data processing device is a data processing unit, a frame header information multiplexing unit and a data sending unit from left to right. When the device receives multiple service data packets sent from the outside, the data processing unit first processes the received data packets, and it can use the FC data protocol to process these data packets with different lengths into multiple data packets with the same length, that is, to obtain multiple first FC data packets.

[0034] In an embodiment of the present application, the data processing unit will send multiple first FC data packets to the frame header information multiplexing unit for processing. The frame header information multiplexing unit can optimize the FC data frame header format, configure the frame header information of each first FC data packet, and add the same frame header field to each first FC data packet, thereby processing each first FC data packet into a second FC data packet with the same frame header information.

[0035] Furthermore, in an embodiment of the present application, the frame header information multiplexing unit sends each second FC data packet to the data sending unit, and the data sending unit transmits each second FC data packet to each internal sub-sending unit for processing. After receiving the corresponding second data packet, each sub-sending unit can call its own IP core to perform data framing on the second FC data packet received by itself, obtain the corresponding FC data frame, and convert the corresponding FC data frame into high-speed serial data, and complete data transmission through the internal high-speed serial channel.

[0036] The data processing device based on FC multi-channel multiplexing in the embodiment of the present application optimizes the FC protocol specification, processes multiple received data packets into multiple FC data packets with the same length, multiplexes the FC data frame header information by using the frame header information multiplexing unit, processes these FC data packets into FC data packets with the same frame header information, and frames the FC data packets with the same frame header information received by each sub-transmitting unit, converts the obtained FC data frames into high-speed serial data for transmission, which can effectively simplify the processing flow of FC data, and improve the utilization rate of the system's high-speed serial channel while ensuring the efficient and fast transmission of FC data communication information, saving hardware resources, and thus improving the information transmission efficiency of the system.

[0037] Figure 2 This is a second structural diagram of a data processing device based on FC multi-channel multiplexing provided in an embodiment of the present application, such as Figure 2 As shown, the data processing unit 1 includes a data length processing subunit 11 and an FC timing control subunit 12; The data length processing subunit 11 is used for processing a plurality of data packets into a plurality of data packets of the same length; The FC timing control subunit 12 is used to generate a plurality of first FC data packets conforming to the FC timing format based on a plurality of data packets having the same length.

[0038] Specifically, the FC timing format described in the embodiment of the present application refers to the timing and frame format of data transmission in the Fibre Channel protocol. The timing format of the Fibre Channel mainly involves the transmission timing of data and the transmission process of data frames. In the Fibre Channel network, data is transmitted according to a certain timing, including the start, transmission and end of the frame. These processes are strictly regulated by the Fibre Channel protocol to ensure the correct transmission of data and the stable operation of the network.

[0039] In the embodiment of the present application, the data processing unit is mainly responsible for providing two parts: unified data length processing and FC timing control logic, that is, it includes a data length processing subunit and a FC timing control subunit.

[0040] In an embodiment of the present application, when the data processing unit processes the received multiple task data packets, the data length processing subunit first converts the input data of different lengths into data of the same length, that is, obtains multiple data packets of the same length. Further, the FC timing control subunit can convert the multiple data packet data streams of the same length into multiple first FC data packets that conform to the FC timing format according to the internal FC timing control logic.

[0041] More specifically, when the data stream enters the data processing unit, the data length processing subunit first processes the data into data of the same length DATA, and gives it to the FC timing control logic, and uses the state machine in the logic to generate a data frame that conforms to the FC timing format, that is, to obtain the first FC data packet. Each frame of FC data in the first FC data packet consists of four parallel data streams: a start identifier (Start of Packet, SOP), an enable EN, an end identifier (End of Packet, EOP) and a data field FC_DATA, where FC_DATA is the PAYLOAD data in the FC-AE-ASM protocol, with a data bit width of 16 bits, and a data length that must be an integer multiple of 4 bytes.

[0042] It should be noted that the full name of the FC-AE-ASM protocol is Fiber Channel Avionics Environment Anonymous Subscriber Messaging, which is a part of the FC-AE (Fibre Channel Avionics Environment) protocol series and is specifically designed to implement unsigned anonymous message exchange in a highly reliable Fibre Channel network.

[0043] The device of the embodiment of the present application constructs a data processing unit by using a data length processing subunit and an FC timing control subunit, processes each data packet into data of the same length, and processes the data into data in an FC timing format through FC timing control logic, thereby ensuring the consistency and integrity of the data, meeting the requirements of the Fibre Channel protocol, and optimizing the transmission efficiency of FC data.

[0044] Based on the content of the above embodiment, as an optional embodiment, the data length processing subunit 11 is specifically used for: Writing multiple data packets into the data buffer; Read each data packet from the data buffer with the target length until the last data packet in each data packet is read; If it is determined that the length of the last data packet is equal to the target length, the last data packet is read; If it is determined that the length of the last data packet is less than the target length, the end of the last data packet is padded with zeros until the length of the last data packet after the zero padding is equal to the target length, and the last data packet after the zero padding is read.

[0045] Specifically, the target length described in the embodiment of the present application refers to a preset fixed data length Lconst, and Lconst can usually take the maximum value of the frame payload PAYLOAD. The frame payload PAYLOAD is the main part of the data frame, which is the actual data information part carried in the data frame.

[0046] Figure 3 is a flow chart of a data length processing method provided in an embodiment of the present application, such as Figure 3 As shown, in the embodiment of the present application, the protocol frame format of FC data DATA includes SOF, HEADER, OPT, PAYLOAD, CRC and EOF, wherein SOF is a frame start mark, HEADER is a frame header field; OPT is an optional header field of the FC-AE-ASM protocol; EOF is a frame end mark. When data of different lengths enter the data length processing subunit, the data length needs to be processed uniformly.

[0047] Exemplarily, when a data frame with a total length of Length1 consisting of n data packets DATA1, DATA2, ..., DATAn with lengths L1, L2, ..., Ln respectively arrives, these data are first written into the data cache, and then each data packet is read from the data cache with the target length, that is, each data packet can be read with the same fixed length Lconst to obtain each data packet DATA-1, DATA-2, ..., DATA-m with a data length of Lconst.

[0048] Furthermore, when the last data DATA-m is read, if it is determined that its length is exactly equal to Lconst, it can be read directly; if it is determined that its length is less than Lconst, the insufficient part is padded with 0, that is, the end of the data packet DATA-m is padded with zeros to make its length equal to Lconst before reading it out. Therefore, the total length of each data packet DATA-1, DATA-2, ..., DATA-m after data length processing becomes Length2. Finally, the m data with a length of Lconst are handed over to the frame header information multiplexing unit and the data sending unit for frame header multiplexing, framing and other operations, and the data transmission is completed.

[0049] The device of the embodiment of the present application can simplify the process of data transmission and processing by processing each data packet into data of fixed length, so that the data is more standardized and normalized during the transmission process, which is conducive to improving the transmission efficiency of FC data; at the same time, the fixed-length data packet can better cooperate with the security mechanism of the FC protocol to ensure the confidentiality and integrity of data transmission. Continue to refer to Figure 2 ,like Figure 2 As shown, as an optional embodiment, in the embodiment of the present application, the frame header information multiplexing unit 2 includes a framing subunit 21 and an ID identifier configuration subunit 22; The framing subunit 21 is used to add the same optional header field of the FC protocol and the same frame header field of the FC protocol to the data field of each first FC data packet, so as to obtain each first FC data packet having the same frame header; The ID identifier configuration subunit 22 is used to configure corresponding ID identifiers for each first FC data packet having the same frame header, so as to obtain each second FC data packet.

[0050] Specifically, in an embodiment of the present application, the frame header information multiplexing unit is used to implement multiplexing processing of data frame header information. After the data processing unit completes processing of a frame of data packets, the data packets are sent to the framing subunit in the frame header information multiplexing unit, and the framing subunit adds the same frame header field HEADER and ASM optional header field OPT to the FC_DATA in each data packet, thereby generating FC-AE-ASM data packets with the same frame header, that is, obtaining first FC data packets with the same frame header.

[0051] Furthermore, the ID identifier configuration subunit can be used to dynamically configure the ID identifier of each first FC data packet with the same frame header, thereby obtaining an FC-AE-ASM data packet with a configured ID identifier, that is, obtaining each second FC data packet. Finally, the multiplexed FC-AE-ASM data packet is distributed to the data transmission unit, and the data transmission unit completes further data packaging, processes it into high-speed serial data, and completes transmission through a high-speed serial channel.

[0052] It should be noted that the ID identifier is an important part of the frame header field, including the source address ID, destination address ID, originating exchange ID, receiving exchange ID, etc., which is used to represent the basic information of the FC data frame. This information itself is not used to control the framing, but is added as part of the HEADER during framing to form an FC-AE-ASM data packet.

[0053] Figure 4 Schematic diagram of FC protocol frame header optimization provided by the embodiment of the present application, such as Figure 4 As shown, in the embodiment of the present application, the FC protocol frame format includes SOF, HEADER, OPT, PAYLOAD, CRC and EOF, wherein a frame header multiplexing flag byte is added to the ASM header OPT.

[0054] Among them, the frame header field HEADER contains ID identifiers such as SID and DID and control fields such as R_CTL and CS_CTL. In the specified FC data frame, control words such as R_CTL and CS_CTL have fixed values ​​and remain unchanged, while identifiers such as SID and DID need to be adjusted according to specific circumstances to adapt to possible port data selection requirements.

[0055] Among them, bytes 8 to 11 of the optional header field OPT are security reserved fields, and the 8th byte is defined as the frame header multiplexing flag byte, which is used to mark the current frame header multiplexing status. Specifically, in the optional header OPT, the first 6 bits represent the length uniformity method, which is used to indicate the method or algorithm used to process the data length. The 7th bit indicates whether the data frame is an FC tail frame, that is, the last frame of an FC data segment. 1 represents the tail frame and 0 represents the non-tail frame. The 8th bit indicates whether the frame header multiplexing mode is adopted. 1 represents the frame header multiplexing mode is adopted, and 0 represents the frame header multiplexing mode is not adopted. In addition, the remaining fields are the same as the standard FC-AE-ASM protocol.

[0056] In the embodiment of the present application, when FC data transmission is performed, except for the ID identifier that needs to be configured separately, the frame header fields and optional header contents of all data frames are the same, and only the PAYLOAD payload field and CRC check field are different between each data frame, which are used to transmit data information. The 14th byte of the optional header OPT carries the length (Message Length) information of the data frame, indicating the length of the data processed uniformly.

[0057] In this embodiment, based on the optimization of the protocol specification, a multiplexing status frame is added on the basis of the reserved field of the optional header of the original data field, and the main information of the frame headers of different data frames is basically consistent by uniformly processing the information such as the data length, thereby ensuring the consistency of the status of each FC-2 frame header, which can effectively improve the data transmission efficiency.

[0058] Figure 5 It is a schematic diagram of the structure of a traditional FC data processing device, such as Figure 5 As shown, in the prior art, the framing unit is usually placed in a data transmission management module in the IP core of the FC, and each data packet needs to be independently processed by a separately configured framing unit.

[0059] In contrast, Figure 2 As shown, in the embodiment of the present application, the framing subunit located in the IP core is placed outside the IP core and placed at the top layer of logic through the method of frame header information multiplexing, and the data processing unit at the front end adds a unified data length processing function. When multiple data packets arrive, the data processing unit processes the length of the data so that it is sent to the frame header information multiplexing unit with the same length in the FC timing format. The framing subunit in the frame header information multiplexing unit adds an optional header and a frame header field to the data field. After the framing is completed, it is sent to the data sending unit for further framing and verification processing. Finally, the high-speed serial channel converts the obtained FC data frame into high-speed serial data for transmission.

[0060] It should be noted that in the process of multiplexing the frame header information, since the data length information is consistent, all data can use the same OPT optional header. For the frame header field HEADER, in the specified FC data frame, the control words such as R_CTL and CS_CTL are the same, so all data can use the same control word, and it is only necessary to dynamically configure the various ID identifiers in the frame header field according to specific requirements, and finally send the generated high-speed serial format FC data frame through IP and high-speed serial channels.

[0061] The device of the embodiment of the present application designs an FC frame header information multiplexing method based on the optimization of the FC protocol specification, optimizes the internal architecture of the FC IP core, enables multiple FC IP cores to uniformly call the same data framing unit before data transmission, processes each data packet into an FC data packet with the same frame header, and supports dynamic configuration of data ID identifiers, further simplifying the FC data processing flow, reducing on-chip resource consumption, and improving the efficient and rapid transmission of FC data communication information.

[0062] Continue to refer to Figure 2 In the embodiment of the present application, each sub-transmission unit 31 includes a data transmission management module 311 and a high-speed serial channel 312 connected in sequence; the data transmission management module 311 includes a frame management subunit 3111 and a credit detection subunit 3112; The frame management subunit 3111 is used to add a frame start and a frame end to the corresponding second FC data packet to obtain a corresponding FC data frame, and convert the corresponding FC data frame into high-speed serial data; The credit detection subunit 3112 is used to verify the corresponding FC data frame and obtain a FC data frame that passes the verification; The high-speed serial channel 312 is used to send high-speed serial data corresponding to the FC data frame that has passed the inspection.

[0063] Specifically, in an embodiment of the present application, after receiving each second FC data packet processed and output by the frame header information multiplexing unit, the data transmission unit sends each second FC data packet to the corresponding sub-transmission unit for processing. Furthermore, after receiving the second FC data packet, the data transmission management module in each sub-transmission unit first sends it to the internal frame management sub-unit for processing, and the frame management sub-unit adds a frame start SOF and a frame end EOF to the second FC data packet to form a corresponding FC data frame, and converts the FC data frame into high-speed serial data.

[0064] Further, in the embodiment of the present application, the internal credit detection subunit verifies the corresponding FC data frame to obtain a FC data frame that passes the verification. The credit detection subunit is a BUFFER TO BUFFER data transmission mechanism of FC, which is used to achieve zero packet loss at the link layer. The unit does not participate in the framing and frame management process, and its function is to ensure that the FC-AE-ASM data packet can be transmitted through the high-speed serial channel without packet loss.

[0065] Furthermore, in an embodiment of the present application, the high-speed serial data corresponding to the verified FC data frame will be transmitted to the high-speed serial channel, and the high-speed serial data will be sent through the high-speed serial channel.

[0066] In the device of the embodiment of the present application, during the data transmission stage, the data transmission management module further frames the FC data packets and verifies the obtained FC data frames, thereby ensuring the integrity and accuracy of the data during transmission and further improving the reliability and efficiency of FC data transmission.

[0067] It should be noted that in the prior art, when multiple FC IP cores are placed in the same QUAD, there will be a clock allocation conflict caused by competition among the internal clock management units of multiple IP cores. In a specific hardware or software architecture, a QUAD usually refers to an area or module that contains specific resources (such as logic units, clock modules, etc.).

[0068] To avoid this problem, the conventional method is to place multiple FC cores in different QUADs, but this will lead to a problem of reduced channel utilization within the QUAD.

[0069] In order to solve the above technical defects, the device of the embodiment of the present application also provides a management clock multiplexing unit.

[0070] Figure 6 is a schematic diagram of the structure of the device management clock multiplexing system provided in the embodiment of the present application, such as Figure 6 As shown, as an optional embodiment, the device further includes a management clock multiplexing unit 4; The management clock multiplexing unit 4 includes a master clock unit 41 and a plurality of slave clock units 42; The master clock unit 41 is used to simultaneously control each slave clock unit 42 to generate a channel clock signal synchronized with itself, and distribute each channel clock signal to the high-speed serial channel 312 in the corresponding IP core; the clock signal of the master clock unit is determined based on the external reference clock; each IP core is placed in the same QUAD.

[0071] Specifically, in the embodiment of the present application, in the implementation method of managing clock multiplexing, since each IP core will occupy a certain number of high-speed channels, according to the maximum number of high-speed channels supported by a single QUAD, the IP cores located in different QUADs are taken out and still placed in the same QUAD, so that all high-speed channel ports in the QUAD can be fully utilized as much as possible. Each IP core has its own clock management unit. In order to ensure that the clock distribution of multiple IP cores in the same QUAD does not conflict, there can be at most one clock management unit in a QUAD, that is, the management unit in the clock unit in the IP core is set to a master-slave mode, including a master clock unit and multiple slave clock units. The slave clock is controlled by the master clock management unit, and the slave clock management unit in the same QUAD reuses the clock signal of the master clock management unit, thereby avoiding clock distribution conflicts.

[0072] Specifically, if Figure 6 As shown in the figure, an IP core is selected from multiple IP cores in the same QUAD1, and the clock management unit responsible for the IP core is placed at the top level of the QUAD logic and set as the master clock management unit. The clock of the master clock unit is connected by an external reference clock. The master clock management unit is configured to act on multiple slave clock management units in a QUAD at the same time to drive multiple high-speed serial channels.

[0073] Each IP core includes a clock management unit and provides up to 2 FC high-speed serial channels. Usually, when multiple FC signals are output, in order to avoid the problem of clock conflicts, only one IP core is configured in each QUAD. In an embodiment of the present application, by adopting a management clock multiplexing method, n IP cores are placed in the same QUAD1, and the upper limit of n depends on 1 / 2 of the maximum number of high-speed serial channels that QUAD1 can support. The clock management unit is taken out of the IP core and only one clock management unit is retained. All IP cores share one clock management unit and place the clock management unit at the top logical level, that is, as the master clock management unit. The master clock management unit can be driven by a single-ended clock after the external 212.5MHz differential reference clock is converted by the first-level global buffer IBUFG. Multiple channel clocks are generated by controlling each slave clock unit and redistributed to up to 2n high-speed serial channels.

[0074] The device of the embodiment of the present application introduces the FC management clock multiplexing method, embeds the bottom-level clock management unit in the original FC IP core into the top of the FC IP core, and uses the master-slave clock synchronization method to redistribute the channel clock, which can effectively solve the clock conflict problem faced by running multiple FC cores in a traditional hardware area. At the same time, through the FC management clock multiplexing method, hardware resources can be further saved and the information transmission efficiency of the system can be improved.

[0075] Figure 7 This is a third structural diagram of a data processing device based on FC multi-channel multiplexing provided in an embodiment of the present application, such as Figure 7 As shown, in the embodiment of the present application, the data processing unit 1 is responsible for providing three parts: an external reference clock interface IBUFG, a data length processing subunit, and an FC timing control subunit. Among them, the data length processing subunit converts input data DATA of different lengths into data of the same length, and the FC timing control subunit can convert these data streams into data frames that conform to the FC timing format, and transmit them to the frame header information multiplexing unit 2 for processing, wherein each frame of FC data is composed of four parallel data streams of the start identifier SOP, enable EN, end identifier EOP and data field FC_DATA; at the same time, the external 212.5MHz differential reference clock is sent to the management clock multiplexing unit 4 through IBUFG.

[0076] In this embodiment, the information multiplexing unit 5 includes a management clock multiplexing unit 4 and a frame header information multiplexing unit 2, which is used to implement multiplexing processing of the management clock and the frame header information according to the frame header information multiplexing method and the management clock multiplexing method of the aforementioned embodiment, which will not be described in detail. Finally, the FC-AE-ASM data carrying the clock information after multiplexing is distributed to the data sending unit 3, and the data sending unit 3 completes the data packetization, processes it into high-speed serial data, and sends it through the internal 2n high-speed serial channels.

[0077] It should be noted that in an embodiment of the present application, when performing frame header information multiplexing, the framing unit located in the IP core is taken outside the core to form a frame header information multiplexing unit, and the control field and the ASM optional header field in the frame header field are multiplexed during the data framing process, and the ID identifier in the frame header field is dynamically configured. In the process of frame header information multiplexing, it is necessary to ensure that all field information except the ID identifier is consistent, especially the data length information is consistent. When FC data of different lengths enter the data processing unit one after another, it is necessary to write the incoming data into the data cache, read the data with the same length, and then perform data framing. Finally, the information is sent through the data sending unit, aiming to ensure that each output FC data reuses the same frame header field.

[0078] The device of the embodiment of the present application provides a data processing method based on FC multi-channel multiplexing, realizes efficient and fast transmission of FC protocol data, and introduces an FC management clock multiplexing method and an FC frame header information multiplexing method by adding a multiplexing management frame of the FC protocol, thereby greatly improving the resource utilization of the high-speed serial channel in a single QUAD under the premise that the existing hardware resources remain unchanged. At the same time, the FC data processing process is greatly simplified, the consumption of on-chip resources is reduced, and the working efficiency of the FC signal processing system is improved.

[0079] The data processing method based on FC multi-channel multiplexing provided by the present application is described below. The data processing method described below and the data processing device based on FC multi-channel multiplexing described above can refer to each other.

[0080] Figure 8 is a flow chart of a data processing method based on FC multi-channel multiplexing provided in an embodiment of the present application. The method can be applied to any of the aforementioned data processing devices based on FC multi-channel multiplexing, such as Figure 8 As shown, the method includes: Step S1, processing the received multiple data packets into multiple first FC data packets of the same length; Step S2, processing each first FC data packet into a second FC data packet with the same frame header information; Step S3, performing data framing on each second FC data packet to obtain an FC data frame corresponding to each second FC data packet, and converting each FC data frame into high-speed serial data for transmission.

[0081] It can be understood that the detailed embodiments of the above method can refer to the introduction of the detailed functional implementation of each unit / module in the above device embodiment, which will not be repeated here.

[0082] It should be understood that the above method is applied to the device in the above embodiment. The implementation principle and technical effect of the method are similar to the description of the corresponding program module in the above device. The corresponding process in the method can refer to the working process of the device and will not be repeated here.

[0083] The data processing method based on FC multi-channel multiplexing in the embodiment of the present application optimizes the FC protocol specification, processes multiple received data packets into multiple FC data packets with the same length, uses a frame header information multiplexing unit to multiplex FC data frame header information, processes these FC data packets into FC data packets with the same frame header information, and uses each sub-transmitting unit to perform data framing on the FC data packets with the same frame header information received by each sub-transmitting unit, converts the obtained FC data frames into high-speed serial data for transmission, which can effectively simplify the processing flow of FC data, and while ensuring the efficient and rapid transmission of FC data communication information, improves the utilization rate of the system's high-speed serial channels, saves hardware resources, and thus improves the information transmission efficiency of the system.

[0084] Based on the content of the above embodiment, as an optional embodiment, processing each first FC data packet into a second FC data packet with the same frame header information includes: Adding the same optional header field of the FC protocol and the same frame header field of the FC protocol to the data field of each first FC data packet to obtain each first FC data packet having the same frame header; A corresponding ID identifier is configured for each first FC data packet having the same frame header to obtain each second FC data packet.

[0085] Based on the content of the above embodiment, as an optional embodiment, processing the received multiple data packets into multiple first FC data packets of the same length includes: Processing multiple data packets into multiple data packets of the same length; Based on the multiple data packets with the same length, multiple first FC data packets conforming to the FC timing format are generated.

[0086] Based on the method in the above embodiment, the embodiment of the present application provides an electronic device, such as Fig. 9As shown, the electronic device may include: a processor (Processor) 910, a communication interface (Communications Interface) 920, a memory (Memory) 930 and a communication bus 940, wherein the processor 910, the communication interface 920, and the memory 930 communicate with each other through the communication bus 940. The processor 910 may call the logic instructions in the memory 930 to execute the method in the above embodiment.

[0087] In addition, the logic instructions in the above-mentioned memory 930 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0088] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0089] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0090] It is understandable that the processor in the embodiment of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0091] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0092] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0093] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0094] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0095] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data processing device based on FC multi-channel multiplexing, characterized in that: include: A data processing unit, a frame header information multiplexing unit and a data sending unit connected in sequence; the data sending unit includes a plurality of sub-sending units; each of the sub-sending units is configured with an IP core; The data processing unit is used for processing the received multiple data packets into multiple first FC data packets of the same length; The frame header information multiplexing unit is used for processing each of the first FC data packets into a second FC data packet with the same frame header information; Each of the sub-transmitting units is used to call its own IP core to perform data framing on the second FC data packets received by it to obtain corresponding FC data frames, and convert the corresponding FC data frames into high-speed serial data for transmission.

2. The data processing device according to claim 1, characterized in that: The frame header information multiplexing unit includes a framing subunit and an ID identifier configuration subunit; The framing subunit is used to add the same optional header field of the FC protocol and the same frame header field of the FC protocol to the data field of each of the first FC data packets, so as to obtain each of the first FC data packets having the same frame header; The ID identifier configuration subunit is used to configure a corresponding ID identifier for each of the first FC data packets having the same frame header, so as to obtain each of the second FC data packets.

3. The data processing device according to claim 1, characterized in that: The data processing unit includes a data length processing subunit and an FC timing control subunit; The data length processing subunit is used for processing the multiple data packets into multiple data packets with the same length; The FC timing control subunit is used to generate a plurality of first FC data packets conforming to the FC timing format based on the plurality of data packets with the same length.

4. The data processing device according to claim 3, characterized in that: The data length processing subunit is specifically used for: Writing the multiple data packets into a data cache; Reading each of the data packets from the data buffer with a target length until the last data packet of each of the data packets is read; If it is determined that the length of the last data packet is equal to the target length, reading the last data packet; If it is determined that the length of the last data packet is less than the target length, the end of the last data packet is padded with zeros until the length of the last data packet after the zero padding is equal to the target length, and the last data packet after the zero padding is read.

5. The data processing device according to claim 1, characterized in that: Each of the sub-transmission units includes a data transmission management module and a high-speed serial channel connected in sequence; the data transmission management module includes a frame management sub-unit and a credit detection sub-unit; The frame management subunit is used to add a frame start and a frame end to the corresponding second FC data packet to obtain a corresponding FC data frame, and convert the corresponding FC data frame into high-speed serial data; The credit detection subunit is used to verify the corresponding FC data frame to obtain a FC data frame that passes the verification; The high-speed serial channel is used to send the high-speed serial data corresponding to the FC data frame that has passed the inspection.

6. The data processing device according to any one of claims 1 to 5, characterized in that: The device also includes a management clock multiplexing unit; The management clock multiplexing unit includes a master clock unit and a plurality of slave clock units; The master clock unit is used to simultaneously control each of the slave clock units to generate a channel clock signal synchronized with itself, and distribute each channel clock signal to the high-speed serial channel in the corresponding IP core; the clock signal of the master clock unit is determined based on an external reference clock; each of the IP cores is placed in the same QUAD.

7. A data processing method applied to the data processing device based on FC multi-channel multiplexing as claimed in any one of claims 1 to 6, characterized in that: include: Processing the received multiple data packets into multiple first FC data packets with the same length; Processing each of the first FC data packets into a second FC data packet with the same frame header information; Perform data framing on each of the second FC data packets to obtain FC data frames corresponding to each of the second FC data packets, and convert each of the FC data frames into high-speed serial data for transmission.

8. The data processing method according to claim 7, characterized in that: The processing of each of the first FC data packets into a second FC data packet with the same frame header information includes: Adding the same optional header field of the FC protocol and the same frame header field of the FC protocol to the data field of each of the first FC data packets to obtain first FC data packets having the same frame header; A corresponding ID identifier is configured for each of the first FC data packets having the same frame header to obtain each of the second FC data packets.

9. The data processing method according to claim 7, characterized in that: The step of processing the received multiple data packets into multiple first FC data packets with the same length includes: Processing the multiple data packets into multiple data packets of the same length; Based on the multiple data packets with the same length, multiple first FC data packets conforming to the FC timing format are generated.

10. An electronic device, characterized in that: include: at least one memory for storing a computer program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the data processing method as described in any one of claims 7 to 9.

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