An anti-side channel attack ntt circuit for lattice-based cryptographic algorithms

Abstract

The application discloses an anti-side channel attack NTT circuit for a lattice-based cryptographic algorithm, comprising: a control unit mainly controlling the enabling of the underlying components in the structure and the data flow between modules; a storage unit for storing coefficients, random rotation factor addresses and rotation factors; an address generation unit for calculating and generating the storage RAM address of the rotation factor participating in operation and the read address required by the coefficient storage unit; and a coefficient transposition unit for realizing the coefficient reading satisfying the index distance between all NTT stages. The anti-side channel attack NTT circuit for the lattice-based cryptographic algorithm reduces the increase of the modulus multiplication resource when masking the low-latency base-4 CT / GS butterfly unit, realizes the significant reduction of resource consumption while maintaining high security.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of information security and cryptographic hardware circuit, and particularly relates to an NTT circuit resisting side channel attacks for lattice-based cryptographic algorithms. BACKGROUND

[0002] The rapid development of quantum computers poses a serious challenge to modern encryption systems. Shor's algorithm significantly weakens the security of encryption systems based on RSA and ECC algorithms. In order to cope with the changes in future information security, NIST launched the Post-Quantum Cryptography (PQC) standardization process in 2016, and announced four PQC standard algorithms including CRYSTALS-Dilithium in 2023. However, while pursuing high mathematical security of lattice-based cryptographic schemes, the threat of side channel attacks (SCA) cannot be ignored. Attackers may use side channel information such as time and power consumption of the system when performing core operators to obtain sensitive information, which brings new challenges to the security of lattice-based cryptographic systems.

[0003] In the RLWE-based cryptographic system, the key is composed of polynomials in a finite ring, and encryption and decryption involve multiplication operations with the key polynomial. This kind of multiplication is an ideal target for SCA. NTT, as a common method to accelerate polynomial multiplication, currently faces one of the main attack methods, single-trace attack (SA). Soft analysis side channel attack (SASCA) was first proposed by Veyrat-Charvillon et al. in 2015, which is a type of attack that combines tracking information and algorithm information. This attack combines algebraic side channel attack (ASCA) with noise tolerance (DPA) based on divide-and-conquer differential energy analysis, which has low time and space complexity. Attackers use the sparsity of intermediate variable information of actual leakage traces to effectively recover the key. Primas et al. first applied this method to side channel attacks on NTT, and implemented SA using the leakage during NTT execution. First, INTT is selected as the attack target, then a factor graph is constructed according to the NTT algorithm, and finally the private key is solved using lattice decoding, but this attack requires about 1 million templates. Pessl et al. reduced the number of templates required for SA to only 213, successfully performed full-key recovery on the constant-time Kyber implemented on an ARM Cortex-M4 microcontroller, and suggested protecting NTT from the above SA by Shuffling or randomizing butterfly operations.

[0004] Ravi et al. proposed two schemes of Shuffling and Randomization for the SA attack of NTT, and evaluated their performance on ARM Cortex-M4 microcontroller. In the randomization scheme, the power of the rotation factor and is used to replace the random number as a mask, thereby avoiding complex modular inverse operations and realizing the secure design of the underlying CT butterfly unit. On this basis, by updating the random rotation factor used by NTT at different stages, three randomization NTT schemes with different granularities are proposed, which increases the complexity of the NTT calculation process and improves the difficulty of SA. However, this method is limited to the software level and has not been implemented to the hardware level.

[0005] In 2023, Rodriguez et al. implemented a hardware implementation of the base-2 NTT side-channel masking protection scheme on this basis, but the hardware overhead is as high as 2.3 to 5.4 times.

[0006] In 2024 CHES, Rodriguez et al. proposed a flexible way to configure the NTT hardware implementation of the above Shuffling and randomization countermeasures, and analyzed the security of the masking scheme, but the hardware overhead is also more than 2 times. SUMMARY

[0007] To solve the technical problems in the background art, the present application proposes an anti-side channel attack NTT circuit for lattice-based cryptography algorithms.

[0008] The anti-side channel attack NTT circuit for lattice-based cryptography algorithms proposed by the present application comprises:

[0009] The control unit mainly controls the enablement of the underlying components in the anti-side channel attack NTT circuit and the data flow between modules;

[0010] The storage unit is used to store the coefficients, random rotation factor addresses and rotation factors;

[0011] The address generation unit is used to calculate and generate the storage RAM address of the rotation factor participating in the operation and the read address required by the coefficient storage unit;

[0012] The coefficient transposition unit realizes the coefficient reading that meets the index distance between all NTT stages;

[0013] The calculation unit is used to obtain the operation mode of the polynomial, and performs polynomial operation according to the operation mode, rotation factor and coefficient to obtain the operation result corresponding to the polynomial, and writes the operation result back to the coefficient storage.

[0014] Preferably, the output of the control unit is electrically connected with a storage unit, the input of the storage unit is electrically connected with the output of the coefficient transposition unit, the output of the storage unit is electrically connected with the input of the coefficient transposition unit, the output of the storage unit is electrically connected with the input of the address generation unit, the input of the storage unit is electrically connected with the output of the address generation unit, the output of the address generation unit is electrically connected with the input of the twiddle factor storage RAM, the twiddle factor storage RAM is communicatively connected with the twiddle factor pre-processing unit, the twiddle factor pre-processing unit is communicatively connected with the calculation unit, the calculation unit is communicatively connected with the coefficient transposition unit, and the storage unit is communicatively connected with the coefficient transposition unit.

[0015] Preferably, the calculation unit comprises a low latency radix-4 CT butterfly unit and a low latency radix-4 GS butterfly unit, the output of the low latency radix-4 CT butterfly unit is electrically connected with the input of the low latency radix-4 GS butterfly unit, the low latency radix-4 CT butterfly unit comprises six first modular multipliers, four first modular adders and four first modular subtractors, and the low latency radix-4 GS butterfly unit comprises six second modular multipliers, four second modular adders and four second modular subtractors.

[0016] Preferably, the low latency radix-4 CT butterfly unit is used to divide the polynomial into four sub-polynomials, and the four sub-polynomials are operated one by one.

[0017] Preferably, the low latency radix-4 CT butterfly unit comprises four inputs and four outputs, the low latency radix-4 GS butterfly unit comprises four inputs and four outputs, and the four outputs of the low latency radix-4 CT butterfly unit are electrically connected with the four inputs of the low latency radix-4 GS butterfly unit one by one.

[0018] Preferably, in the address generation unit, the read address of the twiddle factor RAM is calculated by the twiddle factor address, the last round random twiddle factor address and the current round random twiddle factor address through addition and subtraction.

[0019] Preferably, the operation mode comprises NTT operation and INTT operation, and the control unit is further used to generate an operation control signal, which determines the current operation mode of the calculation unit.

[0020] Preferably, the coefficient transposition unit comprises a 4x4 array of 16 registers and nine MUXs.

[0021] In the present application, the anti-side channel attack NTT circuit for lattice-based cryptographic algorithm proposed in the present application expands the random rotation factor as the base-2 Cooley-Tukey (CT) butterfly unit structure of the mask to the low-delay base-4 CT butterfly unit, reduces the increase of the modulus multiplication resource when the low-delay base-4 CT / GS butterfly unit is masked, and realizes the significant reduction of resource consumption while maintaining high security. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The hardware structure diagram of the polynomial operation component of the anti-side channel attack NTT circuit for lattice-based cryptographic algorithm in the present application is shown in the figure.

[0023] Figure 2 The existing low-delay base-4 CT butterfly unit circuit structure diagram is shown in the figure.

[0024] Figure 3 The existing low-delay base-4 GS butterfly unit circuit structure diagram is shown in the figure.

[0025] Figure 4 The low-delay base-4 MDISO_BF CT structure diagram of the anti-side channel attack NTT circuit for lattice-based cryptographic algorithm in the present application is shown in the figure.

[0026] Figure 5 The low-delay base-4 MDISO_BFGS structure diagram of the anti-side channel attack NTT circuit for lattice-based cryptographic algorithm in the present application is shown in the figure.

[0027] Figure 6 The transpose unit movement sequence diagram in the NTT mode of the anti-side channel attack NTT circuit for lattice-based cryptographic algorithm in the present application is shown in the figure.

[0028] Figure 7 The transpose unit movement sequence diagram in the INTT mode of the anti-side channel attack NTT circuit for lattice-based cryptographic algorithm in the present application is shown in the figure. DETAILED DESCRIPTION

[0029] REFERENCE Figures 1-7 The anti-side channel attack NTT circuit for lattice-based cryptographic algorithm proposed in the present application,

[0030] comprises:

[0031] a control unit, mainly controlling the enablement of the underlying components in the anti-side channel attack NTT circuit and the data flow between modules.

[0032] In the present embodiment, the operation mode includes NTT operation and INTT operation; the control unit is further configured to generate an operation control signal, and the operation control signal determines the current operation mode of the calculation unit.

[0033] Specifically, the control unit mainly controls the enablement of the underlying components in the architecture and the data flow between the modules. It contains a state machine to control the state of the complete polynomial operation. Mode signal is used as the chip select signal of the selector to realize different data flows in different polynomial operation modes. The RAM chip select signal can control the connection between the RAM output and the coefficient transposition unit and the reconfigurable low-latency base-4 CT / GS unit. The control unit also controls the enablement and read-write control of the RAM unit.

[0034] The storage unit is configured to store the coefficients, the random rotation factor addresses, and the rotation factors.

[0035] The address generation unit is configured to calculate the storage RAM addresses of the rotation factors participating in the operation and the read addresses required by the coefficient storage unit.

[0036] Specifically, in the polynomial operation, the address generation unit is used to generate the read addresses of the rotation factor storage RAM and the polynomial coefficient storage RAM, wherein the rotation factor storage RAM read address is calculated by the butterfly algorithm rotation factor address, the last round random rotation factor address, and the current round random rotation factor address through addition and subtraction. Since the polynomial operation component includes two modes: NTT and INTT, it is crucial to effectively complete the reading of the coefficients in different modes. The address generation method has two ways: dynamic generation and static generation. Static generation requires that the reading rules be written into the ROM in advance for storage, and then the addresses are obtained by directly reading the ROM in sequence during the running process, and the coefficients in the RAM are read with the addresses. This paper adopts the dynamic generation method to generate the read addresses of the RAM in real time. Compared with the static generation method, the dynamic generation method avoids the use of additional ROM resources. In addition, in different modes, the address distribution has obvious rules, and a simple hardware circuit can be used to realize this function. In this paper, the read address generation method of the rotation factor RAM is that the rotation factor address is calculated by the butterfly algorithm rotation factor address, the last round random rotation factor address, and the current round random rotation factor address through addition and subtraction. The last round random rotation factor address is stored in the BRAM together with the coefficient data through the coefficient transposition unit.

[0037] In this embodiment, the read address of the rotation factor RAM in the address generation unit is calculated by the rotation factor address, the last round random rotation factor address, and the current round random rotation factor address through addition and subtraction

[0038] The calculation unit is configured to obtain an operation mode of the polynomial, and perform a polynomial operation according to the operation mode, the rotation factor, and the coefficient to obtain an operation result corresponding to the polynomial, and write the operation result back to the coefficient storage.

[0039] In the embodiment, the computing unit comprises a low-latency base-4CT butterfly unit and a low-latency base-4GS butterfly unit; the output end of the low-latency base-4CT butterfly unit is electrically connected with the input end of the low-latency base-4GS butterfly unit; the low-latency base-4CT butterfly unit comprises six first modular multipliers, four first modular adders and four first modular subtractors; and the low-latency base-4GS butterfly unit comprises six second modular multipliers, four second modular adders and four second modular subtractors.

[0040] In the embodiment, the low-latency base-4CT butterfly unit is used to divide the polynomial into four sub-polynomials, and the four sub-polynomials are operated one by one.

[0041] In the embodiment, the low-latency base-4CT butterfly unit comprises four input ends and four output ends, the low-latency base-4GS butterfly unit comprises four input ends and four output ends, and the four output ends of the low-latency base-4CT butterfly unit are electrically connected with the four input ends of the low-latency base-4GS butterfly unit one by one.

[0042] In the embodiment, the butterfly unit of the side-channel attack-resistant NTT of the lattice-based cryptographic algorithm is as follows:

[0043] The NWC computing process is as follows

[0044]

[0045] Based on the above formula, the pre-processing and the NTT are written together, and the rotation factor is used to obtain

[0046]

[0047] According to the index, the summation of the above formula is divided into four groups of length N / 4, and the rotation factor is used to eliminate , and variables X0, X1, X2 and X3 are used to replace The periodicity of the rotation factor is used, and is obtained, and the polynomial can be divided into four parts and represented as follows: i = 0, 1,..., N / 4-1.

[0048]

[0049] If the above formula is decomposed into two-level operations, the number of modular multiplication, modular addition and modular subtraction operations can be effectively reduced, but the two-layer modular multiplication unit means that the number of pipeline stages required is doubled, which may cause a memory conflict problem when performing the NTT transformation. The root cause of the memory conflict problem is analyzed in detail, and where NTT is the radix of the NTT. We seek a decomposition scheme with higher parallelism of modular multiplication from the perspective of reducing the pipeline stage number, as shown in the following equation:

[0050]

[0051] Figure 2 The corresponding circuit structure of the above equation is shown, which only increases one modular multiplication element compared with the low-computational-complexity radix-4 CT butterfly unit, but can realize parallel operation of all modular multiplication operations. In the case of large multiplication delay, the critical path delay is significantly improved, and the problem of doubling the pipeline depth of modular multiplication is avoided. We call the structure a low-delay radix-4 CT butterfly unit. Figure 2 The low-computational-complexity radix-4 GS butterfly unit is optimized in a similar manner, and we call the structure a low-delay radix-4 GS butterfly unit. Figure 3 The low-computational-complexity radix-4 GS butterfly unit is optimized in a similar manner, and we call the structure a low-delay radix-4 GS butterfly unit.

[0052] According to the principle of MDISO_BF, first mask the first-level operation of the above equation, where the input is X0, X1, X2, X3, which are randomly rotated by the factor Masked X'0, X'1, X'2, X'3, the first-level output Y0, Y1 are masked by the new random rotation factor Mask Y2, Y3 are masked by the new random rotation factor Mask. Then, blind the second-level operation of the above equation with random rotation factors and to obtain the following equation:

[0053]

[0054] As can be seen from the above equation, the low-delay radix-4 CT butterfly unit after masking requires a total of 12 modular multiplication operation resources, and the demand for random numbers is 4. Compared with the low-delay radix-4 CT butterfly structure, radix-4 MDISO_BF increases 7 modular multiplication operation resources, which is also a non-negligible overhead in hardware implementation. In order to further compress the number of modular multiplication operation resources, set the output of the first-level operation to be masked by the same random rotation factor, and the input of the second-level operation to be masked by the same random rotation factor, i.e. r4=r5=r6=r7, which can directly avoid the modular multiplication operation of the second-level operation, and the above equation can be simplified as:

[0055]

[0056] The demand for random numbers is reduced to 1, and the modular multiplication operation resources are reduced to 6. Compared with the low-delay radix-4 CT butterfly unit, only one modular multiplication operation resource is added, and the modular multiplication operation can also be implemented in parallel, which will not affect the overall hardware timing, and the circuit structure is shown in Figure 4 . The low-delay radix-4 GS butterfly unit is masked in a similar manner, and we callFigure 5 The structure is a low-delay base -4MDISO_BF GS structure.

[0057] The coefficient transpose unit enables coefficient reading that satisfies the index distance between all NTT stages.

[0058] In this embodiment, the coefficient transpose unit consists of a 4×4 array of 16 registers and 9 MUXs.

[0059] In this embodiment, a single-address, multi-coefficient storage method is used for coefficient storage. Therefore, unlike multi-bank storage, it is not possible to read the four coefficients that meet the NTT index distance in parallel within a single clock cycle. Instead, coefficients that meet the NTT index distance are stored at different addresses in RAM. Therefore, it takes four clock cycles to complete the reading of the 4×4 coefficient matrix. Each column of the coefficient matrix serves as the input to the NTT, and the remaining data needs to be synchronized using an additional linear shift register to ensure no data loss. When the NTT employs a pipelined design, the above reading method may lead to discontinuities in the pipeline input data, thus affecting the pipeline's utilization and resulting in increased computation time costs and decreased overall system performance. Therefore, achieving coefficient reading that satisfies the index distance between all NTT stages is a design challenge.

[0060] The coefficient transpose unit is responsible for synchronizing and transposing the intermediate data to form a 4×4 matrix. The circuit structure is as follows: Figure 6 As shown, the internal circuitry of the coefficient transpose unit consists of a 4×4 array of 16 registers and 9 MUXs. The red and blue arrows in the diagram indicate two data movement modes, which are executed alternately with a 4-clock cycle. This allows for row (column) data storage and column (row) data retrieval, achieving pipelined synchronization and reordering of input data. Furthermore, the coefficient transpose operation must be performed before data enters the butterfly unit in the NTT and after exiting the butterfly unit in the INTT; the coefficient transpose unit in this paper supports both of these scenarios. Figure 6 and Figure 7 The data flow of the improved coefficient transpose unit during data reordering in the first 8 clock cycles of the first stage in NTT / INTT mode is given.

[0061] Specifically, the hardware implementation of NTT's side-channel masking protection scheme currently consumes more than twice the resources, while this design consumes only 1.56 times the resources for masking, which is far less than other design schemes, while ensuring security.

[0062] In the embodiment, the output of the control unit is electrically connected with the storage unit, the input of the storage unit is electrically connected with the output of the coefficient transposition unit, the output of the storage unit is electrically connected with the input of the coefficient transposition unit, the output of the storage unit is electrically connected with the input of the address generation unit, the input of the storage unit is electrically connected with the output of the address generation unit, the output of the address generation unit is electrically connected with the input of the twiddle factor storage RAM, the twiddle factor storage RAM is communicatively connected with the twiddle factor preprocessing unit, the twiddle factor preprocessing unit is communicatively connected with the calculation unit, the calculation unit is communicatively connected with the coefficient transposition unit, and the storage unit is communicatively connected with the coefficient transposition unit.

[0063] The above merely provides the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art, according to the technical range disclosed by the present application and the inventive concept, should be covered in the protection scope of the present application.

Claims

1. A side-channel attack resistant NTT circuit for a lattice-oriented cryptographic algorithm, characterized in that, The application relates to a control unit, a storage unit, an address generation unit, a coefficient transposition unit and a calculation unit. The control unit mainly controls the enabling of underlying components in an anti-side channel attack NTT circuit and the data flow direction between modules. The storage unit is used for storing coefficients, random rotation factor addresses and rotation factors. The address generation unit is used for calculating and generating storage RAM addresses of rotation factors participating in operation and reading addresses required by the coefficient storage unit. The coefficient transposition unit realizes coefficient reading meeting index distance between all NTT stages. The calculation unit is used for obtaining an operation mode of a polynomial, performing polynomial operation according to the operation mode, rotation factors and coefficients to obtain an operation result corresponding to the polynomial, and writing the operation result back to the coefficient storage unit. The calculation unit comprises a low-delay base-4 CT butterfly unit and a low-delay base-4 GS butterfly unit. The low-delay base-4 CT butterfly unit comprises six first module multipliers, four first module adders and four first module subtractors. The low-delay base-4 CT butterfly unit is used for dividing the polynomial into four-term sub-polynomials and performing operation on the four-term sub-polynomials one by one. In the address generation unit, the reading address of the rotation factor RAM is calculated by addition and subtraction of the rotation factor address, the last round random rotation factor address and the current round random rotation factor address.

2. The side-channel-attack resistant NTT circuit for a lattice-oriented cryptographic algorithm according to claim 1, wherein, The coefficient transposition unit is responsible for synchronizing and transposing a 4*4 matrix composed of intermediate data. The output end of the control unit is electrically connected with the storage unit, the input end of the storage unit is electrically connected with the output end of the coefficient transposition unit, the output end of the storage unit is electrically connected with the input end of the coefficient transposition unit, the output end of the storage unit is electrically connected with the input end of the address generation unit, the input end of the storage unit is electrically connected with the output end of the address generation unit, the output end of the address generation unit is electrically connected with the input end of the rotation factor storage RAM, the rotation factor storage RAM is in communication connection with the rotation factor preprocessing unit, the rotation factor preprocessing unit is in communication connection with the calculation unit, the calculation unit is in communication connection with the coefficient transposition unit, and the storage unit is in communication connection with the coefficient transposition unit.

3. The side-channel-attack-resistant NTT circuit of a lattice-based cryptographic algorithm according to claim 1, wherein the low-latency radix-4 CT butterfly unit comprises four input terminals and four output terminals, and the low-latency radix-4 GS butterfly unit comprises four input terminals and four output terminals, and the four output terminals of the low-latency radix-4 CT butterfly unit are electrically connected to the four input terminals of the low-latency radix-4 GS butterfly unit one by one.

4. The side-channel-attack resistant NTT circuit for a lattice-oriented cryptographic algorithm according to claim 1, wherein, The operation modes include NTT operation and INTT operation; and the control unit is further configured to generate an operation control signal, which determines the current operation mode of the calculation unit.

5. The side-channel-attack resistant NTT circuit for a lattice-oriented cryptographic algorithm according to claim 1, wherein, The coefficient transposition unit comprises a 4x4 array of 16 registers and 9 MUXs.

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