FSK (Frequency Shift Keying) caller identification method based on Verilog optimized sampling frequency

Abstract

The invention discloses an FSK (Frequency Shift Keying) caller identification method for optimizing sampling frequency based on Verilog, which comprises the following steps: S1, a synchronization and clock management module optimizes the sampling frequency based on an FSK modulation signal transmission rate and a time sequence requirement of a voice module; s2, the FSK modulation module converts a digital signal received from the outside into an FSK modulation signal based on a Verilog hardware description language and the optimized sampling frequency, and sends the FSK modulation signal to an A-LAW coding module; and S3, the A-LAW coding module carries out compression coding on the FSK modulation signal, converts the FSK modulation signal into a digital signal and outputs the digital signal through a parallel-serial conversion module so as to carry out caller ID display. According to the FSK caller identification method based on the Verilog optimized sampling frequency, an implementation mode based on the Verilog and the optimized sampling frequency are adopted, the processing capacity of a system and the reliability of data transmission are improved, and the FSK caller identification method based on the Verilog optimized sampling frequency has lower cost and shorter development period.

Description

Technical Field

[0001] The invention belongs to the technical field of communication, and in particular relates to an FSK caller ID method for optimizing sampling frequency based on Verilog. Background Art

[0002] As an important part of modern communication, the caller ID function of the telephone communication system is crucial for users to identify the identity of the caller. Traditional caller ID technology mainly relies on analog signal transmission, which is susceptible to noise interference, and may cause signal distortion and signal loss. With the development of digital communication technology, FSK modulation technology has been widely studied and applied due to its excellent anti-interference ability and relatively simple implementation method. FSK transmits digital information by changing the frequency of the carrier signal. Compared with other modulation methods, FSK modulation is not sensitive to amplitude changes and is more suitable for transmission on analog channels such as telephone lines.

[0003] The implementation of traditional FSK caller ID usually relies on hardware devices or analog circuits, most of which are imported devices with high costs. It is difficult to adapt to the rapidly changing communication standards and requirements, and cannot meet the localization needs of some users. At the same time, because the voice band range is about 300H to 3400Hz, according to the Nyquist sampling theorem, the voice data sampling frequency is generally selected as 8000Hz. However, in actual tests, it was found that this sampling frequency could not successfully implement FSK caller ID. According to the requirements of the "China Caller ID Standard", the baud rate of the FSK modulated signal is 1200bps. If 8KHz is still selected as the sampling frequency, it is found through calculation that 1bit of data requires 6.67 8KHz sampling cycles, and there is incomplete data transmission, which affects the accuracy and reliability of caller ID. Summary of the invention

[0004] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.

[0005] In order to achieve these purposes and other advantages of the present invention, a FSK caller ID method based on Verilog optimized sampling frequency is provided, comprising:

[0006] S1, the synchronization and clock management module optimizes the sampling frequency based on the FSK modulation signal transmission rate and the timing requirements of the voice module;

[0007] S2, FSK modulation module converts the digital signal received from the outside into FSK modulation signal based on Verilog hardware description language and optimized sampling frequency, and sends it to A-LAW encoding module;

[0008] S3, A-LAW encoding module compresses and encodes the FSK modulated signal, converts it into a digital signal and outputs it through the parallel-serial conversion module to facilitate caller ID.

[0009] Preferably, in S1, the optimization of the sampling frequency requires that the master clock mclk and the frame synchronization sampling frequency fs be obtained in the following manner:

[0010] S10, multiply the clock provided by the external crystal oscillator through the PLL ip core to obtain the system clock sys_clk;

[0011] S11, divide sys_clk to get mclk;

[0012] S12, count the rising edges of mclk, when the count value is 255, clear the count value and generate a high level of the main clock frequency cycle as the sampling frequency;

[0013] S13, output mclk and fs to the parallel-serial conversion module, and output sys_clk to the FSK modulation module, the parallel-serial conversion module, and the A-LAW encoding module respectively.

[0014] Preferably, in S2, the process of the FSK modulation module converting the digital signal into an FSK modulation signal is:

[0015] S20, calling the DDS IP core, and configuring the aclken parameter and the phase parameter, wherein the aclken parameter is the enable of the DDS IP core input clock, and the phase parameter is an unsigned bit calculated according to the corresponding sine wave frequency and the sampling frequency;

[0016] S21, based on the single data message format, determine the FSK modulated signal sending order and process through a three-stage state machine;

[0017] S22, sending corresponding data in a corresponding state;

[0018] S23. Based on the state of the state machine, the corresponding data single bit is output to control the DDS IP core to switch the output frequency, thereby generating a corresponding sine wave and obtaining a corresponding FSK signal dds_out.

[0019] Preferably, in S3, the workflow of the A-LAW encoding module includes:

[0020] S30, using a delay module delay with an enable signal pcm_en to delay the 13-bit FSK signal dds_out received from the FSK modulation module by one clock cycle;

[0021] S31, the bit width of the a_law_pcm data output by the A-LAW encoding module is 8 bits, the highest bit of the dds_out data is inverted as a_law_pcm[7], and a_law_pcm[6:4] is the paragraph code;

[0022] S32, sending the paragraph code to the Mux module for selecting and judging the remaining four-bit interval value, and combining the paragraph code and the corresponding interval value to obtain 7-bit data;

[0023] S33, perform XOR operation on the above 7-bit data and "85" to obtain an output value;

[0024] S34: Concatenate a_law_pcm[7] in S31 with the output value of S33 through the Concat module to complete A-LAW encoding.

[0025] The present invention has at least the following beneficial effects: The present invention is different from the prior art in that it adopts a Verilog-based implementation method and an optimized sampling frequency, improves the processing capability of the system and the reliability of data transmission, has lower costs and a faster development cycle, specifically:

[0026] First, the present invention can improve data integrity: by optimizing the sampling frequency, accurate sampling of the FSK modulated signal under different communication conditions is ensured, and data loss and errors are reduced.

[0027] Secondly, the present invention can enhance system reliability: the high-speed processing capability and parallel processing mechanism of FPGA improve system stability and response speed.

[0028] Thirdly, the present invention is flexible and expansible: the generation of FSK modulation signals is realized by software, allowing the system to be flexibly configured and functionally expanded according to different application requirements.

[0029] Fourthly, the present invention can reduce costs: by realizing the generation of FSK modulation signals by means of software and utilizing an integrated solution implemented by FPGA, the demand for external components is reduced, thereby reducing system costs.

[0030] Through the above beneficial effects, the present invention not only realizes FSK modulation in a software manner, but also technically realizes efficient and reliable data transmission and display.

[0031] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1It is a schematic diagram of the internal modules of the Verilog implementation of the FSK modulation signal of the present invention;

[0033] Figure 2 The timing diagram of the parallel-to-serial conversion module of the present invention is shown;

[0034] Figure 3 It is a state machine flow chart of the FSK modulation module of the present invention;

[0035] Figure 4 It is a schematic diagram of the composition of a_law_pcm data of the A_LAW encoding module of the present invention;

[0036] Figure 5 The corresponding diagram of data x and paragraph code of the present invention is

[0037] Figure 6 This is a system architecture diagram for verification of the present invention. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0039] The present invention designs an FSK caller ID method for optimizing sampling frequency based on Verilog (Verilog Hardware Description language). By developing an FSK (Frequency Shift Keying) modulation module and utilizing the programmable characteristics of FPGA, the function of converting digital signals into FSK signals is realized through Verilog hardware description language. The FSK modulation module processes input data according to the caller ID standard, generates corresponding FSK signals, and successfully realizes the caller ID function. At the same time, an optimized sampling frequency is set for the baud rate of FSK modulation through calculation and adjustment. The sampling frequency matches the baud rate of FSK modulation to ensure the integrity and accuracy of data during transmission, thereby improving the accuracy and reliability of caller ID. The specific implementation is as follows:

[0040] 1. Implementation of synchronization and clock management module

[0041] According to the transmission rate of FSK modulation and the timing requirements of the voice module, a suitable master clock (mclk) and frame synchronization (fs) are generated. In the present invention, because the FSK data transmission rate is 1200bit / s, if fs (i.e., sampling frequency) uses 8KHz commonly used in voice, the integrity of the transmitted data cannot be guaranteed, so mclk is changed to 2.4576MHz and the sampling frequency is 9600Hz to optimize signal quality and transmission efficiency.

[0042] The specific implementation method of the master clock and frame synchronization generation is as follows: the clock (65.536MHz) provided by the external crystal oscillator is multiplied by the PLL IP core to obtain the system clock (sys_clk, 157.2864MHz), and then the sys_clk is divided to obtain mclk (2.4576MHz), and then the rising edge of mclk is counted. When the count value is 255, the count value is cleared and a high level of the master clock frequency cycle is generated (that is, fs of 9600Hz).

[0043] The sys_clk, mclk and fs generated above will be output to the corresponding internal modules, such as Figure 1 At the same time, mclk and fs will also be output to the voice module connected outside the FPGA.

[0044] 2. FSK modulation module implementation

[0045] The FSK modulation module of the present invention is responsible for converting digital signals into FSK signals and adopts Verilog hardware description language to realize the generation of FSK modulation signals.

[0046] The specific implementation method for generating FSK modulated signals is as follows: first call the DDS IP core and configure the corresponding parameters, among which the most important are the configuration of the aclken and phase parameters. aclken is the enable of the input clock of the IP core. In this module, aclken is the rising edge of the clken of the parallel-to-serial conversion module. Phase is the unsigned bit calculated according to the corresponding sine wave frequency and sampling frequency, and the 6-digit hexadecimal data of the decimal place, that is, the phases corresponding to the logic "0" and "1" are "3aab" and "2000" respectively (the calculation method is the corresponding sine wave frequency / sampling frequency), thereby realizing the binary "0" and "1" sine waves in FSK modulation, and their frequencies are 2200Hz and 1200Hz respectively.

[0047] Secondly, according to the format of caller identification information data specified in the "China Caller ID Standard", this patent implements a single data message format, and sorts out the data transmission order and process according to this format. See the flowchart Figure 3 , the FSK modulation signal sending sequence and process are realized through a three-stage state machine, Figure 4 fsk_en is an external enable signal, which is located between the first and second ring currents. The next state is determined by whether fsk_en is '1'; clken_cnt counts the rising edge of clken (ie, clken_r). The counting method corresponding to the software code belongs to the prior art, so it will not be shown here:

[0048] Then, the corresponding data is sent in the corresponding state. The waiting state is to ensure that the DDS IP core has started to output data normally. The waiting time is about 0.3ms; the channel occupation signal state is to send 300 bits of "0" and "1" alternately, and the flag signal state is to send 180 bits of "1". For the data in the other states, a 0 is preceded by each data word as the start bit and a 1 is added at the end as the end bit. The lowest bit of each data word is sent first. In this way, each word actually occupies 10 bits, that is, 1XXXXXXXX0. The data word sent in the message type state is "00000100", which means that the message type is a single data format; the data sent in the flag bit 1 state is 10 bits of "1", and the flag bit 2 and the flag bit are all sent. The data sent in the flag 3 state is consistent with the flag 1; the data sent in the message length state needs to be calculated, and its value is the flag of the sum of the date and time and the length of the calling number; the date and time of this module is a fixed value (8 bytes, month, day, hour and minute, 2 bytes each), which can be modified to obtain the time from the outside later; the calling number state is the calling number input from the outside, with a maximum length of 11 bits, and the date and length are both ASCII codes; the data sent in the check state is the calculated corresponding check word, which is calculated in the 256 mode and complement. The specific data words that need to be calculated and checked are: message type, message length, date and time, and calling number.

[0049] Finally, the corresponding data is output in single bits according to the state of the state machine, and the lowest bit is sent first and the highest bit is sent last. The single bit data can be used to select the phase of the corresponding DDS IP core, that is, the DDS IP core is controlled according to the single bit data output as needed to switch the output frequency, thereby generating the corresponding sine wave and obtaining the corresponding FSK signal.

[0050] 3. Implementation of A-LAW encoding module

[0051] According to the A-LAW 13-fold nonlinear coding rules, an A-LAW coding module is designed to compress and encode the FSK signal (13 bits) generated by the FSK modulation module and convert it into a digital signal (8 bits).

[0052] The specific implementation method of the A-LAW encoding module is as follows: This module is implemented by building a model on the Simulink platform of the System Generator software. First, confirm the input and output signals. The input is the 13-bit FSK signal (dds_out) and its data valid signal (pcm_en) from the FSK modulation module. First, use a delay module (delay) with an enable signal to delay dds_out by one clock cycle. The enable signal is pcm_en to ensure the stability of the input data.

[0053] The bit width of the a_law_pcm data output by the A-LAW encoding module is 8 bits. For details on the meaning of each bit, see Figure 4 , a_law_pcm[7] is the inversion of the highest bit of the dds_out data, that is, the inversion of the sign bit (the highest bit is extracted by the BitBasher module and inverted by the Inverter module); a_law_pcm[6:4] is the paragraph code. The encoding of the paragraph code first uses the highest bit obtained by the BitBasher module to determine the positive or negative number. If it is a positive number, the lower 12 bits of dds_out remain unchanged. If it is a negative number, the lower 12 bits of dds_out are first inverted and then added by 1 to obtain its complement, and then the lower 12 bits of dds_out are added to 2 respectively. 048, 1024, 512, 256, 128, 64, and 32 are ANDed through the Logic module. The value after the operation is compared with "0" through the Relational module. If it is not equal to "0", the Relational module outputs "1", otherwise it is "0". Each output result of the Relational module is concatenated into 8-bit data x through the Concat module. The above operation constitutes the upper seven bits of the data x. The lowest bit of x is dds_out[11:5] (BitBasher intercepts the upper seven bits of the lower 12 bits of dds out) and is compared with "0" through the Relational module. If it is equal to "0", the output is "1", otherwise it is "0", that is, the value output by this module is the lowest bit of the data x.

[0054] Write a paragraph code judgment module to judge the paragraph code corresponding to data x, and its corresponding value is as follows Figure 5 The output paragraph code is then sent to the Mux module to select and determine the remaining four-bit interval value, and the paragraph code and the corresponding interval value are combined to obtain 7-bit data. This data is XORed with "85" through the Expression module, and the initial a_law_pcm[7] and the value output by this module are concatenated through the Concat module to obtain the a_law_pcm after encoding, that is, A-LAW encoding is completed.

[0055] 4. Implementation of parallel-serial conversion module

[0056] Realize parallel-to-serial conversion, converting the parallel data generated by the A-LAW encoding module into a serial data stream.

[0057] The specific implementation of parallel-to-serial conversion is as follows: Figure 2As shown in the timing diagram, according to the sys_clk, mclk and fs signals generated by the synchronization and clock management module, a cycle of clken is generated when mclk falls and fs is 1 for use by the FSK modulation module; when fs is high, mclk sends data dt on the rising edge, and the a_law_pcm (8-bit) data from the a_law_encode module is shifted left by 1 bit each time mclk falls. dt is the highest bit of the eight-bit data, thereby converting the 8-bit parallel data into serial data, and sending the highest bit first and the lowest bit last.

[0058] 5. System integration and testing

[0059] Integrate the modules 1-4 above into one project, compile the program, burn the program into the FPGA chip, and build the test system in advance, such as Figure 6 As shown, the system is tested again to verify the accuracy and stability of the FSK modulation signal.

[0060] The specific implementation of system integration and testing is as follows: In the above integrated project, the vio module is used to control the number to be displayed on the analog phone screen in real time, and a voice flow control module (this module has been successfully applied in other projects) is added to ensure the completeness of the call process. Then, the FSK signal is generated according to the timing required by the "China Caller ID Standard". The analog phone screen is observed. If the displayed number is the number pre-set by vio, it means that the FSK signal is successfully generated. In order to verify the sampling frequency and ensure the accuracy of the FSK signal, the code is also modified to change the sampling frequency to 8KHz, that is, the phase parameter of the DDS ip core is changed to hexadecimal "4666" and "2666". In this case, no number is displayed on the analog phone.

[0061] Through the above specific implementation, the FSK caller ID method of the present invention is realized, and its feasibility is verified through actual tests. At the same time, the system ensures the integrity of the FSK signal by optimizing the sampling frequency.

[0062] The above solution is only an illustration of a preferred embodiment, but is not limited thereto. When implementing the present invention, appropriate replacement and / or modification can be performed according to user needs.

[0063] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and the embodiments. It can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily realized. Therefore, without departing from the general concept defined by the claims and equivalent scope, the present invention is not limited to the specific details and the illustrations shown and described here.

Claims

1. A FSK caller ID method based on Verilog to optimize sampling frequency, characterized in that: include: S1, the synchronization and clock management module optimizes the sampling frequency based on the FSK modulation signal transmission rate and the timing requirements of the voice module; S2, FSK modulation module converts the digital signal received from the outside into FSK modulation signal based on Verilog hardware description language and optimized sampling frequency, and sends it to A-LAW encoding module; S3, A-LAW encoding module compresses and encodes the FSK modulated signal, converts it into a digital signal and outputs it through the parallel-serial conversion module to facilitate caller ID.

2. The FSK caller ID method based on Verilog optimization sampling frequency as claimed in claim 1, characterized in that: In S1, the optimization of the sampling frequency requires the acquisition of the adapted master clock mclk and frame synchronization sampling frequency fs as follows: S10, multiply the clock provided by the external crystal oscillator through the PLL ip core to obtain the system clock sys_clk; S11, divide sys_clk to get mclk; S12, count the rising edges of mclk, when the count value is 255, clear the count value and generate a high level of the main clock frequency cycle as the sampling frequency fs; S13, output mclk and fs to the parallel-serial conversion module, and output sys_clk to the FSK modulation module, the parallel-serial conversion module, and the A-LAW encoding module respectively.

3. The FSK caller ID method based on Verilog optimization sampling frequency as claimed in claim 1, characterized in that: In S2, the process of the FSK modulation module converting the digital signal into the FSK modulation signal is as follows: S20, calling the DDS ip core, and configuring the aclken parameter and the phase parameter, wherein the aclken parameter is the enable of the DDS ip core input clock, and the phase parameter is an unsigned bit calculated according to the corresponding sine wave frequency and the sampling frequency; S21, based on the single data message format, determine the FSK modulated signal sending order and process through a three-stage state machine; S22, sending corresponding data in a corresponding state; S23. Based on the state of the state machine, the corresponding data single bit is output to control the DDS IP core to switch the output frequency, thereby generating a corresponding sine wave and obtaining a corresponding FSK signal dds_out.

4. The FSK caller ID method based on Verilog optimized sampling frequency as claimed in claim 1, characterized in that: In S3, the workflow of the A-LAW encoding module includes: S30, using a delay module delay with an enable signal pcm_en to delay the 13-bit FSK signal dds_out received from the FSK modulation module by one clock cycle; S31, the bit width of the a_law_pcm data output by the A-LAW encoding module is 8 bits, the highest bit of the dds_out data is inverted as a_law_pcm[7], and a_law_pcm[6:4] is the paragraph code; S32, sending the paragraph code to the Mux module for selecting and judging the remaining four-bit interval value, and combining the paragraph code and the corresponding interval value to obtain 7-bit data; S33, perform XOR operation on the above 7-bit data and "85" to obtain an output value; S34: Concatenate a_law_pcm[7] in S31 with the output value of S33 through the Concat module to complete A-LAW encoding.

Images