Dynamic image and video display device and method

Abstract

The invention discloses a dynamic image and video display device and method, and the method comprises the steps: transmitting a dynamic image TFT needing to be displayed to a dynamic image control board assembly MCU2 through a USB power supply port and a test board assembly MCU1 via a UART communication module, carrying out the image processing and data processing of the dynamic image control board assembly MCU2, and transmitting the processed data to a nixie tube lamp ring module and a liquid crystal display module. Through research on a picture compression mode and a data transmission mode, requirements are met, dynamic display of images and video switching are achieved, high portability and high compatibility are achieved, the scheme design cost is reduced, and the competitiveness and market share of products are improved.

Description

Technical Field

[0001] The present invention relates to a dynamic image and video display device and method, and in particular to a dynamic image and video display device and method with low storage, high efficiency, and realizing dynamic image display and seamless video connection. Background Art

[0002] Simple static display interfaces can no longer meet the user experience and needs. The market needs dynamic images or video displays to enrich the user's vision. Currently, the solutions on the market that can meet the dynamic image display effect are all high-cost solutions with RGB interfaces, that is, high-end processors + large-capacity memory (Flash + SDRAM). Such costs are not competitive in the consumer electronics market.

[0003] In order to reduce costs and improve market competitiveness while meeting customer needs, we analyze dynamic display characteristics through software algorithms and reduce dependence on Flash capacity to achieve rich and diverse dynamic image displays. We optimize the display effects through software processing to achieve seamless connection of multiple videos. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a dynamic image and video display device and method, which has the characteristics of low storage, high efficiency, and realization of dynamic image display and seamless video connection.

[0005] In order to solve the above technical problems, the technical solution of the present invention is: a dynamic image and video display device, whose innovation lies in: the dynamic image and video display device includes a lower base, an upper base arranged above the lower base, a PCBA1 board arranged on the lower base, a test board assembly MCU1 arranged on the PCBA1 board, a plastic frame snap-connected to the upper base and located above the PCBA1 board, a PCBA2 board arranged below the plastic frame, a dynamic image control board assembly MCU2 and a digital tube light ring module arranged on the PCBA2 board, a liquid crystal display module arranged above the plastic frame, and a button arranged on the plastic frame in direct contact with the PCBA2 board, and a USB power supply port connected to the PCBA1 board is formed between the upper base and the lower base.

[0006] Preferably, the upper base is threadedly connected or screwed to the lower base; the PCBA1 board adhesive is arranged on the lower base plate.

[0007] Preferably, the plastic frame is provided with connecting columns extending into preset holes on the PCBA2 board, and the connecting columns are connected to the PCBA2 board by thermal riveting.

[0008] Preferably, the liquid crystal display module is composed of a TFT and a semi-transparent cover plate combined by OCA optical bonding.

[0009] A dynamic image and video display method adopts the dynamic image and video display device. The dynamic image and video display method is to transmit the dynamic image TFT to be displayed to the dynamic image control board component MCU2 through the USB power supply port and the test board component MCU1 via the UART communication module, and then transmit it to the digital tube light ring module and the liquid crystal display module after image processing and data processing by the dynamic image control board component MCU2.

[0010] Preferably, the data processing of the dynamic image control board component MCU2 adopts a dual cache mechanism, including cache A and cache B respectively connected to the dynamic image control board component MCU2, and databases respectively connected to the cache A and cache B, the cache A corresponds to the pic1 data that needs to be displayed and is connected to the dynamic image control board component MCU2, the cache B corresponds to the pic2 data that needs to be displayed and is connected to the dynamic image control board component MCU2, and the cache A and cache B work alternately.

[0011] Preferably, the cache A and cache B work alternately. During data processing, cache A is used to store the pic1 data that currently needs to be displayed, and cache B is used to prepare the data of the next pic2 that needs to be displayed. After the data in cache A is read and displayed, the dynamic image control board component MCU2 will switch to cache B for data reading, and cache A is used to prepare new data.

[0012] Preferably, the image processing of the dynamic image control board component MCU2 is as follows: the dynamic image TFT obtained by the dynamic image control board component MCU2 is subjected to picture format conversion, pixel matrix generation, functional area division, area importance evaluation and construction of color table, index matrix compression in sequence to obtain compressed data, and then data caching is performed through block caching, cache area 1 and cache area 2. After the caching processing, the data is read and decoded by the MCU to obtain data for reading or extraction, and then the data is fed back to the liquid crystal display module for LED dynamic display.

[0013] Preferably, the MCU reads and decodes so that the H.264 hardware timing and the timing of reading memory are operated independently.

[0014] The advantages of the present invention are: by studying the image compression method and the data transmission method, the needs are met, the dynamic display of images and video switching are realized, high portability and high compatibility are achieved, the design cost of the solution is reduced, and the competitiveness and market share of the product are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0016] Figure 1 It is a schematic diagram of the physical structure of a dynamic image and video display device and method of the present invention;

[0017] Figure 2 It is a flow chart of a dynamic image display method of a dynamic image and video display device and method of the present invention;

[0018] Figure 3 It is a schematic diagram of a data transmission method in a dynamic image and video display device and method of the present invention;

[0019] Figure 4-1 This is a schematic diagram of the traditional video decompression and playback process;

[0020] Figure 4-2 It is an implementation path diagram of a method for realizing seamless connection of video in a dynamic image and video display device and method of the present invention;

[0021] Figure 4-3 It is a specific implementation path diagram of a method for realizing seamless connection of video in a dynamic image and video display device and method of the present invention;

[0022] Figure 5 It is a stereoscopic diagram of a dynamic image and video display device in a dynamic image and video display device and method of the present invention.

[0023] Figure 6 It is a three-dimensional exploded view of a dynamic image and video display device in a dynamic image and video display device and method of the present invention.

[0024] Figure 7 It is a three-dimensional cross-sectional view of a dynamic image and video display device in a dynamic image and video display device and method of the present invention.

[0025] In the figure: 1-lower base, 2-upper base, 3-PCBA1 board, 4-test board assembly MCU1, 5-plastic frame, 6-PCBA2 board, 7-dynamic image control board assembly MCU2, 8-digital tube light ring module, 9-LCD display module, 10-button, 11-USB power supply port. DETAILED DESCRIPTION

[0026] The dynamic image and video display device of the present invention includes a lower base 1, an upper base 2 arranged above the lower base 1, a PCBA1 board 3 arranged on the lower base 1, a test board component MCU1 4 arranged on the PCBA1 board 3, a plastic frame 5 snap-connected to the upper base 2 and located above the PCBA1 board 3, a PCBA2 board 6 arranged below the plastic frame 5, a dynamic image control board component MCU27 and a digital tube light ring module 8 arranged on the PCBA2 board 6, a liquid crystal display module 9 arranged above the plastic frame 5, and a button 10 arranged on the plastic frame 5 and directly in contact with the PCBA2 board 6. A USB power supply port 11 connected to the PCBA1 board 3 is formed between the upper base 2 and the lower base 1.

[0027] The upper base 2 is threaded or screwed to the lower base 1; the PCBA1 board 3 is provided with adhesive on the lower base. The plastic frame 5 is provided with connecting posts extending into the preset holes on the PCBA2 board 6, and the connecting posts are connected to the PCBA2 board 6 by thermal riveting. The liquid crystal display module 9 is composed of a TFT and a semi-transparent cover plate combined by OCA optical binding.

[0028] The dynamic image and video display method of the present invention is to transmit the dynamic image TFT to be displayed to the dynamic image control board component MCU27 through the USB power supply port 11 and the test board component MCU14 via the UART communication module, and then transmit it to the digital tube light ring module 8 and the liquid crystal display module 9 after image processing and data processing by the dynamic image control board component MCU27. Figure 1 shown.

[0029] Since the corresponding data are stored in different areas, there is a data delay when decompressing and reading the image, resulting in an unsmooth image switching. The above-mentioned dynamic image control board component MCU27 data processing adopts a double cache mechanism, including cache A and cache B respectively connected to the dynamic image control board component MCU27, and databases respectively connected to cache A and cache B. Cache A corresponds to the pic1 data that needs to be displayed and is connected to the dynamic image control board component MCU27, and cache B corresponds to the pic2 data that needs to be displayed and is connected to the dynamic image control board component MCU27. Cache A and cache B work alternately. Figure 3 As shown. Cache A and cache B work alternately. During data processing, cache A is used to store the pic1 data that needs to be displayed currently, and cache B is used to prepare the data of pic2 that needs to be displayed next. After the data in cache A is read and displayed, the MCU will switch to cache B for data reading, while cache A is used to prepare new data. Cache A and B work alternately. Ensure that there is always one cache providing data to drive the display, while the other cache is used for background data processing. This can avoid interference between data processing and data reading.

[0030] The above-mentioned dynamic image control board component MCU27 image processing is that the dynamic image TFT obtained by the dynamic image control board component MCU27 is subjected to picture format conversion, pixel matrix generation, functional area division, area importance evaluation and construction of color table, index matrix compression to obtain compressed data, and then the data is cached through block cache, cache area 1 and cache area 2. After the cache processing, the MCU reads and decodes to obtain the data for reading or extraction, and then the data is fed back to the liquid crystal display module 9 for LED dynamic display, such as Figure 2 shown.

[0031] Figure 2 In the image preprocessing process, the processing between image format conversion and pixel matrix generation and the processing between pixel matrix generation and functional area division are image preprocessing processes. The goal is to perform image format conversion and functional area division, and preliminarily provide basic data preparation for compression and partition storage. The specific implementation is as follows: The processing between image format conversion and pixel matrix generation is to perform image format conversion, convert the image format to bin format, extract the pixel matrix, and generate a pixel matrix (A(i, j)) from the converted image, where each element represents the color value of a pixel. The image is also subjected to histogram analysis to provide a reference for subsequent area segmentation. The processing between pixel matrix generation and functional area division automatically identifies functional areas based on image content (such as foreground, background, and edge) and generates sub-matrices.

[0032] Figure 2 The process between functional area division and regional importance evaluation, between functional area division and color table construction, between regional importance evaluation and index matrix compression, and between color table construction and index matrix compression is regional evaluation and index optimization. The goal is to improve the efficiency and quality of data compression through regional importance evaluation and color index optimization. Regional importance evaluation is performed between functional area division and regional importance evaluation to evaluate the importance of each divided area and determine the compression priority of each area. Important areas will use a low compression rate to retain more details, and low-scoring areas will be compressed more. Between functional area division and color table construction, a color index table is generated for each important area. Through indexing, the direct storage of color information is reduced and memory is saved. Between regional importance evaluation and index matrix compression, and between color table construction and index matrix compression, the index matrix is ​​compressed in the form of "quantity + index", that is, continuous identical color indexes are compressed into the form of "quantity + index".

[0033] Algorithm example:

[0034] Input: A = [[1, 1, 2], [2, 2, 3], [1, 3, 3]]

[0035] Compression results: [(2, 1), (1, 2)], [(2, 2), (1, 3)], [(1, 1), (2, 3)]

[0036] Figure 2 Data blocking and caching are performed between index matrix compression and block cache, between block cache and cache area 1, between block cache and cache area 2, and between cache area 1 and cache area 2.

[0037] The goal is to compress the image into blocks and store them in the double buffer for easy reading and decoding by MCU. According to the RAM capacity limit, the image is divided into blocks of size Y = floor (maximum image size / (RAM capacity * 2)) + A between the index matrix compression and the block cache. If the block size is an integer, A = 0, otherwise A = 1. The calculation results of the blocks are used between the block cache and cache area 1, and between the block cache and cache area 2, and two cache areas are generated: ① Cache area 1: Store the compressed data block length information X1 for quick reading during subsequent decoding; ② Cache area 2: Store specific compressed data X2. Between cache area 1 and cache area 2, each block of data is marked in cache area 1, and a unique mapping relationship is established with the data in cache area 2.

[0038] Figure 2 Data reprocessing and display are performed between buffer area 1 and MCU reading and decoding, between buffer area 2 and MCU reading and decoding, and between MCU reading and decoding and LED dynamic display.

[0039] The goal is to process the data through the MCU and display it on the LCD to complete the display of dynamic images. Between buffer area 1 and MCU reading and decoding, the MCU reads the data length information in buffer area 1 to locate the corresponding compressed data block. Between buffer area 2 and MCU reading and decoding, the corresponding data block is extracted from buffer area 2 and decoded, and the decoded index data is converted back to the pixel matrix and restored to partial image data. All decoded data blocks are spliced ​​at the original position to reconstruct the complete image.

[0040] The MCU reads and decodes the image data and the LED displays it dynamically. The UART communication module sends the decoded image data to the liquid crystal display module (LCD). The LCD display module receives the decoded data and refreshes the screen to display the current image. The user can control the image switching, play the next picture or adjust the display parameters (such as brightness and contrast) by pressing button 10. In the case of multiple pictures, the MCU automatically switches the display according to the set time interval to achieve the dynamic image playback effect.

[0041] The above MCU reading and decoding is to separate the H.264 hardware timing and the timing of reading memory, such as Figure 4-2 and Figure 4-3As shown. For frequent switching of multiple videos, if software decoding is used, it takes a long time, so hardware decoding is combined to switch multiple videos to reduce decoding time. Through software processing optimization, the connection problem during video conversion is solved.

[0042] Figure 4-2 The method is to separate the H.264 hardware timing and the timing of reading memory, adjust the original underlying code, and add protection code to the hardware decoding and memory reading threads respectively to ensure that the critical timing is not interrupted. Figure 4-3 It uses pictures as pseudo-videos to transition between videos. In the picture and text editing interface, design two video layers V1 and V2 and one picture layer P. During operation, play the first four pictures of V1 in P1, decode V1, and play V1. If there is an event to switch the video, stop playing V1, play the first four pictures of V2 in P, decode V2 and play it, and switch the two layers in a loop to ensure the reliability of operation.

[0043] Figure 5-7 As shown, in the liquid crystal display module 9, the cover plate adopts a composite cover plate (PMMA+PC), which can ensure a certain surface hardness and meet a certain impact resistance compared to a glass cover plate of the same thickness. A semi-transparent cover plate is adopted, which has better effect in the anti-UV light experiment than a conventional cover plate. The semi-transparent cover plate and the TFT are fixed together in the form of OCA optical binding to achieve an overall integrated black effect. The PCBA1 board 3 and the lower base 1 are fixed together on both sides by 3M. The plastic frame 5 reserves a connecting column during the design, and the PCBA2 board 6 is subsequently fixed by hot riveting. The USB power supply port 11 adopts conventional USB power supply. The upper base 2 and the lower base 1 are locked together by screws and nuts, which is convenient for subsequent disassembly, debugging and replacement of components. The button 10 is used for function selection.

[0044] Through the research on image compression and data transmission methods, we can meet the needs, realize dynamic display of images and video switching, achieve high portability and compatibility, reduce solution design costs, and improve product competitiveness and market share.

[0045] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A dynamic image and video display device, characterized in that: The dynamic image and video display device includes a lower base, an upper base arranged above the lower base, a PCBA1 board arranged on the lower base, a test board component MCU1 arranged on the PCBA1 board, a plastic frame snap-connected to the upper base and located above the PCBA1 board, a PCBA2 board arranged below the plastic frame, a dynamic image control board component MCU2 and a digital tube light ring module arranged on the PCBA2 board, a liquid crystal display module arranged above the plastic frame, and a button arranged on the plastic frame and in direct contact with the PCBA2 board. A USB power supply port connected to the PCBA1 board is formed between the upper base and the lower base.

2. A dynamic image and video display device as claimed in claim 1, characterized in that: The upper base is threadedly connected or screwed to the lower base; the PCBA1 board adhesive is arranged on the lower base.

3. A dynamic image and video display device as claimed in claim 1, characterized in that: The plastic frame is provided with connecting posts extending into preset holes on the PCBA2 board, and the connecting posts are connected to the PCBA2 board by thermal riveting.

4. A dynamic image and video display device as claimed in claim 1, characterized in that: The liquid crystal display module is composed of a TFT and a semi-transparent cover plate combined by OCA optical bonding.

5. A method for displaying dynamic images and videos, using a dynamic image and video display device as claimed in any one of claims 1 to 4, characterized in that: The dynamic image and video display method is to transmit the dynamic image TFT to be displayed to the dynamic image control board component MCU2 through the USB power supply port and the test board component MCU1 via the UART communication module, and then transmit it to the digital tube light ring module and the liquid crystal display module after image processing and data processing by the dynamic image control board component MCU2.

6. A method for displaying dynamic images and videos as claimed in claim 5, characterized in that: The dynamic image control board component MCU2 adopts a dual cache mechanism for data processing, including cache A and cache B respectively connected to the dynamic image control board component MCU2, and databases respectively connected to the cache A and cache B. The cache A corresponds to the pic1 data that needs to be displayed and is connected to the dynamic image control board component MCU2, and the cache B corresponds to the pic2 data that needs to be displayed and is connected to the dynamic image control board component MCU2. The cache A and cache B work alternately.

7. A method for displaying dynamic images and videos as claimed in claim 6, characterized in that: The cache A and cache B work alternately. During the data processing, cache A is used to store the pic1 data that needs to be displayed currently, and cache B is used to prepare the data of the next pic2 that needs to be displayed. After the data in cache A is read and displayed, the dynamic image control board component MCU2 will switch to cache B for data reading, and cache A is used to prepare new data.

8. A method for displaying dynamic images and videos as claimed in claim 5, characterized in that: The image processing of the dynamic image control board component MCU2 is as follows: the dynamic image TFT obtained by the dynamic image control board component MCU2 is subjected to picture format conversion, pixel matrix generation, functional area division, area importance evaluation and construction of color table, index matrix compression to obtain compressed data, and then data caching is performed through block caching, cache area 1 and cache area 2. After caching, the data is read and decoded by the MCU to obtain data for reading or extraction, and then the data is fed back to the liquid crystal display module for LED dynamic display.

9. A method for displaying dynamic images and videos as claimed in claim 8, characterized in that: The MCU reads and decodes the H.264 hardware timing and the timing of reading the memory independently.

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