Decoding method and device, electronic equipment and storage medium

Abstract

The invention relates to a decoding method and device, electronic equipment and a storage medium. The decoding method comprises the following steps: acquiring a current decoding interval corresponding to a current syntax element, and a first multi-hypothesis probability and a second multi-hypothesis probability of the current syntax element; based on the first multi-hypothesis probability, the second multi-hypothesis probability and an overflow state of a predetermined register, determining a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval; and performing arithmetic decoding on the current syntax element based on the value of the current code stream and the minimum possible symbol interval to obtain a decoding result of the current syntax element. According to the decoding method and device disclosed by the invention, the decoding efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of video technology. More specifically, the present disclosure relates to a decoding method, device, electronic device and storage medium. Background Art

[0002] Various electronic devices (e.g., digital televisions, laptop or desktop computers, tablet computers, digital cameras, digital recording devices, digital media players, video game consoles, smart phones, video teleconferencing devices, video streaming devices, etc.) support digital video. Electronic devices send and receive or otherwise transmit digital video data through a communication network, and / or store digital video data on a storage device. Due to the limited bandwidth capacity of the communication network and the limited storage resources of the storage device, before the video data is transmitted or stored, the video data can be compressed using a video codec according to one or more video codec standards. For example, video codec standards include general video codec (VVC), joint exploration test model (JEM), high efficiency video codec (HEVC / H.265), advanced video codec (AVC / H.264), moving picture expert group (MPEG) codec, etc. Video codecs generally use prediction methods (e.g., inter-frame prediction, intra-frame prediction, etc.) that utilize the inherent redundancy in video data. Video codecs are intended to compress video data into a form that uses a lower bit rate while avoiding or minimizing the degradation of video quality.

[0003] Universal video codec is the latest generation of international video codec standards. It can improve the compression rate by 50% compared with the previous generation HEVC at the same quality. But at the same time, its computational complexity is very high, especially when decoding on the client side. Universal video codec is mainly divided into two main modules, arithmetic decoding and reconstruction. The work of arithmetic decoding is to convert the code stream into syntax elements, and the work of reconstruction is to restore the syntax elements into images. When the probability of occurrence of each symbol is given, arithmetic decoding is an optimal encoding method. It encodes a string of characters to a point in the interval [0,1], and determines the string corresponding to this point according to the interval in which this point is located. Since arithmetic decoding is strictly serial and has low computational efficiency, and it accounts for a high proportion of the entire decoder, it is still necessary to optimize it. Summary of the invention

[0004] An exemplary embodiment of the present disclosure is to provide a decoding method and apparatus to at least solve the decoding problems in the related art, but may not solve any of the above problems.

[0005] According to an exemplary embodiment of the present disclosure, a decoding method is provided, comprising: obtaining a current decoding interval corresponding to a current syntax element, a first multiple hypothesis probability and a second multiple hypothesis probability of the current syntax element; determining a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and an overflow state of a predetermined register; and performing arithmetic decoding on the current syntax element based on a value of a current code stream and the minimum possible symbol interval to obtain a decoding result of the current syntax element.

[0006] Optionally, determining the minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and the overflow status of a predetermined register may include: determining the probability of the minimum possible symbol corresponding to the current syntax element based on the first multiple hypothesis probability and the second multiple hypothesis probability; updating the probability of the minimum possible symbol based on the overflow status; and determining the minimum possible symbol interval based on the current decoding interval and the updated probability of the minimum possible symbol.

[0007] Optionally, determining the probability of the minimum possible symbol corresponding to the current syntax element based on the first multiple-hypothesis probability and the second multiple-hypothesis probability may include: respectively shifting the binary bits corresponding to the first multiple-hypothesis probability and the second multiple-hypothesis probability left by a first predetermined bit; performing an AND operation on the left-shifted binary bits corresponding to the first multiple-hypothesis probability and the second multiple-hypothesis probability; and right shifting the result obtained by the AND operation by a second predetermined bit to obtain the probability of the minimum possible symbol, wherein the result obtained by the AND operation is stored in the predetermined register.

[0008] Optionally, the updating of the probability of the minimum possible symbol based on the overflow state may include: by using a predetermined condition to select an instruction, based on the overflow state being overflow, bitwise inverting the probability of the minimum possible symbol; by using the predetermined condition to select an instruction, based on the overflow state being no overflow, keeping the probability of the minimum possible symbol unchanged.

[0009] Optionally, the arithmetically decoding the current syntax element based on the value of the current code stream and the minimum possible symbol interval may include: determining that the symbol obtained by arithmetically decoding the current syntax element is a minimum possible symbol based on the value of the current code stream being located in the minimum possible symbol interval; and determining that the symbol obtained by arithmetically decoding the current syntax element is a maximum possible symbol based on the value of the current code stream not being located in the minimum possible symbol interval.

[0010] Optionally, the decoding method may further include: based on the decoding result, updating the current decoding interval to use the updated current decoding interval for decoding of the next syntax element.

[0011] Optionally, the decoding method may further include: updating the value of the current code stream based on the value of the current code stream and the decoding result, so as to use the updated value of the current code stream for decoding of the next syntax element.

[0012] Optionally, the decoding method may further include: based on the decoding result, updating the first multiple hypothesis probability and the second multiple hypothesis probability in parallel, so as to use the updated first multiple hypothesis probability and the updated second multiple hypothesis probability for decoding of the next syntax element.

[0013] Optionally, updating the first multiple-hypothesis probability and the second multiple-hypothesis probability in parallel based on the decoding result may include: updating the first multiple-hypothesis probability based on the decoding result, a first probability update rate and the first multiple-hypothesis probability; updating the second multiple-hypothesis probability based on the decoding result, a second probability update rate and the second multiple-hypothesis probability, wherein updating the first multiple-hypothesis probability and updating the second multiple-hypothesis probability are performed in parallel.

[0014] Optionally, updating the first multi-hypothesis probability and the second multi-hypothesis probability in parallel based on the decoding result may include: combining the first multi-hypothesis probability and the second multi-hypothesis probability into a probability vector, and combining the first probability update rate and the second probability update rate into a probability update rate vector; and updating the probability vector based on the decoding result, the probability update rate vector and the probability vector.

[0015] Optionally, updating the probability vector based on the decoding result, the probability update rate vector, and the probability vector may include: obtaining a predetermined first constant and a predetermined second constant, and combining the predetermined first constant and the predetermined second constant to form a constant vector; determining a product vector obtained by performing a cross product operation on the constant vector and the probability vector; determining a difference vector obtained by subtracting the product vector from the probability vector; and determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result.

[0016] Optionally, determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result may include: determining a mask result of the decoding result; obtaining a predetermined third constant, and determining the product of the predetermined third constant and the mask result; determining a result vector obtained by performing a cross product operation on the difference vector and the probability update rate vector; and performing a sum operation on the result vector and the product, and using the sum vector obtained by the sum operation as the updated probability vector.

[0017] Optionally, determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result may include: when the decoding result is a first value, taking a product vector of the difference vector and the probability update rate vector as the updated probability vector; when the decoding result is a second value, obtaining a predetermined third constant, and taking a sum vector obtained by performing a cross product operation on the difference vector and the probability update rate vector and performing a sum operation on the predetermined third constant as the updated probability vector.

[0018] Optionally, the first predetermined bit may be determined based on a difference between the number of bits of the predetermined register and the number of bits of the first multiple hypothesis probability or the number of bits of the second multiple hypothesis probability, and the second predetermined bit may be determined based on the first predetermined bit and the third predetermined bit.

[0019] According to an exemplary embodiment of the present disclosure, a decoding device is provided, comprising: a parameter acquisition unit, configured to acquire a current decoding interval corresponding to a current syntax element, a first multiple hypothesis probability and a second multiple hypothesis probability of the current syntax element; a corresponding interval determination unit, configured to determine a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and an overflow state of a predetermined register; and a decoding unit, configured to perform arithmetic decoding on the current syntax element based on a value of a current code stream and the minimum possible symbol interval to obtain a decoding result of the current syntax element.

[0020] Optionally, the corresponding interval determination unit can be configured to: determine the probability that the current syntax element corresponds to the minimum possible symbol based on the first multiple hypothesis probability and the second multiple hypothesis probability; update the probability of the minimum possible symbol based on the overflow state; and determine the minimum possible symbol interval based on the current decoding interval and the updated probability of the minimum possible symbol.

[0021] Optionally, the corresponding interval determination unit can be configured to: shift the binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability left by a first predetermined bit respectively; perform an AND operation on the left-shifted binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability; shift the result obtained by the AND operation right by a second predetermined bit to obtain the probability of the minimum possible symbol, wherein the result obtained by the AND operation is stored in the predetermined register.

[0022] Optionally, the corresponding interval determination unit may be configured to: by using a predetermined condition to select an instruction, based on the overflow state being overflow, bitwise invert the probability of the minimum possible symbol; by using the predetermined condition to select an instruction, based on the overflow state being no overflow, keep the probability of the minimum possible symbol unchanged.

[0023] Optionally, the decoding unit may be configured to: determine that the symbol obtained by arithmetically decoding the current syntax element is the minimum possible symbol based on the value of the current code stream being located in the minimum possible symbol interval; and determine that the symbol obtained by arithmetically decoding the current syntax element is the maximum possible symbol based on the value of the current code stream not being located in the minimum possible symbol interval.

[0024] Optionally, the decoding device may further include: a decoding interval updating unit configured to update the current decoding interval based on the decoding result, so as to use the updated current decoding interval for decoding of the next syntax element.

[0025] Optionally, the decoding device may further include: an element updating unit configured to update the value of the current code stream based on the value of the current code stream and the decoding result, so as to use the updated value of the current code stream for decoding of the next syntax element.

[0026] Optionally, the decoding device may further include: a probability updating unit configured to update the first multiple hypothesis probability and the second multiple hypothesis probability in parallel based on the decoding result, so as to use the updated first multiple hypothesis probability and the second multiple hypothesis probability for decoding of the next syntax element.

[0027] Optionally, the probability update unit can be configured to: update the first multiple hypothesis probability based on the decoding result, the first probability update rate and the first multiple hypothesis probability; update the second multiple hypothesis probability based on the decoding result, the second probability update rate and the second multiple hypothesis probability, wherein the updating of the first multiple hypothesis probability and the updating of the second multiple hypothesis probability are performed in parallel.

[0028] Optionally, the probability update unit can be configured to: combine the first multi-hypothesis probability and the second multi-hypothesis probability into a probability vector, and combine the first probability update rate and the second probability update rate into a probability update rate vector; and update the probability vector based on the decoding result, the probability update rate vector, and the probability vector.

[0029] Optionally, the probability update unit can be configured to: obtain a predetermined first constant and a predetermined second constant, and combine the predetermined first constant and the predetermined second constant to form a constant vector; determine a product vector obtained by performing a cross product operation on the constant vector and the probability vector; determine a difference vector obtained by subtracting the product vector from the probability vector; and determine an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result.

[0030] Optionally, the probability update unit can be configured to: determine a mask result of the decoding result; obtain a predetermined third constant, and determine the product of the predetermined third constant and the mask result; determine a result vector obtained by performing a cross product operation on the difference vector and the probability update rate vector; perform a sum operation on the result vector and the product, and use the sum vector obtained by the sum operation as an updated probability vector.

[0031] Optionally, the probability update unit can be configured to: when the decoding result is a first value, use the product vector of the difference vector and the probability update rate vector as an updated probability vector; when the decoding result is a second value, obtain a predetermined third constant, and use the sum vector obtained by performing a cross product operation on the difference vector and the probability update rate vector and performing a sum operation on the predetermined third constant as an updated probability vector.

[0032] Optionally, the first predetermined bit may be determined based on a difference between the number of bits of the predetermined register and the number of bits of the first multiple hypothesis probability or the number of bits of the second multiple hypothesis probability, and the second predetermined bit may be determined based on the first predetermined bit and the third predetermined bit.

[0033] According to an exemplary embodiment of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement a decoding method according to an exemplary embodiment of the present disclosure.

[0034] According to an exemplary embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor of an electronic device, the electronic device performs a decoding method according to an exemplary embodiment of the present disclosure.

[0035] According to an exemplary embodiment of the present disclosure, a computer program product is provided, including a computer program / instruction. When the computer program / instruction is executed by a processor, a decoding method according to an exemplary embodiment of the present disclosure is implemented.

[0036] According to an exemplary embodiment of the present disclosure, a computer program product is provided, having instructions for storing a bit stream, wherein the bit stream includes video data generated by a decoding method according to an exemplary embodiment of the present disclosure.

[0037] According to an exemplary embodiment of the present disclosure, there is provided a method for generating a bit stream, including: generating the bit stream according to the decoding method as described above.

[0038] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:

[0039] By determining the minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and the overflow state of the predetermined register, the decoding efficiency is improved based on the register characteristics.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0042] Figure 1 A block diagram is shown of an exemplary system 10 for encoding and decoding video blocks in parallel, according to some embodiments of the present disclosure.

[0043] Figure 2 A block diagram of an exemplary video encoder 20 is shown, in accordance with some embodiments described herein.

[0044] Figure 3 A block diagram of an exemplary video decoder 30 is shown according to some embodiments of the present application.

[0045] Figure 4 A flowchart of a decoding method according to an exemplary embodiment of the present disclosure is shown.

[0046] Figure 5 A block diagram of a decoding device according to an exemplary embodiment of the present disclosure is shown.

[0047] Figure 6 is a block diagram of an electronic device 600 according to an exemplary embodiment of the present disclosure.

[0048] Figure 7 A diagram showing a computing environment coupled with a user interface according to some implementations of the present disclosure. DETAILED DESCRIPTION

[0049] Reference will now be made in detail to specific embodiments, examples of which are shown in the accompanying drawings. In the following detailed description, a number of non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, various alternatives may be used without departing from the scope of the claims, and the subject matter may be practiced without these specific details. For example, the subject matter presented herein may be implemented on many types of electronic devices having digital video capabilities.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the drawings are used to distinguish objects, but not to describe any specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those shown in the drawings or described in the present disclosure.

[0051] Figure 1 is a block diagram illustrating an exemplary system 10 for encoding and decoding video blocks in parallel according to some embodiments of the present disclosure. Figure 1 As shown in , system 10 includes a source device 12 that generates and encodes video data to be later decoded by a target device 14. Source device 12 and target device 14 may include any of a wide variety of electronic devices, including cloud servers, server computers, desktop or laptop computers, tablet computers, smart phones, set-top boxes, digital televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc. In some implementations, source device 12 and target device 14 are equipped with wireless communication capabilities.

[0052] In some implementations, target device 14 may receive the encoded video data to be decoded via link 16. Link 16 may include any type of communication medium or device capable of moving the encoded video data from source device 12 to target device 14.

[0053] In some other embodiments, the encoded video data may be sent from the output interface 22 to the storage device 32. The encoded video data in the storage device 32 may then be accessed by the target device 14 via the input interface 28.

[0054] like Figure 1 , source device 12 includes a video source 18, a video encoder 20, and an output interface 22. Video source 18 may include sources such as, or a combination of such sources: a video capture device (e.g., a camera), a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and / or a computer graphics system for generating computer graphics data as source video.

[0055] The captured, pre-captured, or computer-generated video may be encoded by video encoder 20. The encoded video data may be sent directly to target device 14 via output interface 22 of source device 12. The encoded video data may also (or alternatively) be stored on storage device 32 for later access by target device 14 or other devices for decoding and / or playback.

[0056] Target device 14 includes input interface 28, video decoder 30, and display device 34. Input interface 28 may include a receiver and / or a modem and receives encoded video data via link 16. The encoded video data transmitted via link 16 or provided on storage device 32 may include various syntax elements generated by video encoder 20 for use by video decoder 30 in decoding the video data. Such syntax elements may be included within the encoded video data sent over a communication medium, stored on a storage medium, or stored on a file server.

[0057] The video encoder 20 and the video decoder 30 can operate according to a proprietary standard or an industry standard (e.g., VVC, HEVC, Part 10 of MPEG-4, AVC) or an extension of such a standard. It should be understood that the present application is not limited to a specific video encoding / decoding standard and can be applied to other video encoding / decoding standards. It is generally believed that the video encoder 20 of the source device 12 can be configured to encode the video data according to any of these current standards or future standards. Similarly, it is also generally believed that the video decoder 30 of the target device 14 can be configured to decode the video data according to any of these current standards or future standards.

[0058] The video encoder 20 and the video decoder 30 may be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic devices, software, hardware, firmware, or any combination thereof. When partially implemented in software, the electronic device may store instructions for the software in a suitable non-transitory computer-readable medium, and use one or more processors to execute the instructions in the hardware to perform the video encoding / decoding operations disclosed in the present disclosure. Each of the video encoder 20 and the video decoder 30 may be included in one or more encoders or decoders, and either of the encoders or decoders may be integrated as part of a combined encoder / decoder (CODEC) in the corresponding device.

[0059] Figure 2 is a block diagram illustrating an exemplary video encoder 20 according to some embodiments described in the present application. The video encoder 20 can perform intra-frame prediction coding and inter-frame prediction coding on video blocks within a video frame. Intra-frame prediction coding relies on spatial prediction to reduce or remove spatial redundancy in video data within a given video frame or picture. Inter-frame prediction coding relies on temporal prediction to reduce or remove temporal redundancy in video data within adjacent video frames or pictures of a video sequence. It should be noted that in the field of video coding and decoding, the term "frame" can be used as a synonym for the term "image" or "picture".

[0060] like Figure 2 As shown in , the video encoder 20 includes a video data memory 40, a prediction processing unit 41, a decoded picture buffer (DPB) 64, an adder 50, a transform processing unit 52, a quantization unit 54, and an entropy coding unit 56. The prediction processing unit 41 further includes a motion estimation unit 42, a motion compensation unit 44, a segmentation unit 45, an intra-frame prediction processing unit 46, and an intra-frame block copy (BC) unit 48. In some embodiments, the video encoder 20 also includes an inverse quantization unit 58, an inverse transform processing unit 60, and an adder 62 for video block reconstruction. A loop filter 63 such as a deblocking filter can be located between the adder 62 and the DPB 64 to filter the block boundary to remove the block effect from the reconstructed video. In addition to the deblocking filter, another loop filter (e.g., a sample adaptive offset (SAO) filter, a cross-component sample adaptive offset (CCSAO) filter, and / or an adaptive loop filter (ALF)) can also be used to filter the output of the adder 62. In some examples, the loop filter may be omitted, and the decoded video blocks may be provided directly by adder 62 to DPB 64. Video encoder 20 may take the form of a fixed or programmable hardware unit, or may be distributed among one or more of the illustrated fixed or programmable hardware units.

[0061] Video data memory 40 may store video data to be encoded by components of video encoder 20. Figure 1 Video source 18 is shown obtaining video data in video data memory 40. DPB 64 is a buffer that stores reference video data (eg, reference frames or pictures) for use by video encoder 20 in encoding the video data (eg, in intra or inter prediction coding modes).

[0062] like Figure 2 As shown in , after receiving the video data, the segmentation unit 45 within the prediction processing unit 41 segments the video data into video blocks. This segmentation may also include segmenting the video frame into strips, tiles (e.g., a set of video blocks), or other larger coding units (CUs) according to a predefined splitting structure associated with the video data, such as a quadtree (QT) structure. It should be noted that the terms "block" or "video block" used herein may be a portion of a frame or picture, in particular a rectangular (square or non-square) portion. With reference to, for example, HEVC and VVC, a block or video block may be or correspond to a coding tree unit (CTU), a CU, a prediction unit (PU), or a transform unit (TU) and / or may be or correspond to a corresponding block (e.g., a coding tree block (CTB), a coding block (CB), a prediction block (PB), or a transform block (TB)) and / or a sub-block.

[0063] The prediction processing unit 41 may select one of a plurality of feasible prediction coding modes for the current video block based on the error results (e.g., coding rate and distortion level), such as one of one or more inter-frame prediction coding modes in a plurality of intra-frame prediction coding modes. The prediction processing unit 41 may provide the resulting intra-frame prediction coding block or inter-frame prediction coding block to the adder 50 to generate a residual block, and to the adder 62 to reconstruct the coding block for subsequent use as part of a reference frame. The prediction processing unit 41 also provides syntax elements (e.g., motion vectors, intra-frame mode indicators, partition information, and other such syntax information) to the entropy coding unit 56.

[0064] To select an appropriate intra-prediction coding mode for the current video block, intra-prediction processing unit 46 within prediction processing unit 41 may perform intra-prediction coding of the current video block in relation to one or more neighboring blocks in the same frame as the current block to be encoded to provide spatial prediction. Motion estimation unit 42 and motion compensation unit 44 within prediction processing unit 41 may perform inter-prediction coding of the current video block in relation to one or more prediction blocks in one or more reference frames to provide temporal prediction. Video encoder 20 may perform multiple encoding passes, for example, to select an appropriate coding mode for each block of video data.

[0065] In some embodiments, motion estimation unit 42 determines an inter-prediction mode for a current video frame by generating a motion vector according to a predetermined pattern within a sequence of video frames, the motion vector indicating the displacement of a video block within the current video frame relative to a prediction block within a reference video frame. Motion estimation performed by motion estimation unit 42 is the process of generating a motion vector that estimates the motion of a video block. For example, a motion vector may indicate the displacement of a video block within a current video frame or picture relative to a prediction block within a reference frame associated with a current block being encoded within the current frame. The predetermined pattern may designate a video frame in a sequence as a P frame or a B frame. Intra BC unit 48 may determine a vector (e.g., a block vector) for intra BC coding in a manner similar to the motion vector determined by motion estimation unit 42 for inter prediction, or may utilize motion estimation unit 42 to determine a block vector.

[0066] Regardless of whether the prediction block is from the same frame according to intra-frame prediction or from a different frame according to inter-frame prediction, the video encoder 20 can form a residual video block by subtracting the pixel values ​​of the prediction block from the pixel values ​​of the current video block being encoded. The pixel difference values ​​forming the residual video block may include both luma component differences and chroma component differences.

[0067] Intra-prediction processing unit 46 may encode the current block using various intra-prediction modes, for example, during separate encoding passes, and intra-prediction processing unit 46 (or, in some examples, mode selection unit) may select an appropriate intra-prediction mode to use from the tested intra-prediction modes. Intra-prediction processing unit 46 may provide information indicating the intra-prediction mode selected for the block to entropy encoding unit 56. Entropy encoding unit 56 may encode the information indicating the selected intra-prediction mode into the bitstream.

[0068] After prediction processing unit 41 determines a prediction block for the current video block via inter-prediction or intra-prediction, adder 50 forms a residual video block by subtracting the prediction block from the current video block. The residual video data in the residual block may be included in one or more TUs and provided to transform processing unit 52. Transform processing unit 52 transforms the residual video data into residual transform coefficients using a transform (e.g., a discrete cosine transform (DCT) or a conceptually similar transform).

[0069] The transform processing unit 52 may send the resulting transform coefficients to a quantization unit 54. The quantization unit 54 quantizes the transform coefficients to further reduce the bit rate. The quantization process may also reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, the quantization unit 54 may then perform a scan on the matrix including the quantized transform coefficients. Alternatively, the entropy coding unit 56 may perform the scan.

[0070] After quantization, entropy coding unit 56 entropy encodes the quantized transform coefficients into a video bitstream using, for example, context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy coding method or technique. The encoded bitstream may then be sent to a video bitstream such as a Figure 1 The video decoder 30 shown, or archived as Figure 1 The video frame may be stored in storage device 32 as shown for later transmission to or retrieval by video decoder 30. Entropy encoding unit 56 may also entropy encode motion vectors and other syntax elements for the current video frame being encoded.

[0071] Inverse quantization unit 58 and inverse transform processing unit 60 apply inverse quantization and inverse transform, respectively, to reconstruct the residual video block in the pixel domain for use in generating reference blocks for predicting other video blocks. As noted above, motion compensation unit 44 may generate a motion compensated prediction block from one or more reference blocks of a frame stored in DPB 64. Motion compensation unit 44 may also apply one or more interpolation filters to the prediction block to calculate sub-integer pixel values ​​for use in motion estimation.

[0072] Adder 62 adds the reconstructed residual block to the motion compensated prediction block generated by motion compensation unit 44 to generate a reference block for storage in DPB 64. The reference block may then be used as a prediction block by intra BC unit 48, motion estimation unit 42, and motion compensation unit 44 to inter-predict another video block in a subsequent video frame.

[0073] Figure 3 1 is a block diagram showing an exemplary video decoder 30 according to some embodiments of the present application. The video decoder 30 includes a video data memory 79, an entropy decoding unit 80, a prediction processing unit 81, an inverse quantization unit 86, an inverse transform processing unit 88, an adder 90, and a DPB 92. The prediction processing unit 81 further includes a motion compensation unit 82, an intra-frame prediction unit 84, and an intra-frame BC unit 85. The video decoder 30 may perform the above-mentioned Figure 2 The encoding process is substantially the inverse of the decoding process described with respect to video encoder 20. For example, motion compensation unit 82 may generate prediction data based on motion vectors received from entropy decoding unit 80, and intra-prediction unit 84 may generate prediction data based on intra-prediction mode indicators received from entropy decoding unit 80.

[0074] In some examples, embodiments of the present disclosure may be dispersed in one or more of the units of the video decoder 30. For example, the intra BC unit 85 may perform embodiments of the present application alone or in combination with other units of the video decoder 30, such as the motion compensation unit 82, the intra prediction unit 84, and the entropy decoding unit 80. In some examples, the video decoder 30 may not include the intra BC unit 85, and the functions of the intra BC unit 85 may be performed by other components of the prediction processing unit 81, such as the motion compensation unit 82.

[0075] Video data memory 79 may store video data, such as an encoded video bitstream, to be decoded by other components of video decoder 30. Video data stored in video data memory 79 may be obtained, for example, from storage device 32, from a local video source (e.g., a camera), via wired or wireless network communication of video data, or by accessing a physical data storage medium (e.g., a flash drive or hard disk).

[0076] See

[0077] During the decoding process, the video decoder 30 receives an encoded video bitstream representing video blocks of an encoded video frame and associated syntax elements. The entropy decoding unit 80 of the video decoder 30 entropy decodes the bitstream to generate quantization coefficients, motion vectors or intra-frame prediction mode indicators, and other syntax elements. The entropy decoding unit 80 then forwards the motion vectors or intra-frame prediction mode indicators, and other syntax elements to the prediction processing unit 81.

[0078] When a video frame is encoded as an intra-prediction coded (I) frame or for intra-coded prediction blocks in other types of frames, the intra-prediction unit 84 of the prediction processing unit 81 can generate prediction data for a video block of the current video frame based on the intra-prediction mode transmitted by the signal and reference data from a previously decoded block of the current frame.

[0079] When the video frame is encoded as an inter-frame prediction coding (i.e., B or P) frame, the motion compensation unit 82 of the prediction processing unit 81 generates one or more prediction blocks for the video block of the current video frame based on the motion vector and other syntax elements received from the entropy decoding unit 80. Each of the prediction blocks can be generated from a reference frame in one of the reference frame lists. The video decoder 30 can construct the reference frame lists, i.e., List 0 and List 1, based on the reference frames stored in the DPB 92 using a default construction technique.

[0080] In some examples, when a video block is encoded according to the intra BC mode described herein, intra BC unit 85 of prediction processing unit 81 generates a prediction block for the current video block based on the block vector and other syntax elements received from entropy decoding unit 80. The prediction block may be within a reconstructed region of the same picture as the current video block as defined by video encoder 20.

[0081] Motion compensation unit 82 and / or intra BC unit 85 determine prediction information for a video block of the current video frame by parsing motion vectors and other syntax elements, and then use the prediction information to generate a prediction block for the current video block being decoded.

[0082] Motion compensation unit 82 may also perform interpolation using interpolation filters as used by video encoder 20 during encoding of the video blocks to calculate interpolated values ​​for sub-integer pixels of reference blocks. In this case, motion compensation unit 82 may determine the interpolation filters used by video encoder 20 based on the received syntax elements and use these interpolation filters to produce the prediction blocks.

[0083] Inverse quantization unit 86 inverse quantizes the quantized transform coefficients provided in the bitstream and entropy decoded by entropy decoding unit 80, using the same quantization parameters calculated by video encoder 20 for each video block in the video frame to determine the degree of quantization. Inverse transform processing unit 88 applies an inverse transform (e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process) to the transform coefficients to reconstruct the residual block in the pixel domain.

[0084] After the motion compensation unit 82 or the intra BC unit 85 generates a prediction block for the current video block based on the vector and other syntax elements, the adder 90 reconstructs the decoded video block for the current video block by adding the residual block from the inverse transform processing unit 88 to the corresponding prediction block generated by the motion compensation unit 82 and the intra BC unit 85. A loop filter 91 (e.g., a deblocking filter, an SAO filter, a CCSAO filter, and / or an ALF) may be located between the adder 90 and the DPB 92 to further process the decoded video block. In some examples, the loop filter 91 may be omitted, and the decoded video block may be provided directly to the DPB 92 by the adder 90. The decoded video blocks in a given frame are then stored in the DPB 92, which stores reference frames for subsequent motion compensation of the next video block. The DPB 92 or a memory device separate from the DPB 92 may also store the decoded video for later presentation on a display device (e.g., Figure 1 on a display device 34).

[0085] Figure 4 A flowchart of a decoding method according to an exemplary embodiment of the present disclosure is shown. For example, when used to perform arithmetic decoding on a video, the video is divided into a plurality of syntax elements, and the decoding method is used to perform arithmetic decoding on each of the plurality of syntax elements in turn.

[0086] Figure 4 The decoding method in can be used to perform arithmetic decoding on the arithmetic coding result. Arithmetic coding encodes the entire input data into a decimal n satisfying (0.0≤n<1.0), while arithmetic decoding converts this decimal n back to the original input data. The basic idea of ​​arithmetic coding is to encode the entire input data into a decimal n satisfying (0.0≤n<1.0). The encoding process involves dividing the input data into a series of intervals, each of which corresponds to the probability of a character or character combination.

[0087] For example, for the characters AABABCABAB, according to the number of times A, B, and C appear, we know that P(A) = 0.5, P(B) = 0.4, and P(C) = 0.1. First, arithmetic coding will divide ABC into intervals in the initial coding interval [0,1), so the three intervals A: [0, 0.5), B: [0.5, 0.9), and C: [0.9, 1) will be obtained first. Encoding is performed based on the above intervals and the character sequence order (from left to right) at the beginning of A, B, and C. After each update of the intervals of A, B, and C, a new target interval is selected based on whether the next character is A, B, or C.

[0088] (1) The first character of the sequence AABABCABAB is A, so the interval [0,0.5) of A is selected as the new target interval (i.e., encoding interval). The new target interval (i.e., encoding interval) is divided according to the probability of ABC: A: [0,0.25), B: [0.25,0.45), C: [0.45,0.5), and the intervals of A, B, and C are updated once. Then, the next step can be carried out. Since the next character is A, A: [0,0.25) should be selected as the new target interval (i.e., encoding interval).

[0089] (2) The second character of the sequence AABABCABAB is A, so the interval [0,0.25) of A is selected as the new target interval (i.e., the coding interval). The new target interval (i.e., the coding interval) is further divided according to the probability ratio of ABC: A: [0,0.125), B: [0.125,0.225), C: [0.225,0.25).

[0090] (3) The third character of the sequence AABABCABAB is B, so the interval [0.125, 0.225) of B is selected as the new target interval (i.e., coding interval). The new target interval (i.e., coding interval) is further divided according to the probability ratio of ABC: A: [0.125, 0.175), B: [0.175, 0.215), C: [0.215, 0.225). And so on, omitting the intermediate steps, (10) until the tenth character of the sequence AABABCABAB is B, then the interval [0.1686, 0.16868) of B is selected as the new target interval (i.e., coding interval). For the new target interval, divide it according to the probability ratio of ABC: A: [0.1686, 0.16864), B: [0.16864, 0.168672), C: [0.168672, 0.16868), then all characters are encoded. The final interval is the encoding interval [0.16864, 0.168672) where the 10th character is B. Finally, select any specific decimal that satisfies the encoding interval [0.16864, 0.168672) as the encoding result. The decoding interval of a syntax element in the decoding process corresponds to the encoding interval of the syntax element in the encoding process.

[0091] Reference Figure 4 In step S401, the current decoding interval corresponding to the current syntax element, the first multiple hypothesis probability and the second multiple hypothesis probability of the current syntax element are obtained. In the general video codec, two multiple hypothesis probabilities p0 and p1 are designed. For example, the average value of the two multiple hypothesis probabilities p0 and p1 of the current syntax element can be used as the final probability value of the current syntax element. The current decoding interval can be determined based on the decoding interval of the previous syntax element of the current syntax element. The first multiple hypothesis probability and the second multiple hypothesis probability of the current syntax element can be determined based on the first multiple hypothesis probability and the second multiple hypothesis probability of the previous syntax element of the current syntax element.

[0092] In an exemplary embodiment of the present disclosure, each syntax element has two multiple-hypothesis probabilities: a first multiple-hypothesis probability and a second multiple-hypothesis probability (p0, p1).

[0093] Using one fixed adaptation parameter for all syntax elements may not be optimal due to their different statistical properties. On the other hand, it has been demonstrated in some scientific studies that better estimation accuracy can be achieved by using multiple probability estimators compared to a single estimator. Therefore, a multi-hypothesis probability estimation scheme is applied in the CABAC design of a general video codec, where two different adaptation parameters α0 and α1 corresponding to one slow and one fast for probability adaptation are utilized. In this way, two different probabilities can be calculated for each binary bit using two adaptation parameters, which are then averaged to generate the final probability of the binary bit.

[0094] Here, α0 and α1 are two adaptive parameters associated with two probability hypotheses. In a general video codec, the values ​​of α0 and α1 are selected independently for each context using a training algorithm designed to jointly optimize the adaptive parameters as well as the initial probabilities. As an example, each context is allowed to select α0 from a set of predefined values ​​{1 / 4, 1 / 8, 1 / 16, 1 / 32} and α1 from another set of predefined values ​​{1 / 32, 1 / 64, 1 / 128, 1 / 256, 1 / 512}.

[0095] In step S402, based on the first multiple hypothesis probability, the second multiple hypothesis probability and an overflow status of a predetermined register, a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval is determined.

[0096] Based on the first multiple hypothesis probability and the second multiple hypothesis probability, the current decoding interval is first subdivided into two parts, a least probable symbol (LPS) interval and a most probable symbol (MPS) interval.

[0097] For example, the average value of the first multiple hypothesis probability and the second multiple hypothesis probability can be mapped to the current decoding interval range to obtain two intervals, and the interval with a smaller interval length between the two intervals is defined as the minimum possible symbol (LowProbality Symbol, LPS for short) interval range_LPS, and the interval with a larger interval length between the two intervals is the maximum possible symbol (Most Probability Symbol, MPS) interval range_MPS, the symbol of the minimum possible symbol interval is the minimum possible symbol (LPS), and the symbol of the maximum possible symbol interval is the maximum possible symbol (MPS).

[0098] For example, LPS may be a "0" symbol, MPS may be a "1" symbol, and the current decoding interval may be a decoding interval between 0 and 1. In general, if R is the width of the current decoding interval range, r LPS is the width of the smallest possible symbol interval, r MPSis the width of the maximum possible symbol interval, p LPS is the probability of the smallest possible symbol and p MPS is the probability of the maximum possible symbol, then r LPS =R×p LPS And r MPS =R×p MPS =Rr LPS Therefore, when the probability of the smallest possible symbol is higher than the probability of the largest possible symbol, the smallest possible symbol interval will have a width r greater than the largest possible symbol interval. MPS The width r LPS That is, when p LPS >p MPS When LPS >r MPS .

[0099] In an exemplary embodiment of the present disclosure, the determination of the probability of the minimum possible symbol corresponding to the current syntax element based on the first multiple hypothesis probability and the second multiple hypothesis probability may include: respectively shifting the binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability left by a first predetermined bit; performing an AND operation on the left-shifted binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability; right shifting the result obtained by the AND operation by a second predetermined bit to obtain the probability of the minimum possible symbol, wherein the result obtained by the AND operation is stored in the predetermined register. Here, the first predetermined bit may be determined based on the difference between the number of bits of the predetermined register and the number of bits of the first multiple hypothesis probability or the number of bits of the second multiple hypothesis probability, and the second predetermined bit may be determined based on the first predetermined bit and the third predetermined bit. For example, the first predetermined bit may be, for example, but not limited to, 16 bits, and the second predetermined bit may be, for example, but not limited to, 26 bits.

[0100] In an exemplary embodiment of the present disclosure, determining the minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and the overflow state of a predetermined register may include: determining the probability of the minimum possible symbol corresponding to the current syntax element based on the first multiple hypothesis probability and the second multiple hypothesis probability; updating the probability of the minimum possible symbol based on the overflow state; determining the minimum possible symbol interval based on the current decoding interval and the updated probability of the minimum possible symbol, thereby improving decoding efficiency by using the overflow state of the predetermined register to complete the update of the probability of the minimum possible symbol.

[0101] In an exemplary embodiment of the present disclosure, updating the probability of the minimum possible symbol based on the overflow state may include: based on the overflow state being an overflow, bitwise inverting the probability of the minimum possible symbol; based on the overflow state being no overflow, keeping the probability of the minimum possible symbol unchanged, thereby improving the updating efficiency of the probability of the minimum possible symbol. For example, using the conditional selection instruction in the instruction set of the ARMv8 platform, based on the overflow state being an overflow, selecting to perform bitwise inversion of the probability of the minimum possible symbol; based on the overflow state being no overflow, selecting to keep the probability of the minimum possible symbol unchanged.

[0102] As an example, according to the register characteristics of the ARMv8 platform, the minimum possible symbol interval can be determined by the following three formulas.

[0103] p′ LPS =((p0<<16)+(p1<<16))>>26

[0104] p′ LPS = overflow? ~p′ LPS ∶p′ LPS

[0105] range LPS =((range>>5)*p′ LPS )>>1+4

[0106] Here, p0 and p1 represent the first multiple hypothesis probability and the second multiple hypothesis probability, respectively, and p′ LPS represents the probability of the minimum possible symbol, range LPS Indicates the minimum possible symbol interval, range indicates the current decoding interval, " indicates left shift, " indicates right shift, and * indicates multiplication. Since the first multiple hypothesis probability p0 and the second multiple hypothesis probability p1 are both 16-bit numbers, and the overflow status register of the ARMv8 platform is at least 32 bits, in order to simulate the overflow (overflow) 16-bit situation in the original formula, it is necessary to shift the first multiple hypothesis probability p0 and the second multiple hypothesis probability p1 left (<<) 16 bits and then add them, which is converted into an overflow (overflow) 32-bit situation.

[0107] Here, overflow refers to the overflow of (p0 < 16) + (p1 < 16). If (p0 < < 16) + (p1 < < 16) is greater than 2^32, the overflow state value is considered to be 1, and p′ LPS Invert bit by bit; if (p0<<16)+(p1<<16) is not greater than 2^32, the overflow state value is considered to be 0, and p′ needs to be LPSRemain unchanged.

[0108] In step S403, based on the value of the current code stream and the minimum possible symbol interval, the current syntax element is arithmetically decoded to obtain a decoding result of the current syntax element. For example, the decoding result may be determined based on whether the value of the current code stream falls within the minimum possible symbol interval. Here, the value of the current code stream refers to the actual decimal value of the code stream at the current moment. The decoding result of the current syntax element may be symbol 0 or symbol 1.

[0109] In an exemplary embodiment of the present disclosure, based on the value of the current code stream and the minimum possible symbol interval, performing arithmetic decoding on the current syntax element may include: determining that the symbol obtained by arithmetic decoding on the current syntax element is the minimum possible symbol based on the value of the current code stream being located in the minimum possible symbol interval; and determining that the symbol obtained by arithmetic decoding on the current syntax element is the maximum possible symbol based on the value of the current code stream not being located in the minimum possible symbol interval. For example, according to the position of the value of the current code stream (or the actual value of the current code stream) value on the current decoding interval range, determining whether the current syntax element falls on the minimum possible symbol interval range_LPS. If the current syntax element falls on the minimum possible symbol interval range_LPS, the decoded symbol x(t) is the minimum possible symbol (LPS), and if the current syntax element does not fall on the minimum possible symbol interval range_LPS, the decoded symbol x(t) is the maximum possible symbol (MPS).

[0110] In an exemplary embodiment of the present disclosure, it may also include: based on the decoding result, updating the current decoding interval to use the updated current decoding interval for decoding the next syntax element, thereby determining the decoding interval when the next syntax element is arithmetically decoded. For example, if the decoded symbol x(t) is the minimum possible symbol (LPS), the current decoding interval is updated to range=range_LPS, that is, the decoding interval of the next syntax element is range_LPS; if the decoded symbol x(t) is the maximum possible symbol (MPS), the current decoding interval is updated to range=range–range_LPS, that is, the decoding interval of the next syntax element is range–range_LPS. Here, range_LPS represents the minimum possible symbol interval.

[0111] In an exemplary embodiment of the present disclosure, it may also include: based on the value of the current code stream and the decoding result, the value of the current code stream is updated to use the updated value of the current code stream for decoding the next syntax element, thereby determining the value of the syntax element when the next syntax element is arithmetically decoded. For example, if the decoded symbol x(t) is the minimum possible symbol (LPS), the value of the current code stream is updated to value=value-(range-range_LPS), that is, the value of the next syntax element is value-(range-range_LPS); if the decoded symbol x(t) is the maximum possible symbol (MPS), the value of the current code stream remains unchanged, that is, the value of the next syntax element is value. Here, range_LPS represents the minimum possible symbol interval.

[0112] In an exemplary embodiment of the present disclosure, it may also include: based on the decoding result, updating the first multiple hypothesis probability and the second multiple hypothesis probability in parallel, so as to use the updated first multiple hypothesis probability and the second multiple hypothesis probability for decoding of the next syntax element, thereby improving decoding efficiency.

[0113] In an exemplary embodiment of the present disclosure, based on the decoding result, the first multiple hypothesis probability and the second multiple hypothesis probability are updated in parallel, which may include: updating the first multiple hypothesis probability based on the decoding result, the first probability update rate and the first multiple hypothesis probability; updating the second multiple hypothesis probability based on the decoding result, the second probability update rate and the second multiple hypothesis probability, wherein the updating of the first multiple hypothesis probability and the updating of the second multiple hypothesis probability are performed in parallel, thereby improving decoding efficiency.

[0114] For example, a single instruction multiple data (SIMD) instruction may be used to execute the following formula in parallel to update the first multiple hypothesis probability and the second multiple hypothesis probability.

[0115] p′ 0,t+1 =(p′ 0,t -α0*p′ 0,t )&MASK0+x(t)*(α0&MASK0),

[0116] p′ 1,t+1 =(p′ 1,t -α1*p′ 1,t )&MASK1+x(t)*(α1&MASK1).

[0117] Here, p′ 0,t+1 represents the updated first multi-hypothesis probability, p′ 0,trepresents the first multiple hypothesis probability, α0 represents a predetermined first constant (which can be obtained by looking up a table), MASK0 represents a first probability update rate, x(t) represents the symbol obtained by decoding, and p′ 1,t+1 represents the updated second multi-hypothesis probability, p′ 1,t represents the second multiple hypothesis probability, α1 represents a predetermined second constant (which can be obtained by looking up a table), and MASK1 represents a second probability update rate.

[0118] In an exemplary embodiment of the present disclosure, based on the decoding result, updating the first multi-hypothesis probability and the second multi-hypothesis probability in parallel may include: combining the first multi-hypothesis probability and the second multi-hypothesis probability into a probability vector, and combining the first probability update rate and the second probability update rate into a probability update rate vector; based on the decoding result, the probability update rate vector, and the probability vector, updating the probability vector to obtain an updated probability vector, thereby improving the updating efficiency of the first multi-hypothesis probability and the second multi-hypothesis probability by calculating the operation of the first multi-hypothesis probability and the second multi-hypothesis probability as a vector.

[0119] In an exemplary embodiment of the present disclosure, updating the probability vector based on the decoding result, the probability update rate vector, and the probability vector may include: obtaining a predetermined first constant and a predetermined second constant, and forming a constant vector with the predetermined first constant and the predetermined second constant; determining a product vector obtained by performing a cross product operation on the constant vector and the probability vector; determining a difference vector obtained by subtracting the product vector from the probability vector; and determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result, thereby simplifying the operation process and further improving the operation efficiency by determining the predetermined third constant in advance.

[0120] In an exemplary embodiment of the present disclosure, determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result may include: determining a mask result of the decoding result; obtaining a predetermined third constant, and determining the product of the predetermined third constant and the mask result; determining a result vector obtained by performing a cross product operation on the difference vector and the probability update rate vector; performing a sum operation on the result vector and the product, and using the sum vector obtained by the sum operation as an updated probability vector, thereby determining whether it is necessary to add the predetermined third constant through a mask, thereby reducing code resource consumption, and further improving computing efficiency by determining the predetermined third constant in advance.

[0121] In an exemplary embodiment of the present disclosure, determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result may include: when the decoding result is a first value, taking the product vector of the difference vector and the probability update rate vector as the updated probability vector; when the decoding result is a second value, obtaining a predetermined third constant, and taking the sum vector obtained by performing a cross product operation on the difference vector and the probability update rate vector and performing a sum operation on the predetermined third constant as the updated probability vector, thereby determining whether it is necessary to add the constant C according to whether the decoding result is 0 or 1, and further improving the computing efficiency by determining the predetermined third constant in advance.

[0122] For example, the first multiple-hypothesis probability and the second multiple-hypothesis probability may be updated more efficiently by the following vector calculation.

[0123] P′ t+1 =(P′ t -A*P′ t )&MASK 01 +x(t)*A&MASK 01 .

[0124] Here, P′ t+1 represents the updated probability vector, P′ t represents the probability vector, A represents the constant vector including α0 and α1, MASK 01 represents the probability update rate vector, and x(t) represents the decoded symbol.

[0125] When the decoded symbol x(t) = 0, P′ t+1 =(P′ t -A*P′ t )&MASK 01 .

[0126] When the decoded symbol x(t) = 1, due to A&MASK 01 It is a fixed value, so there is no need to calculate it every time. Instead, A&MASK 01 As a constant C, therefore, P′ t+1 =(P′ t -A*P′ t )&MASK 01 +C.

[0127] Obviously, it is necessary to judge whether to add the constant C based on the value of x(t). It is very resource-consuming to make the judgment directly in the code. In this disclosure, the mask MASK of x(t) can be used. BIN To determine whether the constant C needs to be added. For example, MASK BIN=(-x(t))>>31. Therefore, it can be obtained by a vector formula P′ t+1 =(P′ t -A*P′ t )&MASK 01 +C&MASK BIN To more efficiently update the first multiple hypothesis probability and the second multiple hypothesis probability.

[0128] The above has been combined Figure 4 A decoding method according to an exemplary embodiment of the present disclosure is described. Figure 5 A decoding device and units thereof according to an exemplary embodiment of the present disclosure are described.

[0129] Figure 5 A block diagram of a decoding device according to an exemplary embodiment of the present disclosure is shown.

[0130] Reference Figure 5 The decoding device includes a parameter acquisition unit 51, a corresponding interval determination unit 52 and a decoding unit 53.

[0131] The parameter acquisition unit 51 is configured to acquire a current decoding interval corresponding to a current syntax element, a first multiple hypothesis probability and a second multiple hypothesis probability of the current syntax element.

[0132] The corresponding interval determination unit 52 is configured to determine the minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and an overflow status of a predetermined register.

[0133] In an exemplary embodiment of the present disclosure, the corresponding interval determination unit 52 can be configured to: determine the probability that the current syntax element corresponds to the minimum possible symbol based on the first multiple hypothesis probability and the second multiple hypothesis probability; update the probability of the minimum possible symbol based on the overflow state; determine the minimum possible symbol interval based on the current decoding interval and the updated probability of the minimum possible symbol.

[0134] In an exemplary embodiment of the present disclosure, the determination of the probability of the minimum possible symbol corresponding to the current syntax element based on the first multiple hypothesis probability and the second multiple hypothesis probability may include: respectively shifting the binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability left by a first predetermined bit; performing an AND operation on the left-shifted binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability; and right-shifting the result obtained by the AND operation by a second predetermined bit to obtain the probability of the minimum possible symbol, wherein the result obtained by the AND operation is stored in the predetermined register. The predetermined register is configured to perform the following operations: performing an AND operation on the first multiple hypothesis probability shifted left by a first predetermined bit and the second multiple hypothesis probability shifted left by a first predetermined bit, wherein here, the first predetermined bit may be determined based on the difference between the number of bits of the predetermined register and the number of bits of the first multiple hypothesis probability or the number of bits of the second multiple hypothesis probability, and the second predetermined bit may be determined based on the first predetermined bit and the third predetermined bit.

[0135] In an exemplary embodiment of the present disclosure, the corresponding interval determination unit 52 may be configured to: by using a predetermined condition to select an instruction, based on the overflow state being overflow, perform bitwise inversion of the probability of the minimum possible symbol; by using the predetermined condition to select an instruction, based on the overflow state being no overflow, keep the probability of the minimum possible symbol unchanged.

[0136] The decoding unit 53 is configured to perform arithmetic decoding on the current syntax element based on the value of the current code stream and the minimum possible symbol interval to obtain a decoding result of the current syntax element.

[0137] In an exemplary embodiment of the present disclosure, the decoding unit 53 may be configured to: determine that the symbol obtained by arithmetically decoding the current syntax element is the minimum possible symbol based on the value of the current code stream being within the minimum possible symbol interval; and determine that the symbol obtained by arithmetically decoding the current syntax element is the maximum possible symbol based on the value of the current code stream not being within the minimum possible symbol interval.

[0138] In an exemplary embodiment of the present disclosure, the decoding device further includes: a decoding interval updating unit (not shown), configured to update the current decoding interval based on the decoding result to use the updated current decoding interval for decoding the next syntax element.

[0139] In an exemplary embodiment of the present disclosure, the decoding device further includes: an element updating unit (not shown), which is configured to update the value of the current code stream based on the value of the current code stream and the decoding result, so as to use the updated value of the current code stream for decoding of the next syntax element.

[0140] In an exemplary embodiment of the present disclosure, the decoding device also includes: a probability updating unit (not shown), which is configured to update the first multiple hypothesis probability and the second multiple hypothesis probability in parallel based on the decoding result, so as to use the updated first multiple hypothesis probability and the second multiple hypothesis probability for decoding of the next syntax element.

[0141] In an exemplary embodiment of the present disclosure, the probability update unit is configured to: update the first multiple hypothesis probability based on the decoding result, the first probability update rate and the first multiple hypothesis probability; update the second multiple hypothesis probability based on the decoding result, the second probability update rate and the second multiple hypothesis probability, wherein the updating of the first multiple hypothesis probability and the updating of the second multiple hypothesis probability are performed in parallel.

[0142] In an exemplary embodiment of the present disclosure, the probability update unit is configured to: combine the first multi-hypothesis probability and the second multi-hypothesis probability into a probability vector, and combine the first probability update rate and the second probability update rate into a probability update rate vector; and update the probability vector based on the decoding result, the probability update rate vector, and the probability vector.

[0143] In an exemplary embodiment of the present disclosure, the probability update unit is configured to: obtain a predetermined first constant and a predetermined second constant, and combine the predetermined first constant and the predetermined second constant into a constant vector; determine a product vector obtained by performing a cross product operation on the constant vector and the probability vector; determine a difference vector obtained by subtracting the product vector from the probability vector; and determine an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result.

[0144] In an exemplary embodiment of the present disclosure, the probability update unit is configured to: determine the decoding result; obtain a predetermined third constant, and determine the product of the predetermined third constant and the mask result; determine a result vector obtained by performing a cross product operation on the difference vector and the probability update rate vector; perform a sum operation on the result vector and the product, and use the sum vector obtained by the sum operation as an updated probability vector.

[0145] In an exemplary embodiment of the present disclosure, the probability update unit is configured to: when the decoding result is a first value, use the product vector of the difference vector and the probability update rate vector as an updated probability vector; when the decoding result is a second value, obtain a predetermined third constant, and use the sum vector obtained by performing a cross product operation on the difference vector and the probability update rate vector and performing a sum operation on the predetermined third constant as an updated probability vector.

[0146] Regarding the device in the above embodiment, the specific manner in which each unit performs the operation has been described in detail in the embodiment of the method, and will not be elaborated here.

[0147] The above has been combined Figure 5 The decoding device according to the exemplary embodiment of the present disclosure is described. Figure 6 An electronic device according to an exemplary embodiment of the present disclosure is described.

[0148] Figure 6 is a block diagram of an electronic device 600 according to an exemplary embodiment of the present disclosure.

[0149] Reference Figure 6 The electronic device 600 includes at least one memory 601 and at least one processor 602, wherein the at least one memory 601 stores a set of computer executable instructions, and when the computer executable instruction set is executed by the at least one processor 602, the decoding method according to the exemplary embodiment of the present disclosure is performed.

[0150] In an exemplary embodiment of the present disclosure, the electronic device 600 may be a PC, a tablet device, a personal digital assistant, a smart phone, or other device capable of executing the above-mentioned instruction set. Here, the electronic device 600 is not necessarily a single electronic device, but may also be any device or circuit collection capable of executing the above-mentioned instructions (or instruction sets) individually or in combination. The electronic device 600 may also be part of an integrated control system or system manager, or may be configured as a portable electronic device interconnected with a local or remote (e.g., via wireless transmission) interface.

[0151] In the electronic device 600, the processor 602 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller or a microprocessor. As an example and not limitation, the processor may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0152] The processor 602 may execute instructions or codes stored in the memory 601, which may also store data. Instructions and data may also be sent and received over a network via a network interface device, which may employ any known transmission protocol.

[0153] The memory 601 may be integrated with the processor 602, for example, by placing RAM or flash memory within an integrated circuit microprocessor or the like. In addition, the memory 601 may include a separate device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The memory 601 and the processor 602 may be operatively coupled, or may communicate with each other, such as through an I / O port, a network connection, etc., so that the processor 602 can read files stored in the memory.

[0154] In addition, the electronic device 600 may further include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.) All components of the electronic device 600 may be connected to each other via a bus and / or a network.

[0155] According to an exemplary embodiment of the present disclosure, a computer-readable storage medium including instructions is also provided, such as a memory 601 including instructions, and the above instructions can be executed by a processor 602 of an apparatus 600 to complete the above method. Alternatively, the computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0156] According to an exemplary embodiment of the present disclosure, a computer program product may also be provided. The computer program product includes a computer program / instruction. When the computer program / instruction is executed by a processor, the decoding method according to the exemplary embodiment of the present disclosure is implemented.

[0157] The above has been referred to Figures 1 to 6 The decoding method and apparatus according to the exemplary embodiments of the present disclosure are described. However, it should be understood that: Figure 5 The decoding device and its units shown in the figure may be respectively configured as software, hardware, firmware or any combination of the above items to perform specific functions. Figure 6 The electronic device shown in is not limited to including the components shown above, but some components may be added or deleted as needed, and the above components may also be combined.

[0158] Figure 7 A computing environment 710 is shown coupled to a user interface 750. The computing environment 710 may be part of a data processing server. The computing environment 710 includes a processor 720, a memory 730, and an input / output (I / O) interface 740.

[0159] The processor 720 generally controls the overall operation of the computing environment 710, such as operations associated with display, data acquisition, data communication, and image processing. The processor 720 may include one or more processors for executing instructions to perform all or some steps in the above method. In addition, the processor 720 may include one or more modules that facilitate the interaction between the processor 720 and other components. The processor may be a central processing unit (CPU), a microprocessor, a single-chip microcomputer, a graphics processing unit (GPU), etc.

[0160] The memory 730 is configured to store various types of data to support the operation of the computing environment 710. The memory 730 may include predetermined software 732. Examples of such data include instructions for any application or method operating on the computing environment 710, video data sets, image data, etc. The memory 730 may be implemented by using any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0161] I / O interface 740 provides an interface between processor 720 and peripheral interface modules (e.g., keyboard, click wheel, buttons, etc.). Buttons may include, but are not limited to, a home button, a start scan button, and a stop scan button. I / O interface 740 may be coupled to an encoder and a decoder.

[0162] In an embodiment, a non-transitory computer-readable storage medium including, for example, a plurality of programs in a memory 730 and / or storing a bit stream generated by the above encoding method or a bit stream to be decoded by the above decoding method is also provided, wherein the plurality of programs can be executed by a processor 720 in a computing environment 710 to perform the above method. In one example, the plurality of programs can be executed by a processor 720 in a computing environment 710 to (for example, from Figure 2 The video encoder 20 in the computing environment 710 receives a bit stream or data stream including encoded video information (e.g., video blocks representing encoded video frames, and / or one or more associated syntax elements, etc.), and can also be executed by the processor 720 in the computing environment 710 to perform the above-mentioned decoding method according to the received bit stream or data stream. In another example, the multiple programs can be executed by the processor 720 in the computing environment 710 to perform the above-mentioned encoding method to encode the video information (e.g., video blocks representing video frames, and / or one or more associated syntax elements, etc.) into a bit stream or data stream, and can also be executed by the processor 720 in the computing environment 710 to (e.g., to Figure 3Alternatively, a non-transitory computer-readable storage medium may store the bit stream or data stream generated by the encoder (e.g., Figure 2 The video encoder 20 in FIG. 1 generates a video signal for a decoder (eg, Figure 3 A bitstream or data stream including encoded video information (e.g., video blocks representing encoded video frames, and / or associated one or more syntax elements, etc.) used by the video decoder 30 in the video decoder 30 when decoding video data. The non-transitory computer-readable storage medium can be, for example, a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0163] In an embodiment, a bit stream generated by the above encoding method or a bit stream to be decoded by the above decoding method is provided. In an embodiment, a bit stream including encoded video information generated by the above encoding method or encoded video information to be decoded by the above decoding method is provided.

[0164] In an embodiment, a computing device is also provided, which includes: one or more processors (e.g., processor 720); and a non-transitory computer-readable storage medium or memory 730 in which multiple programs that can be executed by the one or more processors are stored, wherein the one or more processors are configured to perform the above-mentioned method when executing the multiple programs.

[0165] In an embodiment, a computer program product having instructions for storing or transmitting a bitstream is also provided, wherein the bitstream includes coded video information generated by the above encoding method or coded video information to be decoded by the above decoding method. In an embodiment, a computer program product including, for example, a plurality of programs in a memory 730 is also provided, wherein the plurality of programs can be executed by a processor 720 in a computing environment 710 for performing the above method. For example, the computer program product may include a non-transitory computer-readable storage medium.

[0166] In an embodiment, the computing environment 710 may be implemented by one or more ASICs, DSPs, digital signal processing devices (DSPDs), programmable logic devices (PLDs), FPGAs, GPUs, controllers, microcontrollers, microprocessors, or other electronic components for performing the above methods.

[0167] In an embodiment, a method for storing a bit stream is also provided, comprising: storing the bit stream on a digital storage medium, wherein the bit stream comprises encoded video information generated by the above encoding method or encoded video information to be decoded by the above decoding method.

[0168] In an embodiment, a method for transmitting a bit stream generated by the above encoder is also provided. In an embodiment, a method for receiving a bit stream to be decoded by the above decoder is also provided.

[0169] The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limited to the present disclosure. Many modifications, variations, and alternative embodiments will be apparent to one of ordinary skill in the art having the benefit of the teachings presented in the foregoing description and the associated drawings.

[0170] Unless otherwise specifically stated, the order of steps of the method according to the present disclosure is intended to be illustrative only, and the steps of the method according to the present disclosure are not limited to the order specifically described above, but can be changed according to actual conditions. In addition, at least one of the steps of the method according to the present disclosure can be adjusted, combined or deleted according to actual needs.

[0171] The examples are chosen and described in order to explain the principles of the present disclosure and to enable other persons skilled in the art to understand the various embodiments of the present disclosure and to best utilize the basic principles and various embodiments with various modifications suitable for the specific use contemplated. Therefore, it will be understood that the scope of the present disclosure is not limited to the specific examples of the disclosed embodiments, and modifications and other embodiments are intended to be included within the scope of the present disclosure.

[0172] According to the decoding method and device disclosed in the present invention, by obtaining the current decoding interval corresponding to the current syntax element, the first multiple hypothesis probability and the second multiple hypothesis probability of the current syntax element, based on the first multiple hypothesis probability, the second multiple hypothesis probability and the overflow state of the predetermined register, the minimum possible symbol interval corresponding to the current syntax element in the current decoding interval is determined, and based on the value of the current code stream and the minimum possible symbol interval, the current syntax element is arithmetically decoded to obtain the decoding result of the current syntax element, thereby improving the decoding efficiency.

Claims

1. A decoding method, characterized in that: include: Obtaining a current decoding interval corresponding to a current syntax element, a first multiple hypothesis probability and a second multiple hypothesis probability of the current syntax element; Determining, based on the first multiple hypothesis probability, the second multiple hypothesis probability, and an overflow state of a predetermined register, a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval; Based on the value of the current code stream and the minimum possible symbol interval, the current syntax element is arithmetically decoded to obtain a decoding result of the current syntax element.

2. The decoding method according to claim 1, characterized in that: The determining, based on the first multiple hypothesis probability, the second multiple hypothesis probability and an overflow state of a predetermined register, a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval comprises: Determining, based on the first multiple hypothesis probability and the second multiple hypothesis probability, a probability that the current syntax element corresponds to a minimum possible symbol; updating the probability of the minimum possible symbol based on the overflow state; The minimum possible symbol interval is determined based on the current decoding interval and the updated probability of the minimum possible symbol.

3. The decoding method according to claim 2, characterized in that: The determining, based on the first multiple hypothesis probability and the second multiple hypothesis probability, a probability that the current syntax element corresponds to a minimum possible symbol includes: Left-shifting the binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability by a first predetermined bit, respectively; Performing an AND operation on the left-shifted binary bits corresponding to the first multiple hypothesis probability and the second multiple hypothesis probability; The result obtained by the sum operation is shifted right by a second predetermined bit to obtain the probability of the minimum possible symbol, The result obtained by the sum operation is stored in the predetermined register.

4. The decoding method according to claim 3, characterized in that: The updating of the probability of the minimum possible symbol based on the overflow state comprises: Based on the overflow state being an overflow, bitwise inverting the probability of the minimum possible symbol; Based on the overflow status being no overflow, the probability of the minimum possible symbol is kept unchanged.

5. The decoding method according to claim 1, characterized in that: The performing arithmetic decoding on the current syntax element based on the value of the current code stream and the minimum possible symbol interval includes: Determining, based on the value of the current code stream being in the minimum possible symbol interval, that a symbol obtained by performing arithmetic decoding on the current syntax element is a minimum possible symbol; Based on the fact that the value of the current code stream is not located in the minimum possible symbol interval, it is determined that the symbol obtained by performing arithmetic decoding on the current syntax element is a maximum possible symbol.

6. The decoding method according to claim 1, characterized in that: Also includes: Based on the decoding result, the current decoding interval is updated to use the updated current decoding interval for decoding of a next syntax element.

7. The decoding method according to claim 1, characterized in that: Also includes: Based on the value of the current code stream and the decoding result, the value of the current code stream is updated, so that the updated value of the current code stream is used for decoding of the next syntax element.

8. The decoding method according to claim 1, characterized in that: Also includes: Based on the decoding result, the first multiple hypothesis probability and the second multiple hypothesis probability are updated in parallel, so as to use the updated first multiple hypothesis probability and the updated second multiple hypothesis probability for decoding of the next syntax element.

9. The decoding method according to claim 8, characterized in that: The updating of the first multiple hypothesis probability and the second multiple hypothesis probability in parallel based on the decoding result comprises: Based on the decoding result, the first probability update rate and the first multiple hypothesis probability, updating the first multiple hypothesis probability; Based on the decoding result, the second probability update rate, and the second multiple hypothesis probability, updating the second multiple hypothesis probability, The updating of the first multiple hypothesis probabilities and the updating of the second multiple hypothesis probabilities are performed in parallel.

10. The decoding method according to claim 8, characterized in that: The updating of the first multiple hypothesis probability and the second multiple hypothesis probability in parallel based on the decoding result comprises: Combining the first multiple hypothesis probability and the second multiple hypothesis probability into a probability vector, and combining the first probability update rate and the second probability update rate into a probability update rate vector; The probability vector is updated based on the decoding result, the probability update rate vector, and the probability vector.

11. The decoding method according to claim 10, characterized in that: The updating of the probability vector based on the decoding result, the probability update rate vector, and the probability vector comprises: Obtaining a predetermined first constant and a predetermined second constant, and combining the predetermined first constant and the predetermined second constant into a constant vector; Determine a product vector obtained by performing a cross product operation of the constant vector and the probability vector; Determine a difference vector obtained by subtracting the product vector from the probability vector; An updated probability vector is determined based on the difference vector, the probability update rate vector, and the decoding result.

12. The decoding method according to claim 11, characterized in that: The step of determining an updated probability vector based on the difference vector, the probability update rate vector, and the decoding result comprises: Determining a mask result of the decoding result; Obtaining a predetermined third constant, and determining a product of the predetermined third constant and the mask result; Determine a result vector obtained by performing a cross product operation of the difference vector and the probability update rate vector; A sum operation is performed on the result vector and the product, and a sum vector obtained by the sum operation is used as an updated probability vector.

13. A decoding device, characterized in that: include: A parameter acquisition unit, configured to acquire a current decoding interval corresponding to a current syntax element, a first multiple hypothesis probability and a second multiple hypothesis probability of the current syntax element; a corresponding interval determining unit, configured to determine a minimum possible symbol interval corresponding to the current syntax element in the current decoding interval based on the first multiple hypothesis probability, the second multiple hypothesis probability and an overflow state of a predetermined register; and The decoding unit is configured to perform arithmetic decoding on the current syntax element based on the value of the current code stream and the minimum possible symbol interval to obtain a decoding result of the current syntax element.

14. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the decoding method according to any one of claims 1 to 12.

15. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor of an electronic device, the electronic device is caused to perform the decoding method according to any one of claims 1 to 12.

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