Image sensing apparatus

Abstract

Disclosed is an image sensing apparatus including: a current supply circuit coupled between a supply terminal of a first voltage and a pair of output terminals; an input circuit coupled between the pair of output terminals and the common node and adapted to receive a pixel signal and a ramp signal; and a mirroring circuit coupled between the common node and the supply terminal of the second voltage, and adapted to compensate an operation current flowing between the common node and the supply terminal of the second voltage based on the reference current when the operation current is generated by mirroring the reference current.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application date of November 11, 2020, application number 202011256081.3, and invention name “Image Sensing Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to Korean Patent Application No. 10-2020-0045972, filed on April 16, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to an image sensing device. Background Art

[0005] An image sensing device is a device for capturing images using the property of semiconductors to react to light. Image sensing devices can be classified into charge coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. Recently, CMOS image sensing devices are more widely used because they can allow both analog and digital control circuits to be directly implemented on a single integrated circuit (IC). Summary of the invention

[0006] Various embodiments of the present disclosure are directed to an image sensing device capable of suppressing noise occurring in a circuit structure.

[0007] According to one embodiment, an image sensing device may include: a current supply circuit coupled between a supply terminal of a first voltage and a pair of output terminals; an input circuit coupled between the pair of output terminals and a common node and adapted to receive a pixel signal and a ramp signal; and a mirror circuit coupled between the common node and a supply terminal of a second voltage and adapted to compensate an operating current based on a reference current when an operating current flowing between the common node and the supply terminal of the second voltage is generated by mirroring a reference current.

[0008] The mirror circuit may include: a first mirror element coupled between an input terminal of a reference current and a supply terminal of a second voltage, and adapted to generate a bias voltage corresponding to the reference current; a second mirror element coupled between a common node and a supply terminal of the second voltage, and adapted to generate an operating current corresponding to the reference current based on the bias voltage; a compensation element coupled between a supply terminal of a third voltage and an output terminal of the bias voltage, and adapted to compensate the bias voltage based on the reference current; and a current source coupled between the output terminal of the bias voltage and the supply terminal of the second voltage.

[0009] The first mirror element and the compensation element may be coupled to each other in a nested feedback structure.

[0010] According to one embodiment, an image sensing device may include: a current supply circuit coupled between a supply terminal of a first voltage and a pair of output terminals; an input circuit coupled between the pair of output terminals and a common node and adapted to receive a pixel signal and a ramp signal; and a mirror circuit coupled between the common node and a supply terminal of a second voltage and adapted to compensate an operating current based on the operating current when an operating current flowing between the common node and the supply terminals of the second voltage is generated by mirroring a reference current.

[0011] The mirror circuit may include: a first mirror element coupled between an input terminal of a reference current and a supply terminal of a second voltage, and adapted to generate a bias voltage corresponding to the reference current; a second mirror element coupled between a common node and a supply terminal of the second voltage, and adapted to generate an operating current corresponding to the reference current based on the bias voltage; a compensation element coupled between the supply terminal of the first voltage and an output terminal of the bias voltage, and adapted to compensate the bias voltage based on the operating current; and a current source coupled between the output terminal of the bias voltage and the supply terminal of the second voltage.

[0012] The first mirror element and the compensation element may be coupled to each other in a nested feedback structure.

[0013] According to one embodiment, an image sensing device may include: a reference current generator, suitable for generating a reference current; at least one bias voltage generator, suitable for generating at least one bias voltage corresponding to the reference current and compensating at least one bias voltage based on the reference current; and a plurality of comparators, which are enabled based on at least one bias voltage and are suitable for respectively comparing a plurality of pixel signals with a ramp signal.

[0014] At least one bias voltage generator may include: a first mirror element coupled between an input terminal of a reference current and a supply terminal of a low voltage and adapted to generate a bias voltage corresponding to the reference current; a compensation element coupled between a supply terminal of a first high voltage and an output terminal of the bias voltage and adapted to compensate the bias voltage based on the reference current; and a current source coupled between the output terminal of the bias voltage and the supply terminal of the low voltage.

[0015] The first mirror element and the compensation element may be coupled to each other in a nested feedback structure.

[0016] According to one embodiment, an image sensing device may include: a reference current generator, suitable for generating a reference current; at least one bias voltage generator, suitable for generating at least one bias voltage corresponding to the reference current; and a plurality of comparators, which are enabled based on at least one bias voltage and are suitable for compensating for the bias voltage based on an operating current generated in the plurality of comparators when respectively comparing a plurality of pixel signals with a ramp signal.

[0017] Each of the comparators may include: a current supply circuit coupled between a supply terminal of a second high voltage and a pair of output terminals; an input circuit coupled between the pair of output terminals and a common node and adapted to receive each of the pixel signals and a ramp signal; a second mirror element coupled between the common node and a supply terminal of a low voltage and adapted to generate an operating current corresponding to a reference current based on a corresponding bias voltage; a compensation element coupled between the supply terminal of the second high voltage and an output terminal of a corresponding bias voltage and adapted to compensate for the bias voltage based on the operating current; and a current source coupled between the output terminal of the corresponding bias voltage and the supply terminal of the low voltage.

[0018] The second mirror element and the compensation element may be coupled to each other in a nested feedback structure.

[0019] The at least one bias voltage generator may include a first mirror element coupled between an input terminal of the reference current and a supply terminal of the low voltage and generating a bias voltage corresponding to the reference current.

[0020] According to one embodiment, an image sensing device may include: a generating circuit adapted to generate a bias voltage based on a reference current; a comparing circuit adapted to generate an operating current based on the bias voltage and, based on the operating current, compare a pixel signal with a ramp signal to generate a comparison signal; and a compensating circuit adapted to compensate the bias voltage based on one of the reference current and the operating current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram illustrating an image sensing device according to a first embodiment of the present disclosure.

[0022] Figure 2 It is a graphic Figure 1 Circuit diagram of the bias voltage generator and the first comparator shown in .

[0023] Figure 3 is a block diagram illustrating an image sensing device according to a second embodiment of the present disclosure.

[0024] Figure 4 It is a graphic Figure 3 Circuit diagram of the bias voltage generator and the first comparator shown in .

[0025] Figure 5 is a block diagram illustrating an image sensing device according to a third embodiment of the present disclosure.

[0026] Figure 6 It is a graphic Figure 5 Circuit diagram of the first bias voltage generator and the first comparator shown in .

[0027] Figure 7 is a block diagram illustrating an image sensing device according to a fourth embodiment of the present disclosure.

[0028] Figure 8 It is a graphic Figure 7 Circuit diagram of the first bias voltage generator and the first comparator shown in . DETAILED DESCRIPTION

[0029] Various embodiments are described below with reference to the accompanying drawings in order to describe the present disclosure in detail so that a person having ordinary skill in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0030] It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or coupled to the other element, or electrically connected to or coupled to the other element with one or more elements interposed therebetween. In addition, it will be understood that when used in this specification, the terms "comprises" and "includes" specify the presence of the element, and do not exclude the presence or addition of one or more other elements. Throughout the description of the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it will be understood that components may be formed in the plural.

[0031] Figure 1 is a block diagram illustrating an image sensing apparatus 100 according to a first embodiment of the present disclosure.

[0032] refer to Figure 1 , the image sensing device 100 may include a reference current generator 110 , a bias voltage generator 120 , and first to nth comparators 130_1 to 130 — n.

[0033] The reference current generator 110 may generate a reference current IREF. For example, the reference current generator 110 may include a bandgap reference circuit. In one embodiment, the reference current generator 110 may be coupled between a supply terminal of the first high voltage VDD1 and a supply terminal of the low voltage VSS.

[0034] The bias voltage generator 120 may generate a bias voltage VBIAS corresponding to the reference current IREF. The bias voltage generator 120 may compensate the bias voltage VBIAS based on the reference current IREF. In one embodiment, the bias voltage generator 120 may be coupled between a supply terminal of the first high voltage VDD1 and a supply terminal of the low voltage VSS (reference voltage VDD1). Figure 2 ).

[0035] Each of the first to nth comparators 130_1 to 130_n may be enabled based on the bias voltage VBIAS. The first to nth comparators 130_1 to 130_n may respectively compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP, and respectively generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results. For example, the first comparator 130_1 may be enabled based on the bias voltage VBIAS, compare the first pixel signal VPX1 with the ramp signal VRP, and generate a first comparison signal COMP1 corresponding to the comparison result. In one embodiment, each of the first to nth comparators 130_1 to 130_n may be coupled between a supply terminal of the second high voltage VDD2 and a supply terminal of the low voltage VSS (reference voltage VDD2). Figure 2 ). The first high voltage VDD1 and the second high voltage VDD2 may be different voltages or the same voltage.

[0036] Figure 2 It is a diagram such as Figure 1 2 and 3. The circuit diagram of the bias voltage generator 120 and the first comparator 130_1 is shown in FIG.

[0037] refer to Figure 2 , the bias voltage generator 120 may include a first mirror element N1, a compensation element N2, and a current source CS.

[0038] The first mirror element N1 may be coupled between an input terminal of a reference current IREF and a supply terminal of a low voltage VSS, and generate a bias voltage VBIAS corresponding to the reference current IREF. For example, the first mirror element N1 may include an NMOS transistor having a gate terminal coupled to an output terminal of the bias voltage VBIAS, and having a drain terminal and a source terminal coupled between an input terminal of the reference current IREF and a supply terminal of the low voltage VSS.

[0039] The compensation element N2 may be coupled between the supply terminal of the first high voltage VDD1 and the output terminal of the bias voltage VBIAS, and compensate the bias voltage VBIAS based on the reference current IREF. For example, the compensation element N2 may include an NMOS transistor having a gate terminal coupled to the input terminal of the reference current IREF, and having a source terminal and a drain terminal coupled between the supply terminal of the first high voltage VDD1 and the output terminal of the bias voltage VBIAS.

[0040] The first mirror element N1 and the compensation element N2 may be coupled to each other in a nested feedback structure.

[0041] The current source CS may be coupled between the output terminal of the bias voltage VBIAS and the supply terminal of the low voltage VSS. The current source CS may be used to help the compensation element N2 apply a compensation current to the output terminal of the bias voltage VBIAS.

[0042] The first comparator 130_1 may include current supply circuits PM1 and PM2, input circuits NM1 and NM2, an enabling circuit NM3, and switch circuits SW1 and SW2.

[0043] The current supply circuits PM1 and PM2 may be coupled between a supply terminal of the second high voltage VDD2 and a pair of output terminals ON1 and ON2. A first comparison signal COMP1 may be generated through one output terminal of the pair of output terminals ON1 and ON2.

[0044] The input circuits NM1 and NM2 may be coupled between the pair of output terminals ON1 and ON2 and the common node CN. The input circuits NM1 and NM2 may receive the first pixel signal VPX1 and the ramp signal VRP.

[0045] The enabling circuit NM3 may be coupled between the common node CN and the supply terminal of the low voltage VSS. The enabling circuit NM3 may generate an operating current IN corresponding to the reference current IREF based on the bias voltage VBIAS. For example, the enabling circuit NM3 may include an NMOS transistor having a gate terminal coupled to an output terminal of the bias voltage VBIAS and having a drain terminal and a source terminal coupled between the common node CN and the supply terminal of the low voltage VSS.

[0046] The enabling circuit NM3 together with the bias voltage generator 120 can be configured as a mirror circuit MC. That is, the enabling circuit NM3 can be configured as a second mirror element NM3 interconnected with the first mirror element N1. The mirror circuit MC can be coupled between the common node CN and the supply terminal of the low voltage VSS, and by mirroring the reference current IREF, to generate an operating current IN, which flows between the common node CN and the supply terminal of the low voltage VSS. The mirror circuit MC can compensate the operating current IN based on the reference current IREF.

[0047] Hereinafter, the operation of the image sensing device 100 according to the first embodiment having the above-described configuration will be described.

[0048] When the reference current generator 110 generates the reference current IREF, the bias voltage generator 120 may generate a bias voltage VBIAS corresponding to the reference current IREF, and the first to nth comparators 130_1 to 130 — n may be enabled according to the bias voltage VBIAS.

[0049] When the first to nth pixel signals VPX1 to VPXn and the ramp signal VRP are input, the first to nth comparators 130_1 to 130_n may respectively compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP and respectively generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results.

[0050] In one embodiment, the first to nth comparators 130_1 to 130_n may operate simultaneously. That is, the first to nth comparison signals COMP1 to COMPn may be transformed simultaneously or at different times according to the levels of the first to nth pixel signals VPX1 to VPXn, respectively. As the number of comparison signals simultaneously transformed among the first to nth comparison signals COMP1 to COMPn increases, noise may be reflected in the operating current IN flowing through each of the first to nth comparators 130_1 to 130_n. In other words, noise having a positive (+) voltage level or a negative (-) voltage level may be applied to the output terminal of the bias voltage VBIAS. This noise is called band noise. Due to the band noise, the reference current IREF may not have a target level. Because the bias voltage VBIAS does not have a target level due to the reference current IREF not having a target level, the first to nth comparators 130_1 to 130_n may not be able to normally generate the first to nth comparison signals COMP1 to COMPn.

[0051] However, the compensation element N2 included in the bias voltage generator 120 can sense when the reference current IREF does not have a target level and compensate the bias voltage VBIAS. For example, when the reference current IREF changes, the compensation element N2 can adjust the compensation current applied to the output terminal of the bias voltage VBIAS. When the reference current IREF becomes higher than the target level due to the band noise with a positive (+) voltage level, the compensation element N2 can apply a relatively low compensation current to the output terminal of the bias voltage VBIAS. On the other hand, when the reference current IREF becomes lower than the target level due to the band noise with a negative (-) voltage level, the compensation element N2 can apply a relatively high compensation current to the output terminal of the bias voltage VBIAS. Therefore, while the noise reflected in the operating current IN is offset, the first to nth comparators 130_1 to 130_n can respectively generate the first to nth comparison signals COMP1 to COMPn normally.

[0052] Figure 3 is a block diagram illustrating an image sensing apparatus 200 according to a second embodiment of the present disclosure.

[0053] refer to Figure 3 , the image sensing device 200 may include a reference current generator 210 , a bias voltage generator 220 , and first to nth comparators 230_1 to 230 — n.

[0054] The reference current generator 210 may generate a reference current IREF. For example, the reference current generator 210 may include a bandgap reference circuit.

[0055] The bias voltage generator 220 may generate a bias voltage VBIAS corresponding to the reference current IREF.

[0056] Each of the first to nth comparators 230_1 to 230_n may be enabled based on the bias voltage VBIAS. The first to nth comparators 230_1 to 230_n may respectively compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP, and respectively generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results. For example, the first comparator 230_1 may be enabled based on the bias voltage VBIAS, compare the first pixel signal VPX1 with the ramp signal VRP, and generate a first comparison signal COMP1 corresponding to the comparison result. When each of the first to nth pixel signals VPX1 to VPXn is compared with the ramp signal VRP, the first to nth comparators 230_1 to 230_n may compensate for the bias voltage VBIAS based on the operating current IN generated therein.

[0057] Figure 4 It is a diagram such as Figure 3 2 and 3. The circuit diagram of the bias voltage generator 220 and the first comparator 230_1 is shown in FIG.

[0058] refer to Figure 4 , the bias voltage generator 220 may include a first mirror element N1.

[0059] The first mirror element N1 may be coupled between an input terminal of a reference current IREF and a supply terminal of a low voltage VSS, and generate a bias voltage VBIAS corresponding to the reference current IREF. For example, the first mirror element N1 may include an NMOS transistor having a gate terminal and a drain terminal coupled to an output terminal of the bias voltage VBIAS, and having a source terminal coupled to a supply terminal of the low voltage VSS.

[0060] The first comparator 230_1 may include current supply circuits PM1 and PM2 , input circuits NM1 and NM2 , an enable circuit NM3 , a compensation element NM4 , a current source CS, and switch circuits SW1 and SW2 .

[0061] The current supply circuits PM1 and PM2 may be coupled between a supply terminal of the second high voltage VDD2 and a pair of output terminals ON1 and ON2. A first comparison signal COMP1 may be generated through one output terminal of the pair of output terminals ON1 and ON2.

[0062] The input circuits NM1 and NM2 may be coupled between the pair of output terminals ON1 and ON2 and the common node CN. The input circuits NM1 and NM2 may receive the first pixel signal VPX1 and the ramp signal VRP.

[0063] The enabling circuit NM3 may be coupled between the common node CN and the supply terminal of the low voltage VSS. The enabling circuit NM3 may generate an operating current IN corresponding to the reference current IREF based on the bias voltage VBIAS. For example, the enabling circuit NM3 may include an NMOS transistor having a gate terminal coupled to an output terminal of the bias voltage VBIAS and having a drain terminal and a source terminal coupled between the common node CN and the supply terminal of the low voltage VSS.

[0064] The compensation element NM4 may be coupled between the supply terminal of the second high voltage VDD2 and the output terminal of the bias voltage VBIAS, and compensate the bias voltage VBIAS based on the operation current IN. For example, the compensation element NM4 may include an NMOS transistor having a gate terminal coupled to the common node CN, and having a source terminal and a drain terminal coupled between the supply terminal of the second high voltage VDD2 and the output terminal of the bias voltage VBIAS.

[0065] The enabling circuit NM3 and the compensation element NM4 may be coupled to each other in a nested feedback structure.

[0066] The current source CS may be coupled between the output terminal of the bias voltage VBIAS and the supply terminal of the low voltage VSS. The current source CS may be used to help the compensation element NM4 apply a compensation current to the output terminal of the bias voltage VBIAS.

[0067] The enabling circuit NM3 together with the bias voltage generator 220 may be configured as a mirror circuit MC. That is, the enabling circuit NM3 may be configured as a second mirror element NM3 interconnected with the first mirror element N1. The mirror circuit MC may be coupled between the common node CN and the supply terminal of the low voltage VSS, and by mirroring the reference current IREF, to generate an operating current IN, which flows between the common node CN and the supply terminal of the low voltage VSS. In one embodiment, the mirror circuit MC may compensate the operating current IN based on the operating current IN.

[0068] Hereinafter, the operation of the image sensing device 200 according to the second embodiment having the above-described configuration will be described.

[0069] When the reference current generator 210 generates the reference current IREF, the bias voltage generator 220 may generate a bias voltage VBIAS corresponding to the reference current IREF, and the first to nth comparators 230_1 to 230 — n may be enabled according to the bias voltage VBIAS.

[0070] When the first to nth pixel signals VPX1 to VPXn and the ramp signal VRP are input, the first to nth comparators 230_1 to 230_n may respectively compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP and respectively generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results.

[0071] In one embodiment, the first to nth comparators 230_1 to 230_n may operate simultaneously. That is, the first to nth comparison signals COMP1 to COMPn may be transformed simultaneously or at different times according to the levels of the first to nth pixel signals VPX1 to VPXn, respectively. As the number of comparison signals simultaneously transformed among the first to nth comparison signals COMP1 to COMPn increases, noise may be reflected in the operating current IN flowing through each of the first to nth comparators 230_1 to 230_n. In other words, noise having a positive (+) voltage level or a negative (-) voltage level may be applied to the output terminal of the bias voltage VBIAS. This noise is called band noise. Due to the band noise, the reference current IREF may not have a target level. Because the bias voltage VBIAS does not have a target level due to the reference current IREF not having a target level, the first to nth comparators 230_1 to 230_n may not be able to normally generate the first to nth comparison signals COMP1 to COMPn.

[0072] However, the compensation element NM4 included in each of the first to nth comparators 230_1 to 230_n can sense when the operating current IN does not have a target level and compensate the bias voltage VBIAS. For example, when the reference current IREF changes, the compensation element NM4 can adjust the compensation current applied to the output terminal of the bias voltage VBIAS. When the reference current IREF becomes higher than the target level due to the band noise with a positive (+) voltage level, the compensation element NM4 can apply a relatively low compensation current to the output terminal of the bias voltage VBIAS. On the other hand, when the reference current IREF becomes lower than the target level due to the band noise with a negative (-) voltage level, the compensation element NM4 can apply a relatively high compensation current to the output terminal of the bias voltage VBIAS. Therefore, while the band noise reflected in the operating current IN is offset, the first to nth comparators 230_1 to 230_n can respectively generate the first to nth comparison signals COMP1 to COMPn normally.

[0073] Figure 5 is a block diagram illustrating an image sensing apparatus 300 according to a third embodiment of the present disclosure.

[0074] refer to Figure 5 , the image sensing device 300 may include a reference current generator 310 , first to nth bias voltage generators 320_1 to 320 — n , and first to nth comparators 330_1 to 330 — n .

[0075] The reference current generator 310 may generate a reference current IREF. For example, the reference current generator 310 may include a bandgap reference circuit.

[0076] The first to nth bias voltage generators 320_1 to 320_n may respectively generate first to nth bias voltages VBIAS1 to VBIASn corresponding to the reference current IREF. For example, the first to nth bias voltages VBIAS1 to VBIASn may have the same voltage level. The first to nth bias voltage generators 320_1 to 320_n may respectively compensate the first to nth bias voltages VBIAS1 to VBIASn based on the reference current IREF. In one embodiment, each of the first to nth bias voltage generators 320_1 to 320_n may be coupled between a supply terminal of the first high voltage VDD1 and a supply terminal of the low voltage VSS (reference voltage VDD1). Figure 6 ).

[0077] The first to nth comparators 330_1 to 330_n may be enabled based on the first to nth bias voltages VBIAS1 to VBIASn, respectively. The first to nth comparators 330_1 to 330_n may compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP, respectively, and generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results, respectively. For example, the first comparator 330_1 may be enabled based on the first bias voltage VBIAS1, compare the first pixel signal VPX1 with the ramp signal VRP, and generate a first comparison signal COMP1 corresponding to the comparison result. Although not shown, each of the first to nth comparators 330_1 to 330_n may be coupled between a supply terminal of the second high voltage VDD2 and a supply terminal of the low voltage VSS (reference Figure 6 ). The first high voltage VDD1 and the second high voltage VDD2 may be different voltages or the same voltage.

[0078] Figure 6 It is a graphic Figure 5 2 and 3. A circuit diagram of the first bias voltage generator 320_1 and the first comparator 330_1 is shown in FIG.

[0079] refer to Figure 6 , the first bias voltage generator 320_1 may include a first mirror element N1, a compensation element N2, and a current source CS.

[0080] The first mirror element N1 may be coupled between an input terminal of a reference current IREF and a supply terminal of a low voltage VSS, and generate a first bias voltage VBIAS1 corresponding to the reference current IREF. For example, the first mirror element N1 may include an NMOS transistor having a gate terminal coupled to an output terminal of the first bias voltage VBIAS1, and having a drain terminal and a source terminal coupled between an input terminal of the reference current IREF and a supply terminal of the low voltage VSS.

[0081] The compensation element N2 may be coupled between the supply terminal of the first high voltage VDD1 and the output terminal of the first bias voltage VBIAS1, and compensate the first bias voltage VBIAS1 based on the reference current IREF. For example, the compensation element N2 may include an NMOS transistor having a gate terminal coupled to the input terminal of the reference current IREF, and having a source terminal and a drain terminal coupled between the supply terminal of the first high voltage VDD1 and the output terminal of the first bias voltage VBIAS1.

[0082] The first mirror element N1 and the compensation element N2 may be coupled to each other in a nested feedback structure.

[0083] The current source CS may be coupled between the output terminal of the first bias voltage VBIAS1 and the supply terminal of the low voltage VSS. The current source CS may be used to help the compensation element N2 apply a compensation current to the output terminal of the first bias voltage VBIAS1.

[0084] The first comparator 330_1 may include current supply circuits PM1 and PM2, input circuits NM1 and NM2, an enabling circuit NM3, and switch circuits SW1 and SW2.

[0085] The current supply circuits PM1 and PM2 may be coupled between a supply terminal of the second high voltage VDD2 and a pair of output terminals ON1 and ON2. A first comparison signal COMP1 may be generated through one output terminal of the pair of output terminals ON1 and ON2.

[0086] The input circuits NM1 and NM2 may be coupled between the pair of output terminals ON1 and ON2 and the common node CN. The input circuits NM1 and NM2 may receive the first pixel signal VPX1 and the ramp signal VRP.

[0087] The enabling circuit NM3 may be coupled between the common node CN and the supply terminal of the low voltage VSS. The enabling circuit NM3 may generate an operating current IN corresponding to the reference current IREF based on the first bias voltage VBIAS1. For example, the enabling circuit NM3 may include an NMOS transistor having a gate terminal coupled to an output terminal of the first bias voltage VBIAS1 and having a drain terminal and a source terminal coupled between the common node CN and the supply terminal of the low voltage VSS.

[0088] The enabling circuit NM3 and the first bias voltage generator 320_1 can be configured as a mirror circuit MC. That is, the enabling circuit NM3 can be configured as a second mirror element NM3 interconnected with the first mirror element N1. The mirror circuit MC can be coupled between the common node CN and the supply terminal of the low voltage VSS, and by mirroring the reference current IREF, to generate an operating current IN, which flows between the common node CN and the supply terminal of the low voltage VSS. In one embodiment, the mirror circuit MC can compensate the operating current IN based on the reference current IREF.

[0089] Because each of the second to nth bias voltage generators 320_2 to 320_n can be configured in the same manner as the first bias voltage generator 320_1, and each of the second to nth comparators 330_2 to 330_n can be configured in the same manner as the first comparator 330_1, a detailed description of the second to nth bias voltage generators 320_2 to 320_n and the second to nth comparators 330_2 to 330_n is omitted.

[0090] Although it is described as an example in the present embodiment that n bias voltage generators 320_1 to 320_n and n comparators 330_1 to 330_n are configured, the present disclosure is not limited thereto, and m bias voltage generators 320_1 to 320_m and n comparators 330_1 to 330_n (where "m" is a natural number less than "n") may be configured. For example, when m bias voltage generators 320_1 to 320_m and n comparators 330_1 to 330_n are configured, the bias voltage generators and the comparators may be coupled to each other in a one-to-many relationship.

[0091] Hereinafter, the operation of the image sensing device 300 according to the third embodiment having the above-described configuration will be described.

[0092] When the reference current generator 310 generates the reference current IREF, the first to nth bias voltage generators 320_1 to 320_n may respectively generate first to nth bias voltages VBIAS1 to VBIASn corresponding to the reference current IREF, and the first to nth comparators 330_1 to 330_n may respectively be enabled according to the first to nth bias voltages VBIAS1 to VBIASn.

[0093] When the first to nth pixel signals VPX1 to VPXn and the ramp signal VRP are input, the first to nth comparators 330_1 to 330_n may respectively compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP and respectively generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results.

[0094] In one embodiment, the first to nth comparators 330_1 to 330_n may operate simultaneously. That is, the first to nth comparison signals COMP1 to COMPn may be transformed simultaneously or at different times according to the levels of the first to nth pixel signals VPX1 to VPXn, respectively. As the number of comparison signals simultaneously transformed among the first to nth comparison signals COMP1 to COMPn increases, noise may be reflected in the operating current IN flowing through each of the first to nth comparators 330_1 to 330_n. In other words, noise having a positive (+) voltage level or a negative (-) voltage level may be applied to the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. This noise is called band noise. Due to the band noise, the reference current IREF may not have a target level. Since the first to nth bias voltages VBIAS1 to VBIASn do not have the target level due to the reference current IREF not having the target level, the first to nth comparators 330_1 to 330_n may not normally generate the first to nth comparison signals COMP1 to COMPn.

[0095] However, the compensation element N2 included in each of the first to nth bias voltage generators 320_1 to 320_n can sense when the reference current IREF does not have a target level and compensate the first to nth bias voltages VBIAS1 to VBIASn. For example, when the reference current IREF changes, the compensation element N2 can adjust the compensation current applied to each of the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. When the reference current IREF becomes higher than the target level due to a band noise having a positive (+) voltage level, the compensation element N2 can apply a relatively low compensation current to each of the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. On the other hand, when the reference current IREF becomes lower than the target level due to a band noise having a negative (-) voltage level, the compensation element N2 can apply a relatively high compensation current to each of the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. Therefore, while the band noise reflected in the operating current IN is canceled, the first to nth comparators 330_1 to 330_n may normally generate the first to nth comparison signals COMP1 to COMPn, respectively.

[0096] Figure 7 is a block diagram illustrating an image sensing apparatus 400 according to a fourth embodiment of the present disclosure.

[0097] refer to Figure 7 , the image sensing device 400 may include a reference current generator 410 , first to nth bias voltage generators 420_1 to 420 — n , and first to nth comparators 430_1 to 430 — n .

[0098] The reference current generator 410 may generate a reference current IREF. For example, the reference current generator 410 may include a bandgap reference circuit.

[0099] The first to nth bias voltage generators 420_1 to 420_n may respectively generate first to nth bias voltages VBIAS1 to VBIASn corresponding to the reference current IREF For example, the first to nth bias voltages VBIAS1 to VBIASn may have the same voltage level.

[0100] The first to nth comparators 430_1 to 430_n may be enabled based on the first to nth bias voltages VBIAS1 to VBIASn, respectively. The first to nth comparators 430_1 to 430_n may compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP, respectively, and generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results, respectively. For example, the first comparator 430_1 may be enabled based on the first bias voltage VBIAS1, compare the first pixel signal VPX1 with the ramp signal VRP, and generate the first comparison signal COMP1 corresponding to the comparison result. When each of the first to nth pixel signals VPX1 to VPXn is compared with the ramp signal VRP, the first to nth comparators 430_1 to 430_n may compensate for the first to nth bias voltages VBIAS1 to VBIASn, respectively, based on the operation current IN generated therein.

[0101] Figure 8 It is a graphic Figure 7 2 and 3. A circuit diagram of the first bias voltage generator 420_1 and the first comparator 430_1 is shown in FIG.

[0102] refer to Figure 8 , the first bias voltage generator 420_1 may include a first mirror element N1.

[0103] The first mirror element N1 may be coupled between an input terminal of a reference current IREF and a supply terminal of a low voltage VSS, and generate a first bias voltage VBIAS1 corresponding to the reference current IREF. For example, the first mirror element N1 may include an NMOS transistor having a gate terminal and a drain terminal coupled to an output terminal of the first bias voltage VBIAS1, and having a source terminal coupled to the supply terminal of the low voltage VSS.

[0104] The first comparator 430_1 may include current supply circuits PM1 and PM2, input circuits NM1 and NM2, an enabling circuit NM3, a compensation element NM4, a current source CS, and switch circuits SW1 and SW2.

[0105] The current supply circuits PM1 and PM2 may be coupled between a supply terminal of the second high voltage VDD2 and a pair of output terminals ON1 and ON2. A first comparison signal COMP1 may be generated through one output terminal of the pair of output terminals ON1 and ON2.

[0106] The input circuits NM1 and NM2 may be coupled between the pair of output terminals ON1 and ON2 and the common node CN. The input circuits NM1 and NM2 may receive the first pixel signal VPX1 and the ramp signal VRP.

[0107] The enabling circuit NM3 may be coupled between the common node CN and the supply terminal of the low voltage VSS. The enabling circuit NM3 may generate an operating current IN corresponding to the reference current IREF based on the first bias voltage VBIAS1. For example, the enabling circuit NM3 may include an NMOS transistor having a gate terminal coupled to an output terminal of the first bias voltage VBIAS1 and having a drain terminal and a source terminal coupled between the common node CN and the supply terminal of the low voltage VSS.

[0108] The compensation element NM4 may be coupled between the supply terminal of the second high voltage VDD2 and the output terminal of the first bias voltage VBIAS1, and compensate the first bias voltage VBIAS1 based on the operation current IN. For example, the compensation element NM4 may include an NMOS transistor having a gate terminal coupled to the common node CN, and having a source terminal and a drain terminal coupled between the supply terminal of the second high voltage VDD2 and the output terminal of the first bias voltage VBIAS1.

[0109] The enabling circuit NM3 and the compensation element NM4 may be coupled to each other in a nested feedback structure.

[0110] The current source CS may be coupled between the output terminal of the first bias voltage VBIAS1 and the supply terminal of the low voltage VSS. The current source CS may be used to help the compensation element NM4 apply a compensation current to the output terminal of the first bias voltage VBIAS1.

[0111] The enabling circuit NM3 together with the first bias voltage generator 420 can be configured as a mirror circuit MC. That is, the enabling circuit NM3 can be configured as a second mirror element NM3 interconnected with the first mirror element N1. The mirror circuit MC can be coupled between the common node CN and the supply terminal of the low voltage VSS, and by mirroring the reference current IREF, to generate an operating current IN, which flows between the common node CN and the supply terminal of the low voltage VSS. In one embodiment, the mirror circuit MC can compensate the operating current IN based on the operating current IN.

[0112] Because each of the second to nth bias voltage generators 420_2 to 420_n can be configured in the same manner as the first bias voltage generator 420_1, and each of the second to nth comparators 430_2 to 430_n can be configured in the same manner as the first comparator 430_1, a detailed description of the second to nth bias voltage generators 420_2 to 420_n and the second to nth comparators 430_2 to 430_n is omitted.

[0113] Although it is described as an example in the present embodiment that n bias voltage generators 420_1 to 420_n and n comparators 430_1 to 430_n are configured, the present disclosure is not limited thereto, and m bias voltage generators 420_1 to 420_m and n comparators 430_1 to 430_n (where "m" is a natural number less than "n") may be configured. For example, when m bias voltage generators 420_1 to 420_m and n comparators 430_1 to 430_n are configured, the bias voltage generators and the comparators may be coupled to each other in a one-to-many relationship.

[0114] Hereinafter, the operation of the image sensing device 400 according to the fourth embodiment having the above-described configuration will be described.

[0115] When the reference current generator 410 generates the reference current IREF, the first to nth bias voltage generators 420_1 to 420_n may respectively generate first to nth bias voltages VBIAS1 to VBIASn corresponding to the reference current IREF, and the first to nth comparators 430_1 to 430_n may respectively be enabled according to the first to nth bias voltages VBIAS1 to VBIASn.

[0116] When the first to nth pixel signals VPX1 to VPXn and the ramp signal VRP are input, the first to nth comparators 430_1 to 430_n may respectively compare the first to nth pixel signals VPX1 to VPXn with the ramp signal VRP and respectively generate first to nth comparison signals COMP1 to COMPn corresponding to the comparison results.

[0117] In one embodiment, the first to nth comparators 430_1 to 430_n may operate simultaneously. That is, the first to nth comparison signals COMP1 to COMPn may be transformed simultaneously or at different times according to the levels of the first to nth pixel signals VPX1 to VPXn, respectively. As the number of comparison signals simultaneously transformed among the first to nth comparison signals COMP1 to COMPn increases, noise may be reflected in the operating current IN flowing through each of the first to nth comparators 430_1 to 430_n. In other words, noise having a positive (+) voltage level or a negative (-) voltage level may be applied to the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. This noise is called band noise. Due to the band noise, the reference current IREF may not have a target level. Since the first to nth bias voltages VBIAS1 to VBIASn do not have the target level due to the reference current IREF not having the target level, the first to nth comparators 430_1 to 430_n may not normally generate the first to nth comparison signals COMP1 to COMPn.

[0118] However, the compensation element NM4 included in each of the first to nth comparators 430_1 to 430_n can sense when the operating current IN does not have a target level and compensate the first to nth bias voltages VBIAS1 to VBIASn. For example, when the reference current IREF changes, the compensation element NM4 can adjust the compensation current applied to each of the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. When the reference current IREF becomes higher than the target level due to a band noise having a positive (+) voltage level, the compensation element NM4 can apply a relatively low compensation current to each of the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. On the other hand, when the reference current IREF becomes lower than the target level due to a band noise having a negative (-) voltage level, the compensation element NM4 can apply a relatively high compensation current to each of the output terminals of the first to nth bias voltages VBIAS1 to VBIASn. Therefore, while the band noise reflected in the operating current IN is canceled, the first to nth comparators 430_1 to 430_n may normally generate the first to nth comparison signals COMP1 to COMPn, respectively.

[0119] According to an embodiment of the present disclosure, band noise reflected in the operating current can be suppressed through a nested feedback structure.

[0120] According to the embodiments of the present disclosure, it is possible to prevent degradation of image quality by suppressing band noise occurring in a circuit structure.

[0121] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for illustration only and are not intended to be limiting. In addition, it is noted that, as will be appreciated by those skilled in the art from this disclosure, the present disclosure may be implemented in various ways by substitutions, changes and modifications falling within the scope of the appended claims.

Claims

1. An image sensing device, comprising: A reference current generator, adapted to generate a reference current; at least one bias voltage generator, adapted to generate at least one bias voltage corresponding to the reference current; as well as A plurality of comparators are enabled based on the at least one bias voltage and are adapted to compensate for the bias voltage based on operating currents generated in the plurality of comparators when respectively comparing a plurality of pixel signals with the ramp signal.

2. The image sensing device according to claim 1, wherein each of the comparators comprises: a current supply circuit coupled between a supply terminal of a second high voltage and a pair of output terminals; an input circuit coupled between the pair of output terminals and a common node and adapted to receive each of the pixel signals and the ramp signal; a second mirror element coupled between the common node and a supply terminal of a low voltage and adapted to generate the operating current corresponding to the reference current based on a corresponding bias voltage; a compensation element coupled between the supply terminal of the second high voltage and the output terminal of the corresponding bias voltage and adapted to compensate the bias voltage based on the operating current; as well as A current source is coupled between the output terminal of the corresponding bias voltage and the supply terminal of the low voltage. 3 . The image sensing device of claim 2 , wherein the second mirror element and the compensation element are coupled to each other in a nested feedback structure.

4. The image sensing device according to claim 1, wherein the at least one bias voltage generator comprises a first mirror element, which is coupled between an input terminal of the reference current and a supply terminal of a low voltage and is suitable for generating the bias voltage corresponding to the reference current.

5. An image sensing device, comprising: A generating circuit adapted to generate a bias voltage according to a reference current; a comparison circuit adapted to generate an operation current according to the bias voltage, and compare the pixel signal with a ramp signal based on the operation current to generate a comparison signal; as well as The compensation circuit is adapted to compensate the bias voltage according to one of the reference current and the operating current.

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