Capacitor unit and analog-to-digital converter

Abstract

The invention discloses a capacitor unit. The capacitor unit comprises upper layer metal and M layers of lower layer metal, the upper-layer metal comprises a plurality of upper-layer common-end metal and an upper-layer non-common-end metal; the upper-layer metal common end is located on the outer side, and a plurality of notches are reserved in the periphery; the upper-layer non-common end metal is positioned on the inner side and is arranged in an interdigitated manner with the upper-layer metal common end; the lower-layer metal comprises a lower-layer common end metal and a lower-layer non-common end metal; the lower-layer metal common end is positioned on the outer side and is closed into a ring; and the lower-layer non-common end metal is positioned on the inner side and is arranged in an interdigitated manner with the lower-layer metal common end. According to the capacitor unit and the capacitor array formed by the capacitor unit, the chip area of the capacitor array can be saved, the parasitic capacitance is reduced, the consistency of the capacitors is better, and the matching between the capacitors is better. The invention further discloses an analog-to-digital converter comprising the capacitor array composed of the capacitor units.

Description

Technical Field

[0001] The present invention relates to MOM (Metal-Oxide-Metal) capacitor technology, and in particular to a capacitor unit and an analog-to-digital converter. Background Art

[0002] Capacitor arrays are often used in analog-to-digital converters (ADCs). Capacitor arrays are composed of hundreds or even thousands of capacitor units. Different bits of the ADC correspond to different numbers of unit capacitors, and the ratio between the number of unit capacitors corresponding to different bits usually needs to be accurately determined. One end (upper plate or lower plate) of the capacitor corresponding to all bits is connected together, and the other end is connected to a potential determined by the codeword of the corresponding bit, such as Figure 1 shown.

[0003] The ratio of capacitance values ​​corresponding to different bits directly affects the linearity of the ADC, and the capacitance mismatch caused by various factors will cause deviations in the ratio of the above capacitance values, so the capacitors are required to have a good match. The mismatch between capacitors is divided into random mismatch and systematic mismatch. Random mismatch is usually introduced by process inconsistency, which is difficult to avoid in practice. Its impact can only be reduced by taking reasonable capacitance values ​​or calibration. Systematic mismatch is usually introduced by circuit design and layout, especially the non-uniform parasitic capacitance introduced by layout will introduce significant mismatch. In order to reduce the capacitance ratio mismatch caused by layout, it is usually required that the parasitic capacitance is as small as possible, and there must be an accurate proportional relationship between the parasitic capacitances corresponding to different bits. The capacitor arrays used in most existing ADCs are as follows. Figure 2 The standard MOM (Metal-Oxide-Metal) capacitor shown in the figure includes an upper metal layer, an intermediate oxide layer, and a lower metal layer. The upper metal layer and the lower metal layer are connected by through holes. The connection between the capacitors needs to be realized through additional metal connections and routing channels outside the capacitors. The typical ADC capacitor layout connection is as follows Figure 3 As shown, the red wire is the connection between the upper and lower plates of the capacitor, and the blue area will generate additional parasitic capacitance. The upper and lower plates of the existing standard MOM capacitor unit can only lead the connection from one direction, which causes the connection between the capacitors to occupy additional routing channels, and the above-mentioned additional routing increases the parasitics between the routing and other capacitors, and also increases the complexity of the layout design, which will eventually lead to a waste of area and introduce systematic mismatch between capacitors, thereby increasing the overall cost of the chip and making the linearity of the ADC worse. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a capacitor unit, and a capacitor array composed of the capacitor unit can save the chip area of ​​the capacitor array, reduce parasitic capacitance, improve the consistency of capacitance, and better match between capacitors.

[0005] In order to solve the above technical problems, the present invention provides a capacitor unit, which includes an upper metal layer 1 and M layers of lower metal layers 2, where M is a positive integer;

[0006] The upper metal 1 includes N upper common metal ends 11 and one upper non-common metal end 12, where N is an integer greater than 1; the upper metal common end 11 is located on the outside, with N gaps left on the periphery; the upper non-common metal end 12 is located on the inside, and is arranged in a finger-shaped manner with the upper metal common end 11;

[0007] The lower metal 2 includes a lower common end metal 21 and a lower non-common end metal 22; the lower metal common end 21 is located on the outside and is closed into a ring; the lower non-common end metal 22 is located on the inside and is arranged in a finger-shaped manner with the lower metal common end 21;

[0008] The upper metal common terminal 11 is connected to the lower metal common terminal 21 via a contact hole 33;

[0009] The upper metal non-common terminal 12 is connected to the lower metal non-common terminal 22 via a contact hole 33 .

[0010] Preferably, the upper non-common metal 12 is surrounded by N upper common metals 11, the fingers of the upper common metals 11 face inwards, and the fingers of the upper non-common metals 12 face outwards;

[0011] The lower non-common terminal metal 22 is surrounded by the lower common terminal metal 21 , the insertion fingers of the lower common terminal metal 21 face inwards, and the insertion fingers of the lower non-common terminal metal 22 face outwards.

[0012] Preferably, the upper non-common terminal metal 12 is in a herringbone shape.

[0013] Preferably, the upper common terminal metal 11 is comb-shaped.

[0014] Preferably, the upper common terminal metal 11 is in an "E" shape.

[0015] Preferably, N is 2 or 4.

[0016] Preferably, a finger of an upper layer non-common terminal metal 12 is correspondingly provided at the notch adjacent to any two upper layers of common terminal metals 11 .

[0017] Preferably, M is 1, 2, 3, 4 or 5.

[0018] The present invention also provides an analog-to-digital converter, which comprises a capacitor array composed of the capacitor units.

[0019] The capacitor unit of the present invention is composed of two or more layers of metal, and the metal capacitor plates of the same layer are arranged in a finger-like manner; the lower metal common terminal 21 is located outside the lower metal layer and is closed into a ring, which is used to connect to the common terminal of the capacitor array; the upper metal common terminal 11 has multiple gaps on the periphery to leave a routing channel. The outside of the same layer of metal is the same plate (the common terminal of the capacitor array connected together). When the capacitor unit is seamlessly spliced ​​into a capacitor array, all the outer plates can be connected through the lower metal layer; the other end of the capacitor (non-common terminal) can be connected to multiple directions arbitrarily through the gaps on the periphery of the upper common terminal metal 11. The capacitor array composed of the capacitor units can be seamlessly spliced ​​between different capacitor units through the capacitor unit frame 32, saving chip area; the connection between the non-common end plates of the capacitor array can be realized by using a very small area of ​​the capacitor non-common end connection metal 31, and the common end of the capacitor can be connected through the capacitor itself, reducing the routing channel, saving the chip area of ​​the capacitor array, and reducing parasitic capacitance; because the spacing between capacitors is reduced, the consistency of the capacitors is better; because the parasitic influence of the connection is reduced, the matching between capacitors is better. In the analog-to-digital converter using the capacitor array composed of the capacitor units, the size of the parasitic capacitance formed by the connection of the capacitors corresponding to different bits can be proportional to the number of capacitors, and matching between parasitic capacitors can be achieved, reducing the systematic mismatch caused by parasitic capacitance, and the linearity of the analog-to-digital converter can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a capacitor array circuit diagram that is often used in analog-to-digital converters (ADC);

[0022] Figure 2 It is a schematic diagram of the MOM capacitor structure;

[0023] Figure 3 It is a schematic diagram of the connection of the existing ADC capacitor layout;

[0024] Figure 4 is a schematic structural diagram of a capacitor unit according to an embodiment of the present invention having one layer of lower metal;

[0025] Figure 5is a schematic structural diagram of another embodiment of a capacitor unit of the present invention having two layers of lower metal;

[0026] Figure 6 The present invention is a schematic diagram of the connection of an ADC capacitor layout using a capacitor array formed by the capacitor units of the present invention.

[0027] Description of reference numerals:

[0028] 1. Upper metal layer; 2. Lower metal layer; 11. Upper common metal layer; 12. Upper non-common metal layer; 21. Lower common metal layer; 22. Lower non-common metal layer; 33. Contact hole; 32. Capacitor unit frame; 31. Capacitor non-common connection metal. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Embodiment 1

[0031] A capacitor unit such as Figure 4 , Figure 5 As shown, it includes an upper metal layer 1 and M lower metal layers 2, where M is a positive integer;

[0032] The upper metal 1 includes N upper common metal ends 11 and one upper non-common metal end 12, where N is an integer greater than 1; the upper metal common end 11 is located on the outside, with N gaps left on the periphery; the upper non-common metal end 12 is located on the inside, and is arranged in a finger-shaped manner with the upper metal common end 11;

[0033] The lower metal 2 includes a lower common end metal 21 and a lower non-common end metal 22; the lower metal common end 21 is located on the outside and is closed into a ring; the lower non-common end metal 22 is located on the inside and is arranged in a finger-shaped manner with the lower metal common end 21;

[0034] The upper metal common terminal 11 is connected to the lower metal common terminal 21 via a contact hole 33;

[0035] The upper metal non-common terminal 12 is connected to the lower metal non-common terminal 22 via a contact hole 33 .

[0036] The capacitor unit of the present invention is composed of two or more layers of metal, and the metal capacitor plates of the same layer are arranged in a finger-like manner; the lower metal common terminal 21 is located outside the lower metal layer and is closed into a ring, which is used to connect to the common terminal of the capacitor array; the upper metal common terminal 11 has multiple gaps on the periphery to leave a routing channel. The outside of the same layer of metal is the same plate (the common terminal of the capacitor array connected together). When the capacitor unit is seamlessly spliced ​​into a capacitor array, all the outer plates can be connected through the lower metal layer; the other end of the capacitor (non-common terminal) can be connected to multiple directions arbitrarily through the gaps on the periphery of the upper common terminal metal 11.

[0037] The capacitor unit of the present invention comprises a capacitor array as follows: Figure 6 As shown, different capacitor units can be seamlessly spliced ​​through the capacitor unit frame 32, saving chip area; a very small area of ​​capacitor non-common end connection metal 31 can be used to realize the connection between the non-common end plates of the capacitor array, and the common end of the capacitor can be connected through the capacitor itself, reducing the routing channel, saving the chip area of ​​the capacitor array, reducing parasitic capacitance, and reducing parasitics by more than 90% compared with the connection of traditional capacitors; since the spacing between capacitors is reduced, the consistency of capacitors is better; since the parasitic influence of the connection is reduced, the matching between capacitors is better. The analog-to-digital converter using the capacitor array composed of the capacitor unit, the size of the parasitic capacitance formed by the connection of capacitors corresponding to different bits can be proportional to the number of capacitors, and matching between parasitic capacitors can be achieved, reducing the systematic mismatch caused by parasitic capacitance, and the linearity of the analog-to-digital converter can be improved.

[0038] Embodiment 2

[0039] Based on the capacitor unit of the first embodiment, the upper non-common-end metal 12 is surrounded by N upper common-end metals 11, the insertion fingers of the upper common-end metal 11 face inwards, and the insertion fingers of the upper non-common-end metal 12 face outwards;

[0040] The lower non-common terminal metal 22 is surrounded by the lower common terminal metal 21 , the insertion fingers of the lower common terminal metal 21 face inwards, and the insertion fingers of the lower non-common terminal metal 22 face outwards.

[0041] Preferably, the upper non-common terminal metal 12 is in a herringbone shape.

[0042] Preferably, the upper common terminal metal 11 is comb-shaped.

[0043] Preferably, the upper common terminal metal 11 is in an "E" shape.

[0044] Preferably, N is 2 or 4.

[0045] Preferably, a finger of an upper layer non-common terminal metal 12 is correspondingly provided at the notch adjacent to any two upper layers of common terminal metals 11 .

[0046] Preferably, M is 1, 2, 3, 4 or 5.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A capacitor unit, characterized in that: It includes an upper metal layer (1) and M lower metal layers (2), where M is a positive integer; The upper metal layer (1) comprises N upper metal common terminals (11) and one upper metal non-common terminal (12), where N is an integer greater than 1; the upper metal common terminal (11) is located on the outside, with N notches left on the periphery; the upper metal non-common terminal (12) is located on the inside, and is arranged in a finger-shaped manner with the upper metal common terminal (11); The lower metal layer (2) comprises a lower common end metal (21) and a lower non-common end metal (22); the lower metal common end (21) is located on the outside and is closed into a ring; the lower non-common end metal (22) is located on the inside and is arranged in a finger-shaped manner with the lower metal common end (21); The upper metal common terminal (11) and the lower metal common terminal (21) are connected via a contact hole (33); The upper metal non-common end (12) and the lower metal non-common end (22) are connected via a contact hole (33).

2. The capacitor unit according to claim 1, characterized in that: The upper non-common-end metal (12) is surrounded by N upper common-end metals (11), the insertion fingers of the upper common-end metal (11) face inwards, and the insertion fingers of the upper non-common-end metal (12) face outwards; The lower layer non-common terminal metal (22) is surrounded by the lower layer common terminal metal (21), the insertion fingers of the lower layer common terminal metal (21) face inwards, and the insertion fingers of the lower layer non-common terminal metal (22) face outwards.

3. The capacitor unit according to claim 1, characterized in that: The upper non-common terminal metal (12) is in a fishbone shape.

4. The capacitor unit according to claim 1, characterized in that: The upper common terminal metal (11) is in a comb shape.

5. The capacitor unit according to claim 1, characterized in that: The upper common terminal metal (11) is in an "E" shape.

6. The capacitor unit according to claim 1, characterized in that: N is 2 or 4.

7. The capacitor unit according to claim 1, characterized in that: A finger of an upper layer non-common end metal (12) is correspondingly provided at the notch adjacent to the outer periphery of any two upper layers of common end metal (11).

8. The capacitor unit according to claim 1, characterized in that: M is 1, 2, 3, 4 or 5.

9. An analog-to-digital converter, characterized in that: A capacitor array comprising the capacitor units according to any one of claims 1 to 8.

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