A planar power diode

Abstract

The present application relates to a kind of plane power diode, belong to the field of semiconductor power device.The diode includes: substrate area;Drift region is located in the surface of substrate area;Second electrode semiconductor region is located in drift region;Terminal voltage resistance zone is located in drift region and is distributed in the two sides of second electrode semiconductor region;Second electrode metal region lower part is located in the upper surface of second electrode semiconductor region and terminal voltage resistance zone;Second electrode metal region middle part is located in the upper surface of second electrode metal region lower part;Second electrode metal region upper part is located in the upper surface of second electrode metal region middle part;First insulating passivation layer is located in the upper surface of terminal voltage resistance zone and drift region and is distributed in the two sides of second electrode metal region lower part;Second insulating passivation layer is located between the upper surface of first insulating passivation layer and second electrode metal region upper part and is distributed in the two sides of second electrode metal region middle part;First electrode metal region is located in the lower surface of substrate area.The present application can shorten the length of package lead or copper band, reduce space occupation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices and relates to a planar power diode. Background Technology

[0002] Power diodes are indispensable basic electronic components in power electronic systems and are among the most widely used power semiconductor devices, primarily serving rectification and freewheeling functions. In practical applications, power diodes can appear as single transistors or in modules. A single transistor typically contains only one power diode chip; while a module often includes multiple chips, such as a single-phase full-bridge rectifier module containing four power diode chips; in some switching power modules, power diode chips and power switching transistor chips are used together. Regardless of whether it is a single transistor or a module, the electrodes on the surface of the power diode chip need to be connected to the electrodes of other chips or the leads of the casing, often using wire bonding or copper strip bonding. Due to limitations such as electrical isolation and manufacturing processes, longer wires or copper strips occupy space and introduce parasitic inductance, thus affecting switching speed and increasing switching losses. Therefore, advanced packaging technology continuously shortens the length of wires or copper strips to reduce device area and parasitic inductance. However, shortening the length of wires or copper strips affects the chip's breakdown voltage.

[0003] Power diodes often need to withstand high voltages. Therefore, in addition to the active region used for conduction, power diode chips typically have terminating voltage withstand regions around the active region. The terminating voltage withstand regions of power diode chips can be structurally divided into two types: mesa-type and planar-type. Planar-type terminating voltage withstand regions are simpler to manufacture and compatible with the active region manufacturing process, making them more widely used. When a power diode chip is subjected to a reverse high voltage, the planar-type terminating voltage withstand region absorbs the high voltage distributed along its surface. This high voltage not only appears inside and on the surface of the chip but also forms an electric field above the terminating voltage withstand region. Conductive materials such as metals (e.g., leads and copper strips) above the terminating voltage withstand region affect the electric field distribution, ultimately affecting the chip's breakdown voltage. Therefore, during wire bonding for packaging, the leads or copper strips are often curved to maintain a certain distance from the chip's terminating voltage withstand region, avoiding interference with the chip's breakdown voltage. However, curved leads or copper strips increase length, thus occupying more space. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a planar power diode that, by setting a shielding structure on the terminal withstand voltage region of the chip, avoids affecting the terminal withstand voltage region of the power diode chip while shortening the length of the package leads or copper strip.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A planar power diode, comprising:

[0007] Substrate region of the first conductivity type;

[0008] A drift region of the first conductivity type located on the upper surface of the substrate region;

[0009] The second electrode semiconductor region of the second conductivity type is located in the drift region;

[0010] A second conductivity type terminal withstand voltage region located in the drift region and distributed on both sides of the second electrode semiconductor region;

[0011] The lower part of the second electrode metal region is located on the upper surface of the second electrode semiconductor region and the terminal withstand voltage region;

[0012] The middle part of the second electrode metal region is located on the upper surface of the lower part of the second electrode metal region;

[0013] The upper part of the second electrode metal region is located on the upper surface of the middle part of the second electrode metal region;

[0014] The first insulating passivation layer is located on the upper surface of the terminal withstand voltage region and the drift region and is distributed on both sides of the lower part of the second electrode metal region;

[0015] The second insulating passivation layer is located between the upper surface of the first insulating passivation layer and the upper part of the second electrode metal region, and is distributed on both sides of the middle part of the second electrode metal region.

[0016] The first electrode metal region is located on the lower surface of the substrate region.

[0017] Furthermore, the upper part of the second electrode metal region completely covers the top surface of the planar power diode, thereby forming an equipotential surface.

[0018] Furthermore, the central part of the second electrode metal region is rectangular or inverted trapezoidal.

[0019] Furthermore, the second electrode semiconductor region may be a single integral structure or multiple dispersed regions separated by drift regions.

[0020] Furthermore, the terminal pressure-resistant area is either an integral structure or a series of dispersed terminal rings, which are separated by a drift region.

[0021] The beneficial effects of this invention are as follows: By introducing a second insulating passivation layer and a second electrode surface metal layer to form a metal shielding structure for the terminal withstand voltage region, this invention can effectively eliminate the influence of package leads or copper strips on the terminal withstand voltage region of the power diode chip, ensuring that the chip's breakdown voltage is not disturbed. Compared with conventional planar power diode structures, this invention can further shorten the length of package leads or copper strips, and may even eliminate the need for wire bonding, thereby reducing the area occupied by the chip package leads and the parasitic inductance introduced by the leads. The planar power diode proposed in this invention is particularly suitable for compact power electronic circuits and systems.

[0022] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0024] Figure 1 This is a schematic diagram of the planar power diode structure provided in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of the planar power diode structure provided in Embodiment 2 of the present invention;

[0026] Figure 3 This is a schematic diagram of the planar power diode structure provided in Embodiment 3 of the present invention;

[0027] Figure 4 This is a schematic diagram of the planar power diode structure provided in Embodiment 4 of the present invention.

[0028] Reference numerals: 1-First electrode metal region; 2-Second electrode metal region; 3-Substrate region; 4-Drift region; 5-Second electrode semiconductor region; 6-Terminal withstand voltage region; 7-First insulating passivation layer; 8-Second insulating passivation layer. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0030] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0031] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0032] This invention provides a planar power diode structure. Through a terminal metal shielding technology, the influence of package leads or copper strips on the terminal withstand voltage region of the power diode chip can be effectively eliminated, ensuring that the chip's breakdown voltage is not disturbed. This allows for further shortening of the length of package leads or copper strips, or even eliminating the need for wire bonding, thereby reducing the volume occupied by the chip package leads and the parasitic inductance introduced by the leads. Several embodiments are described in detail below for the planar power diode.

[0033] Example 1

[0034] like Figure 1 The diagram shows a planar power diode provided in this embodiment, which includes:

[0035] The first type of semiconductor heavily doped substrate region 3;

[0036] A first electrode metal region 1 is located below the substrate region 3, and the first electrode metal region 1 is in contact with the substrate region 3;

[0037] A lightly doped semiconductor drift region 4 of the first conductivity type is located on the substrate region 3 and is in contact with the substrate region 3;

[0038] A second electrode semiconductor region 5 of a second conductivity type and a second terminal withstand voltage region 6 of a second conductivity type are provided inside the drift region 4. The terminal withstand voltage region 6 is divided into two parts and located on both sides of the second electrode semiconductor region 5, and the two parts are in contact.

[0039] The second electrode metal region 2 is located above the second electrode semiconductor region 5 and the terminal withstand voltage region 6. The second electrode metal region 2 completely covers the upper surface of the second electrode semiconductor region 5 and partially covers the upper surface of the terminal withstand voltage regions 6 on both sides. The second electrode metal region 2 is divided into three parts: upper, middle and lower, and is in the shape of an inverted "I". The upper part is the longer end of the "I" and completely covers the top of the diode device. The middle part is the vertical line in the middle of the "I". The lower part is the shorter end of the "I" and completely covers the upper surface of the second electrode semiconductor region 5 and partially covers the upper surface of the terminal withstand voltage regions 6 on both sides.

[0040] The first insulating passivation layer 7 is located on the upper surface of the terminal withstand voltage region 6 and the drift region 4, and is distributed on both sides of the second electrode metal region 2, wherein the first insulating passivation layer 7 is embedded in the lower part of the second electrode metal region 2.

[0041] And a second insulating passivation layer 8 located between the upper surface of the first insulating passivation layer 7 and the upper part below the second electrode metal region 2, and distributed on both sides of the middle part of the second electrode metal region 2, the second insulating passivation layer 8 being in contact with the second electrode metal region 2 and the first insulating passivation layer 7 respectively.

[0042] In this embodiment, by introducing a thicker second insulating passivation layer 8 into the planar power diode chip, and simultaneously thickening the second electrode metal region 2 and extending the second electrode metal region 2 to the entire chip surface, the chip surface becomes an equipotential surface. Therefore, when the power diode is subjected to a reverse high voltage, the electric field above the chip terminal withstand voltage region 6 is confined within the insulating passivation layer and determined by the thickness and dielectric constant of the insulating passivation layer. Based on the insulating passivation layer, the effect of connecting metal lines (such as leads, copper strips, etc.) passing through the chip surface on the electric field in the terminal withstand voltage region 6 can be shielded, ensuring that the chip's breakdown voltage is not affected.

[0043] It is important to note that the thickness of the second insulating passivation layer 8 should be set appropriately to ensure that it is not broken down by reverse high voltage, thereby maintaining safe and reliable operation.

[0044] In this embodiment, when the first conductivity type is N-type, the second conductivity type is P-type, the first electrode is the cathode, and the second electrode is the anode; when the first conductivity type is P-type, the second conductivity type is N-type, the first electrode is the anode, and the second electrode is the cathode.

[0045] In this embodiment, the semiconductor region can be made of silicon, or it can be made of germanium, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, diamond, or aluminum nitride, etc.

[0046] In this embodiment, the terminal pressure-resistant zone can be a floating field limiting ring, a junction terminal extension, a field plate, or a combination of a floating field limiting ring, a junction terminal extension, and a field plate.

[0047] Example 2

[0048] In this embodiment, the middle part of the second electrode metal region 2 is inverted trapezoidal, such as... Figure 2 As shown. The apex angle of the trapezoid needs to be set appropriately to avoid affecting the electric field distribution inside the second insulating passivation layer 8.

[0049] Example 3

[0050] In this embodiment, the second electrode semiconductor region 5 is configured as multiple dispersed regions distributed between the two terminal withstand voltage regions 6, such as... Figure 3 As shown, except for the second electrode semiconductor regions on both sides which are in contact with the terminal withstand voltage region, the remaining second electrode semiconductor regions are all surrounded by the drift region 4. In addition, the second electrode metal region 2 completely covers all the second electrode semiconductor regions.

[0051] Example 4

[0052] In this embodiment, the terminal withstand voltage region 6 is configured as multiple terminal rings of the second conductivity type distributed on both sides of the second electrode semiconductor region 5, such as... Figure 4 As shown, except for the first ring, which serves as the main junction and is connected to the second electrode semiconductor region 5, the remaining terminal rings are all surrounded by the drift region 4. Specifically, a portion of the first ring, which serves as the main junction, is covered by the second electrode metal region 2, while a portion of the first ring, which serves as the main junction, and the remaining terminal rings are covered by the first insulating passivation layer 7.

[0053] It should be noted that the above embodiments are only used to illustrate the structure of the planar power diode proposed in this invention, and should not be regarded as a limitation on the structure of the planar power diode. Besides the above embodiments, the planar power diode proposed in this invention can also have other structures. For example, in a specific embodiment of a planar power diode, the middle part of its second electrode metal region 2 is inverted trapezoidal, and its second electrode semiconductor region 5 is a plurality of dispersed regions distributed between the two terminal withstand voltage regions 6. As another example, in a specific embodiment of a planar power diode, the middle part of its second electrode metal region 2 is inverted trapezoidal, and its terminal withstand voltage region 6 is a plurality of terminal rings of a second conductivity type uniformly distributed on both sides of the second electrode semiconductor region 5. Alternatively, in a specific embodiment of a planar power diode, the second electrode semiconductor region 5 is a plurality of dispersed regions, and the terminal withstand voltage region 6 is a plurality of terminal rings of a second conductivity type distributed on both sides of the second electrode semiconductor region 5.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A planar power diode, characterized in that, It includes: Substrate region of the first conductivity type; A drift region of the first conductivity type located on the upper surface of the substrate region; The second electrode semiconductor region of the second conductivity type is located in the drift region; A second conductivity type terminal withstand voltage region located in the drift region and distributed on both sides of the second electrode semiconductor region; The lower part of the second electrode metal region is located on the upper surface of the second electrode semiconductor region and the terminal withstand voltage region; The middle part of the second electrode metal region is located on the upper surface of the lower part of the second electrode metal region; The upper part of the second electrode metal region is located on the upper surface of the middle part of the second electrode metal region; A first insulating passivation layer located on the upper surface of the terminal withstand voltage region and drift region and distributed on both sides of the lower part of the second electrode metal region; The second insulating passivation layer is located between the upper surface of the first insulating passivation layer and the upper part of the second electrode metal region, and is distributed on both sides of the middle part of the second electrode metal region. The upper part of the second electrode metal region completely covers the top surface of the planar power diode, that is, completely covers the second insulating passivation layer. The first electrode metal region is located on the lower surface of the substrate region; The metal shielding structure, which forms the terminal withstand voltage region above the second electrode metal region that completely covers the second insulating passivation layer, eliminates the influence of the package leads or copper strip on the terminal withstand voltage region of the diode, ensuring that the breakdown voltage of the diode is not disturbed, and reduces the area occupied by the diode package leads and the parasitic inductance introduced by the leads.

2. The planar power diode according to claim 1, characterized in that, The second electrode metal region has a rectangular shape in the middle.

3. The planar power diode according to claim 1, characterized in that, The middle part of the metal region of the second electrode is inverted trapezoidal.

4. The planar power diode according to claim 1, characterized in that, The second electrode semiconductor region is a plurality of dispersed regions, which are separated by the drift region.

5. The planar power diode according to claim 1, characterized in that, The terminal withstand pressure zone consists of multiple dispersed terminal rings, which are separated by the drift zone.

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