Post-annealing optimization method of thin film transistor based on high-k gate dielectric and IGTO structure
By adopting high-k gate dielectric HfLaO and IGTO structures in thin film transistors and performing post-annealing optimization treatment, the problems of stability and tunneling effects of traditional Si/SiO2 structure in small-sized transistors are solved, and high performance and low power consumption are achieved.
Patent Information
- Application Number
- CN202411806493.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-04-11
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
As the transistor size shrinks, traditional Si/SiO2 structures are difficult to meet the needs of low power consumption and high performance, and the mechanical and chemical stability of the gate oxide layer decreases, resulting in a decrease in device reliability and a significant tunneling effect.
Thin film transistors with high k gate dielectric HfLaO and IGTO structures are used to form high k gate dielectric layer and IGTO channel layer through post-annealing optimization method to control the charge of the channel layer, improve electrical performance, and improve mobility through annealing treatment.
It significantly improves gate capacitance, reduces leakage current, enhances the thermal stability and reliability of the device, improves electrical performance, and reduces power consumption.
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Figure CN119815853A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor material technology, and in particular relates to a post-annealing optimization method for a thin film transistor based on a high-k gate dielectric and an IGTO structure. Background Art
[0002] As Moore's Law continues to drive the size of silicon-based transistors, this trend has led to a rapid increase in computing performance, but it has also posed unprecedented challenges to the manufacturing and design of semiconductor devices. As a key component in transistors, the continuous reduction in the thickness of the gate oxide layer has directly led to a series of problems such as increased tunneling current, increased power consumption, and reduced reliability.
[0003] The traditional Si / SiO2 structure has been unable to meet the future device's demand for low power consumption and high performance in the context of the continuous reduction in transistor size. As the size of the transistor decreases, the thickness of the gate oxide layer also needs to be reduced accordingly to maintain the performance of the device. However, when the thickness of the gate oxide layer is reduced to a certain extent, its mechanical stability and chemical stability will be affected, resulting in a decrease in the reliability of the device. In the Si / SiO2 structure, the tunneling effect is an unavoidable problem. As the size of the transistor decreases, the tunneling effect becomes more and more obvious, making it difficult to control the performance and power consumption of the device. Summary of the invention
[0004] In response to the problems existing in the above-mentioned related technologies, the embodiments of the present application provide a post-annealing optimization method for a thin film transistor based on a high-k gate dielectric and an IGTO structure. By combining the high-k gate material with the oxide semiconductor IGTO, the charge of the channel layer can be effectively controlled, the electrical performance of the device can be improved, and power consumption can be reduced. At the same time, through post-annealing treatment, the mobility can be improved to further improve the device performance.
[0005] In a first aspect, the present application embodiment provides a post-annealing optimization method for a thin film transistor based on a high-k gate dielectric and an IGTO structure, comprising the following steps:
[0006] A HfLaO film is deposited on the surface of the substrate by sputtering La target and Hf target simultaneously to form a high-k gate dielectric layer;
[0007] sputtering an IGTO film on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited, using an IGTO target to form an IGTO film, to form a channel layer; and
[0008] The substrate after the IGTO film is deposited is subjected to annealing treatment.
[0009] Furthermore, the annealing treatment of the substrate after the IGTO film is deposited comprises:
[0010] The substrate after the IGTO film is deposited is placed in an annealing furnace for annealing treatment. The annealing atmosphere is air, the annealing temperature is 250 degrees Celsius, and the annealing time is 1 hour.
[0011] Furthermore, before annealing the substrate after depositing the IGTO film, the method further comprises:
[0012] The substrate after the IGTO film is deposited is subjected to plasma treatment.
[0013] Furthermore, the method of simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a high-k gate dielectric layer includes:
[0014] The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.
[0015] Furthermore, before the HfLaO film is deposited on the substrate surface by sputtering using a La target and a Hf target simultaneously to form a high-k gate dielectric layer, the method further includes:
[0016] A P-type heavily doped Si material is used as a substrate and the substrate is cleaned, and the P-type heavily doped Si is selected as a gate electrode layer.
[0017] Furthermore, the method of depositing an IGTO film by sputtering an IGTO target on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited to form a channel layer comprises:
[0018] The IGTO film is deposited on the surface of the high-k gate dielectric layer of the HfLaO film by sputtering using an IGTO target using a magnetron sputtering method to form the channel layer.
[0019] Further, after the IGTO film is deposited on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited by sputtering using an IGTO target to form a channel layer, the method further includes:
[0020] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.
[0021] In the second aspect, an embodiment of the present application also provides a thin film transistor based on a high-k gate dielectric and an IGTO structure, which is manufactured by a method as described in any of the above items, wherein the thin film transistor includes a gate dielectric layer and a channel layer, wherein the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of a high-K gate dielectric, and the channel layer is made of In-doped IGTO.
[0022] Furthermore, the gate dielectric layer is made of HfLaO.
[0023] Furthermore, it also includes a substrate, a gate electrode layer, a source electrode and a drain electrode, the substrate is arranged below the gate electrode layer, the substrate is made of P-type heavily doped Si, the gate electrode layer is arranged below the gate dielectric layer, the gate electrode layer is made of P-type heavily doped Si, and the source electrode and the drain electrode are arranged above the channel layer.
[0024] The post-annealing optimization method of the thin film transistor based on the high-k gate dielectric and IGTO structure provided in the embodiment of the present application forms a three-terminal transistor device with a bottom gate structure by setting a high-k gate dielectric layer HfLaO and a channel layer of the IGTO film. The thin film transistor provided in the embodiment of the present application uses the high-k material HfLaO as the gate dielectric, which can significantly improve the gate capacitance, reduce the leakage current, and enhance the thermal stability and reliability of the device. The high-k material HfLaO is combined with the new oxide semiconductor IGTO to more effectively control the charge of the channel layer, significantly improve the electrical performance, and significantly reduce the power consumption. In addition, the substrate after the IGTO film is deposited is post-annealed, which can activate impurity atoms in terms of electrical performance to regulate the conductivity type and resistivity, reduce carrier scattering and increase mobility to improve device performance, and can eliminate lattice defects and restore integrity in the crystal structure, thereby improving related performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.
[0026] Figure 1 A schematic flow chart of a post-annealing optimization method for a thin film transistor provided in an embodiment of the present application;
[0027] Figure 2 for Figure 1 Schematic diagram of device output characteristics and transfer comparison of selected thin film transistor arrays prepared by the post-annealing optimization method;
[0028] Figure 3 for Figure 1 Schematic diagram of AFM surface morphology characterization comparison of thin film transistors prepared by post-annealing optimization method;
[0029] Figure 4 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application.
[0030] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0032] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.
[0033] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, the singular forms of "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.
[0034] Reference Figure 1 A post-annealing optimization method for a thin film transistor based on a high-k gate dielectric and an IGTO structure comprises the following steps:
[0035] S101: sputtering and depositing a HfLaO (lanthanum-doped hafnium-based oxide) thin film on the surface of the substrate using a La target and a Hf target simultaneously to form a high-k gate dielectric layer;
[0036] S102: sputtering an IGTO (gallium indium tin oxide) film on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited, using an IGTO target to form an IGTO film to form a channel layer; and
[0037] S103: Annealing the substrate after the IGTO film is deposited.
[0038] Specifically, the post-annealing optimization method of the thin film transistor based on the high-k gate dielectric and IGTO structure provided in the embodiment of the present application forms a three-terminal transistor device with a bottom gate structure by setting a high-k gate dielectric layer HfLaO and a channel layer of the IGTO film. The thin film transistor provided in the embodiment of the present application uses the high-k material HfLaO as the gate dielectric, which can significantly improve the gate capacitance, reduce the leakage current, and enhance the thermal stability and reliability of the device. The high-k material HfLaO is combined with the new oxide semiconductor IGTO to more effectively control the charge of the channel layer, significantly improve the electrical performance, and significantly reduce the power consumption. In addition, the substrate after the IGTO film is deposited is post-annealed, which can activate impurity atoms in terms of electrical performance to regulate the conductivity type and resistivity, reduce carrier scattering and increase mobility to improve device performance, and eliminate lattice defects and restore integrity in the crystal structure, thereby improving related performance. It can also relieve internal and interface stress to avoid structural problems, optimize the band structure to facilitate carrier transmission, and help enhance process compatibility and repeatability to facilitate large-scale production, and can optimize physical properties to pave the way for subsequent process development.
[0039] Further, in some embodiments of the present application, the annealing treatment of the substrate after the IGTO film is deposited includes:
[0040] The substrate after the IGTO film is deposited is placed in an annealing furnace for annealing treatment. The annealing atmosphere is air, the annealing temperature is 250 degrees Celsius, and the annealing time is 1 hour.
[0041] Reference Figure 2 , Figure 2 The output characteristics and transfer comparison diagram of the selected devices of the thin film transistor array prepared by the post-annealing optimization method provided in the embodiment of the present application, the left figure a and c are the output and transfer curves of the unannealed device, and the right figure b and d are the output and transfer curves of the device after annealing at 250 degrees Celsius in air atmosphere for 1 hour. Figure 2 It can be seen that the thin film transistor based on high-k gate dielectric and IGTO structure prepared by the post-annealing optimization method provided in the embodiment of the present application has good electrical characteristics.
[0042] Reference Figure 3 , Figure 3 A schematic diagram of the comparison of the AFM (Atomic Force Microscope) surface morphology characterization prepared by the post-annealing optimization method provided in the embodiment of the present application, the left figure a is the AFM morphology characterization of the unannealed device, and the right figure b is the AFM morphology characterization of the device annealed for 1 hour at 250 degrees Celsius in an air atmosphere. The comparison results show that the surface roughness of the IGTO film after annealing is lower and there are fewer defects, which optimizes the interface characteristics of the subsequent channel layer and the gate dielectric.
[0043] The above test results show that the thin film transistor based on high-k gate dielectric and IGTO prepared in the embodiment of the present application has the advantages of good field effect and low threshold voltage, and combines the advantages of high-k gate dielectric and new oxide semiconductor IGTO.
[0044] Furthermore, in some embodiments of the present application, before annealing the substrate after depositing the IGTO film, the method further includes:
[0045] The substrate after the IGTO film is deposited is subjected to plasma treatment.
[0046] Specifically, before annealing the substrate after the IGTO film is deposited, the substrate after the IGTO film is deposited needs to be placed in a plasma treatment machine for plasma treatment, and the plasma treatment is carried out in an Ar atmosphere with a power of 50 W and a treatment time of 1 minute. The plasma cleaning process is used to remove stains and impurities on the chip surface, improve surface activity, and ensure device performance.
[0047] Similarly, after the HfLaO thin film is deposited on the substrate surface by sputtering La target and Hf target simultaneously to form a high-k gate dielectric layer, the substrate after the IGTO thin film is deposited needs to be placed in a plasma treatment machine for plasma treatment. The plasma treatment is carried out in an O2 atmosphere with a power of 50W and a treatment time of 1 minute. The plasma cleaning process is used to remove stains and impurities on the chip surface, improve surface activity, and ensure device performance.
[0048] Furthermore, in some embodiments of the present application, the method of simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a high-k gate dielectric layer includes:
[0049] The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.
[0050] Specifically, in the above steps, the vacuum degree of the chamber where the thin film is grown is less than 10 -4 Pa, working pressure is 1Pa, La target sputtering power is 45W, Hf target sputtering power is 8W; sputtering gas Ar is introduced with a flow rate of 24sccm; sputtering gas N2 is introduced with a flow rate of 1sccm; reaction gas O2 is introduced with a flow rate of 6sccm; sputtering time is 6000s.
[0051] Furthermore, in some embodiments of the present application, before simultaneously sputtering and depositing a HfLaO film on the substrate surface using a La target and a Hf target to form a high-k gate dielectric layer, the method further includes:
[0052] A P-type heavily doped Si material is used as a substrate and the substrate is cleaned, and the P-type heavily doped Si is selected as a gate electrode layer.
[0053] Specifically, a P-type heavily doped Si material is used as a substrate and placed in an ultrasonic instrument and ultrasonically cleaned for 15 minutes using anhydrous ethanol and deionized water, respectively, and then the P-type heavily doped Si is selected as a gate electrode. In semiconductor technology, substrate cleaning is a crucial step. The purpose of cleaning is to remove contaminants on the surface of the substrate, which may include dust, grease, metal ions, organic matter, etc. These contaminants will affect the quality of subsequent process steps, such as photolithography, etching, ion implantation, etc., thereby affecting the performance and reliability of the final device.
[0054] The cleaning step usually includes multiple sub-steps, such as chemical cleaning (using acidic or alkaline solutions to remove organic matter and metal ions), physical cleaning (using ultrasonic or sandblasting to remove solid particles), deionized water rinsing (removing residual chemicals and ions), etc. The specific methods and steps of cleaning depend on the type of substrate material, the type and concentration of contaminants, and the requirements of subsequent processes.
[0055] Placing the substrate in an ultrasonicator and using anhydrous ethanol and deionized water for ultrasonic cleaning in sequence can ensure that the substrate surface is thoroughly cleaned. This step is crucial in semiconductor processing because it directly affects the quality of subsequent process steps and the performance of the final device.
[0056] After cleaning, the substrate usually needs to be dried to ensure that there is no residual moisture on the surface of the substrate. The drying method may include natural drying, hot air drying or vacuum drying, etc. The specific method depends on the type of substrate material and the requirements of the subsequent process.
[0057] Further, in some embodiments of the present application, the step of sputtering an IGTO film on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited by using an IGTO target to form a channel layer comprises:
[0058] The IGTO film is deposited on the surface of the high-k gate dielectric layer of the HfLaO film by sputtering using an IGTO target using a magnetron sputtering method to form the channel layer.
[0059] Specifically, an IGTO film is deposited on the surface of the HfLaO film located above the substrate by sputtering using an IGTO target to form a channel layer. During the sputtering, the vacuum degree of the cavity in which the film is grown is less than 10 -4 Pa, working pressure is 1Pa, IGTO target sputtering power is 60W; sputtering gas Ar is introduced with a flow rate of 20sccm; reaction gas O2 is introduced with a flow rate of 1sccm; sputtering time is 2000s.
[0060] It should be noted that the substrate surface after the IGTO film is deposited is treated with argon plasma. Argon plasma treatment can cause lattice vibration and structural reorganization on the surface, reduce lattice defects and scattering centers, improve contact with subsequent electrodes, and enhance the mobility of the device. Specifically, the substrate after the IGTO film is deposited is placed in a plasma treatment machine for plasma treatment; the plasma treatment is carried out in an Ar atmosphere, with a power of 50W and a treatment time of 1 minute.
[0061] Furthermore, in some embodiments of the present application, after the IGTO film is deposited on the surface of the high-k gate dielectric layer after the HfLaO film is deposited, the method further includes:
[0062] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.
[0063] Specifically, an electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation, and then an Au film is deposited on the Ti film by electron beam evaporation to form a source-drain electrode. The source-drain electrode is rectangular in shape, 300 μm long and 100 μm wide, and the channel length of the final thin-film transistor is 40 μm.
[0064] In addition, refer to Figure 4 The embodiment of the present application proposes a thin film transistor 100 based on a high-k gate dielectric and an IGTO structure, including a gate dielectric layer 110 and a channel layer 120, wherein the gate dielectric layer 110 is arranged below the channel layer 120, the gate dielectric layer 110 is made of a high-k gate dielectric, and the channel layer 120 is made of an IGTO thin film.
[0065] Specifically, Figure 1As shown, the gate dielectric layer 110 is made of a high-k gate dielectric. High-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium-based oxides (such as HfO2), aluminum-based oxides (Al2O3) and zirconium-based oxides (ZrO2). The characteristics of high-k materials include higher dielectric constants, good thermal stability and wide band gaps, which enable them to perform well in semiconductor devices. The channel layer 120 is made of IGTO, which can improve the mobility of the device. The thin-film transistor 100 provided in the embodiment of the present application uses a high-k material as the gate dielectric layer 110, which can significantly improve the gate capacitance, reduce leakage current, and enhance the thermal stability and reliability of the device. By combining the high-k material with the channel layer 120 of the oxide semiconductor IGTO, the charge of the channel layer 120 can be effectively controlled, its electrical performance can be improved, and power consumption can be reduced.
[0066] Further, refer again to Figure 1 In some embodiments of the present application, the gate dielectric layer 110 is made of HfLaO.
[0067] As mentioned above, high-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium-based oxides (such as HfO2), aluminum-based oxides (Al2O3) and zirconium-based oxides (ZrO2). The characteristics of high-k materials include higher dielectric constants, good thermal stability and wide band gaps, which enable them to perform well in semiconductor devices. The gate dielectric layer 110 of the thin film transistor 100 provided in the embodiment of the present application is preferably made of HfLaO.
[0068] In addition, in some embodiments of the present application, the gate dielectric layer 110 is preferably 90 nm thick, and the gate dielectric layer 100 is moderately thick to avoid large device leakage or weakened gate control capability. The channel layer 120 is an IGTO film, and the thickness is preferably 30 nm.
[0069] Furthermore, if Figure 1 As shown, in some embodiments of the present application, the thin film transistor 100 proposed in the embodiments of the present application also includes a substrate, a gate electrode layer 130, a source electrode (Source) 140 and a drain electrode (Drain) 150, the substrate is made of P-type heavily doped Si, the gate electrode layer 130 is arranged below the gate dielectric layer 100, the gate electrode layer 130 is made of P-type heavily doped Si, and the source electrode 140 and the drain electrode 150 are arranged above the channel layer.
[0070] Specifically, the gate electrode layer 130 controls the current between the drain and the source by changing the gate voltage. When the gate voltage is zero or negative, the channel is in a closed state, and the current between the drain and the source is almost zero. When the gate voltage increases to a certain value, the channel opens, allowing current to pass. The gate electrode layer 130 of the thin film transistor provided in the embodiment of the present application is made of P-type heavily doped Si.
[0071] Specifically, the source electrode 140 is an input terminal of current, carriers (electrons or holes) enter from the source electrode, and the drain electrode 150 is an output terminal of current, carriers are discharged from the drain electrode 150 . The source electrode 140 and the drain electrode 150 are arranged above the channel layer 120 .
[0072] Specifically, the main function of the substrate is to connect various parts of the transistor and play a role of stability and support. The substrate of the thin film transistor 100 provided in the embodiment of the present application is arranged below the gate electrode layer 130, and the substrate is made of P-type heavily doped Si.
[0073] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A post-annealing optimization method for a thin film transistor based on a high-k gate dielectric and an IGTO structure, characterized in that: The following steps are involved: A HfLaO film is deposited on the surface of the substrate by sputtering La target and Hf target simultaneously to form a high-k gate dielectric layer; An IGTO film is deposited on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited by sputtering using an IGTO target to form a channel layer; and the substrate on which the IGTO film is deposited is annealed.
2. The method according to claim 1, characterized in that The annealing treatment of the substrate after the IGTO film is deposited includes: The substrate after the IGTO film is deposited is placed in an annealing furnace for annealing treatment. The annealing atmosphere is air, the annealing temperature is 250 degrees Celsius, and the annealing time is 1 hour.
3. The method according to claim 1 or 2, characterized in that Before annealing the substrate after depositing the IGTO film, the method further comprises: The substrate after the IGTO film is deposited is subjected to plasma treatment.
4. The method according to claim 1 or 2, characterized in that: The method of simultaneously sputtering and depositing a HfLaO film on the surface of a substrate using a La target and a Hf target to form a high-k gate dielectric layer comprises: The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.
5. The method according to claim 1 or 2, characterized in that: Before the HfLaO film is simultaneously sputtered and deposited on the substrate surface using a La target and a Hf target to form a high-k gate dielectric layer, the method further includes: A P-type heavily doped Si material is used as a substrate and the substrate is cleaned, and the P-type heavily doped Si is selected as a gate electrode layer.
6. The method according to claim 1 or 2, characterized in that: The method of sputtering an IGTO film by using an IGTO target on the surface of the high-k gate dielectric layer on which the HfLaO film is deposited to form a channel layer comprises: The IGTO film is deposited on the surface of the high-k gate dielectric layer of the HfLaO film by sputtering using an IGTO target using a magnetron sputtering method to form the channel layer.
7. The method according to claim 1, characterized in that After the IGTO film is deposited on the surface of the gate dielectric layer on which the HfLaO film is deposited by sputtering using an IGTO target to form a channel layer, the method further includes: An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.
8. A thin film transistor based on a high-k gate dielectric and an IGTO structure, manufactured by the method according to any one of claims 1 to 7, characterized in that: The thin film transistor comprises a gate dielectric layer and a channel layer, wherein the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of a high-K gate dielectric, and the channel layer is made of an IGTO thin film.
9. The thin film transistor according to claim 8, wherein: The gate dielectric layer is made of HfLaO.
10. The thin film transistor according to claim 9, wherein: It also includes a substrate, a gate electrode layer, a source electrode and a drain electrode, wherein the substrate is arranged below the gate electrode layer, the substrate is made of P-type heavily doped Si, the gate electrode layer is arranged below the gate dielectric layer, the gate electrode layer is made of P-type heavily doped Si, and the source electrode and the drain electrode are arranged above the channel layer.
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