Semiconductor structure and static random access memory cell

Abstract

The semiconductor structure includes an epitaxial feature disposed in an active region; a front side contact disposed directly over and electrically coupled to the epitaxial feature; a metal gate stack; an internal spacer between the metal gate stack and the epitaxial feature; and a backside contact in physical contact with a bottom portion of the metal gate stack and in physical contact with a bottom portion of the front side contact. The embodiment of the invention also relates to a static random access memory unit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and static random access memory cells. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. During IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] In deep submicron integrated circuit technology, static random access memory (SRAM) devices have become popular memory cells for high-speed communications, image processing, and system-on-chip (SOC) products. As silicon technology continues to scale from one generation to the next, traditional SRAM devices and / or their manufacture may encounter limitations. For example, the dramatic scaling down of IC size has produced densely spaced source / drain components and gate structures, as well as densely spaced source / drain contacts and gate vias formed thereon. In some SRAM devices, a multilayer interconnect structure is formed above the source / drain contacts and gate vias of the transistors of the memory cells, which provides metal lines for interconnecting power lines and signal lines in and between the memory cells of the SRAM device. With the continuous reduction in device size and the dense spacing of transistors, interconnect components (e.g., contacts, vias, and metal lines) are formed to have reduced sizes, which can result in increased parasitic resistance, increased parasitic capacitance, high process risk, and / or poor connection, which can reduce the speed of the memory device. All of these issues bring challenges in performance, yield, and cost. Thus, while existing SRAM devices may be generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0004] An embodiment of the present disclosure provides a semiconductor structure, comprising: an epitaxial component disposed in an active region; a front-side contact directly disposed above the epitaxial component and electrically coupled to the epitaxial component; a metal gate stack; an internal spacer between the metal gate stack and the epitaxial component; and a back-side contact in physical contact with a bottom portion of the metal gate stack and in physical contact with a bottom portion of the front-side contact.

[0005] Another embodiment of the present disclosure provides a semiconductor structure, comprising: an active region, including a semiconductor substrate, a stack of nanostructures located above the semiconductor substrate, and an epitaxial component located above the semiconductor substrate and adjacent to the nanostructure, the active region extending longitudinally in a first direction; an isolation component arranged on the sidewall of the semiconductor substrate; a metal gate stack wrapping each of the nanostructures, the metal gate stack extending longitudinally in a second direction perpendicular to the first direction; a first contact component directly arranged above the epitaxial component and electrically coupled to the epitaxial component; and a second contact component directly arranged below the first contact component and the metal gate stack and electrically coupled to the first contact component and the metal gate stack, wherein the isolation component separates the second contact component from physically contacting the semiconductor substrate.

[0006] Yet another embodiment of the present disclosure provides a static random access memory (SRAM) cell, comprising: a first active region and a second active region, extending longitudinally along a first direction; a first metal gate stack, intersecting the first active region when forming a first pull-up transistor of the static random access memory cell; a second metal gate stack, intersecting the second active region when forming a second pull-up transistor of the static random access memory cell; a first contact component, disposed between the first metal gate stack and the second metal gate stack and extending longitudinally along a second direction perpendicular to the first direction, wherein the first contact component is disposed above a source / drain component of the first pull-up transistor and is electrically connected to the source / drain component of the first pull-up transistor; and a second contact component, in physical contact with a bottom surface of the first contact component and a bottom surface of the second metal gate stack, wherein, in a top view of the static random access memory cell, the second contact component is spaced apart from a bottom surface of the source / drain component of the first pull-up transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A circuit schematic diagram of a static random access memory (SRAM) cell according to some embodiments of the present disclosure is shown.

[0009] Figure 2 Cross-sectional views of various layers of a memory device according to some embodiments of the present disclosure are shown.

[0010] Figure 3 A partial layout of an exemplary memory device according to some embodiments of the present disclosure is shown.

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D An exemplary memory device according to some embodiments of the present disclosure is shown along Figure 3 Partial cross-sectional view along lines AA, BB, CC and DD.

[0012] Figure 5 A flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure is shown.

[0013] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 An exemplary workpiece according to some embodiments of the present disclosure is shown in FIG. Figure 5 During the manufacturing process of the method Figure 3 Partial cross-sectional view along lines CC and DD. DETAILED DESCRIPTION

[0014] The present disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0015] In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, in the following present disclosure, the formation of a component on another component, connected to another component and / or coupled to another component may include an embodiment in which the component is formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the components so that the components may not be in direct contact. In addition, in order to facilitate the present disclosure to describe the relationship between one component and another component, spatial relative terms are used, for example, "lower", "upper", "horizontal", "vertical", "above...", "above...", "below...", "below...", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downward", "upward", etc.). Spatial relative terms are intended to cover different orientations of devices including components. In addition, unless otherwise stated, when a numerical value or a numerical range is described with "about", "approximately", etc., the term is intended to cover a numerical value within + / -10% of the described numerical value. For example, the term "about 5nm" includes a size range from 4.5nm to 5.5nm.

[0016] Static random access memory (SRAM) is an electronic data storage device implemented on a semiconductor-based integrated circuit and generally has a much faster access time than other types of data storage technologies. SRAM is popular in high-speed communications, image processing, and system-on-chip (SOC) applications. A bit can be read from or written to an SRAM cell in a few nanoseconds. An SRAM cell includes a transistor and a metal interconnect structure located above the transistor. The metal interconnect structure includes metal lines for interconnecting transistor gates and source / drain regions (such as signal lines for routing bit line and word line signals to cell components) and power rails for powering cell components (such as metal lines for power supply voltage and electrical grounding). Some contacts and corresponding contact vias electrically connect the cell components to the signal lines and power rails. For example, some source / drain regions in an SRAM cell are coupled to a power supply voltage VDD (also referred to as VCC) and / or electrical ground VSS through source / source contacts, source / drain contact vias, and corresponding metal lines in the power rail. Some other contacts (also called butt contacts) each abut two conductive regions and can reduce the number of contacts required. For example, a butt contact in an SRAM cell can include a bottom surface that lands on a gate electrode, and another bottom surface that lands on an active region (such as a source / drain region or a corresponding silicide feature above). A source / drain region can refer to a source or a drain, either individually or collectively, depending on the context.

[0017] Traditionally, SRAM devices are built in a stacked manner, with transistors located at the lowest level and interconnect structures (contacts, vias, and metal lines) located on top of the transistors to provide connections to the transistors. For example, the interconnect structure may include a butt contact that electrically connects the common source / drain region of the first pull-down transistor and the first pull-up transistor to the common gate of the second pull-down transistor and the second pull-up transistor. If the butt contact is incorporated in the front-side interconnect structure, it will occupy the already limited space above the transistor. On the other hand, the butt contact can be incorporated in the back-side interconnect structure without occupying valuable layout resources above the transistor. As a result, the density of the conductive contacts on the front side of the device layer is reduced, which can reduce the short circuit and parasitic capacitance between adjacent conductive contacts on the front side of the device layer, thereby improving the performance and long-term reliability of the semiconductor die. However, if the formation of the back-side butt contact in the SRAM device involves creating a back-side opening above the source / drain component, and a step of recessing the source / drain component through the opening before depositing the back-side butt contact, the process flow will reduce the volume of the source / drain component. The reduction in volume in the source / drain features typically results in a loss of strain in the source / drain region, which typically affects the performance of the p-type transistor. Thus, while existing methods in semiconductor manufacturing have generally been adequate for their intended purposes, they have not been completely satisfactory in all respects in the context of memory devices such as SRAM devices.

[0018] Some exemplary embodiments relate to, but are not limited to, multi-gate devices. Multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). One such multi-gate device that has been introduced is a gate-all-around (GAA) transistor. The GAA transistor derives its name from a gate structure that can extend around a channel region (e.g., a stack of nanosheets), providing access to the channel on four sides. The GAA transistor is compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and its structure allows it to be massively scaled while maintaining gate control and mitigating SCE. The following disclosure will continue with one or more GAA examples to illustrate various embodiments of the present disclosure. However, it should be understood that unless otherwise stated, the application should not be limited to GAA transistors or other specific types of transistors (e.g., FinFET transistors).

[0019] The present disclosure provides various embodiments of semiconductor devices. In particular, some embodiments of the present disclosure provide semiconductor devices with back-side docking contacts. The semiconductor device includes a stack of nanostructures (e.g., nanosheets or nanowires), a gate stack located above the stack of nanostructures, a source / drain component in contact with the stack of nanostructures, and a source / drain contact falling on the front side of the source / drain component. The stack of nanostructures may be located at the end of the active region. The back-side docking contact extends from the back side of the semiconductor device to directly contact the bottom portion of the gate stack and the bottom portion of the source / drain contact. Therefore, the back-side docking contact electrically connects the gate stack and the source / drain component through the source / drain contact without directly contacting the source / drain component. In the top view of the semiconductor device, the back-side docking contact does not overlap with the source / drain component. As a result, the source / drain component remains unexposed and does not suffer etching loss during the formation of the back-side docking contact. Because the butt contact is formed on the back side of the semiconductor device, the front side via density of the semiconductor device can be reduced, providing increased space for front side conductive components (such as metal lines and vias). The semiconductor device may include an SRAM cell. However, it should be understood that unless otherwise stated, the application should not be limited to SRAM devices or other specific types of devices (e.g., other memory devices).

[0020] Reference now Figure 1 . Figure 1 is a circuit diagram of an exemplary SRAM cell 10. In the illustrated embodiment, the SRAM cell 10 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, the SRAM cell 10 may be other types of memory cells, such as a dual-port memory cell or a memory cell having more than six transistors. For clarity, the SRAM cell 10 is simplified. Figure 1 To better understand the inventive concepts of the present disclosure. Additional components may be added to the SRAM cell 10, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the SRAM cell 10.

[0021] The exemplary SRAM cell 10 is a single-port SRAM cell that includes six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistor PG-1 and the pass-gate transistor PG-2 provide access to a storage portion of the SRAM cell 10 that includes a cross-coupled pair of inverters, an inverter 12, and an inverter 14. The inverter 12 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and the inverter 14 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. In some embodiments, the pull-up transistors PU-1, PU-2 are configured as p-type transistors, such as p-type GAA transistors, and the pull-down transistors PD-1, PD-2 are configured as n-type transistors, such as n-type GAA transistors.

[0022] The gate of the pull-up transistor PU-1 is between the source (electrically coupled to the power supply voltage (VDD)) and the first common drain (CD1), and the gate of the pull-down transistor PD-1 is between the source (electrically coupled to the power supply voltage (VSS), which may be electrically grounded) and the first common drain. The gate of the pull-up transistor PU-2 is between the source (electrically coupled to the power supply voltage (VDD)) and the second common drain (CD2), and the gate of the pull-down transistor PD-2 is between the source (electrically coupled to the power supply voltage (VSS)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) storing data in the original code form, and the second common drain (CD2) is a storage node (SNB) storing data in the complement code form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are coupled to the second common drain (CD2), and the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 are coupled to the first common drain (CD1). The gate of the transfer gate transistor PG-1 is between the source (electrically coupled to the bit line BL) and the drain, which is electrically coupled to the first common drain (CD1). The gate of the transfer gate transistor PG-2 is between the source (electrically coupled to the complementary bit line BLB) and the drain, which is electrically coupled to the second common drain (CD2). The gates of the transfer gate transistors PG-1 and PG-2 are electrically coupled to the word line WL. In some embodiments, the transfer gate transistors PG-1 and PG-2 provide access to the storage nodes SN and SNB during read operations and / or write operations. For example, in response to the voltage applied to the gates of the transfer gate transistors PG-1 and PG-2 by the word line WL, the transfer gate transistors PG-1 and PG-2 couple the storage nodes SN and SNB to the bit lines BL and BLB, respectively.

[0023] Figure 2is a partial schematic cross-sectional view of a semiconductor device 50 according to various aspects of the present disclosure, the semiconductor device 50 including various layers (levels) that may be fabricated over a semiconductor substrate (or wafer) 60 to form a SRAM cell (such as Figure 1 The SRAM cell 10 is a portion of a memory device. Figure 2 As shown, the various layers include a device layer DL, a front-side multi-layer interconnect structure (FMLI) disposed above the device layer DL, and a back-side multi-layer interconnect structure (BMLI) disposed below the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain features). In some embodiments, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation feature 64, and a transistor T. In the depicted embodiment, the transistor T includes a floating channel layer 70 disposed between source / drain features 72 and a gate structure 68, wherein the gate structure 68 wraps around the floating channel layer 70. Each gate structure 68 has a metal gate stack formed by a gate electrode 74 disposed above a gate dielectric 76 and a gate spacer 78 disposed along the sidewalls of the metal gate stack.

[0024] The multi-layer interconnect structures FMLI and BMLI electrically couple various devices and / or components of the device layer DL so that the various devices and / or components can operate according to the design requirements of the memory device. Each of the multi-layer interconnect structures FMLI and BMLI may include one or more interconnect layers.

[0025] In the depicted embodiment, the FMLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero layer (M0 level), a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The present disclosure contemplates FMLIs with more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the FMLI is 2 to 10. Each level of the FMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features at the same level of the FMLI (such as the M0 level) are formed simultaneously. In some embodiments, conductive features at the same level of the FMLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially flat to each other. The CO level includes source / drain contacts (MD) disposed in the dielectric layer 66; the V0 level includes gate vias VG and source / drain contact vias VD disposed in the dielectric layer 66. The M0 level includes an M0 metal line disposed in the dielectric layer 66, wherein the gate vias VG connect the gate structure to the M0 metal line, the source / drain vias V0 connect the source / drain to the M0 metal line, and the butting contacts connect the gate structure and the source / drain together and to the M0 metal line. The V1 level includes a V1 via disposed in the dielectric layer 66, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 level includes an M1 metal line disposed in the dielectric layer 66. The V2 level includes a V2 via disposed in the dielectric layer 66, wherein the V2 via connects the M1 line to the M2 line. The M2 level includes an M2 metal line disposed in the dielectric layer 66. The V3 level includes V3 vias disposed in dielectric layer 66 , wherein the V3 vias connect the M2 lines to the M3 lines.

[0026] In the depicted embodiment, the BMLI includes a backside via zero layer (BV0 level), a backside metal zero layer (BM0 level), a backside via one layer (BV1 level), and a backside metal one layer (BM1 level). The present disclosure contemplates a BMLI having more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the BMLI is 2 to 10. Each level of the BMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features at the same level of the BMLI (such as the BM0 level) are formed simultaneously. In some embodiments, the conductive features at the same level of the BMLI have top surfaces that are substantially flat with each other and / or bottom surfaces that are substantially flat with each other. The BV0 level includes a via BV0 formed below the device layer DL. For example, the via BV0 may include one or more backside source / drain vias formed directly below the source / drain features 72 of the device layer DL and coupled to those source / drain features 72 through the silicide layer. The via BV0 may include one or more backside gate vias formed directly below the gate structure 68 of the device layer DL and in direct contact with the gate structure 68 of the device layer DL. In the present disclosure, the via BV0 may include one or more backside docking contacts directly contacting the bottom portion of the gate structure 68 and the bottom portion of the source / drain contact (MD) for electrically connecting the gate structure 68 and the corresponding source / drain features 72. The BM0 level includes a BM0 metal line formed below the BV0 level and disposed in the backside dielectric structure 66'. The backside gate via connects the gate structure 68 to the BM0 metal line, and the backside source / drain via connects the source / drain feature 72 to the BM0 metal line. The BV1 level includes a BV1 via disposed in the backside dielectric structure 66', wherein the BV1 via connects the BM0 metal line to the BM1 metal line. The BM1 level includes a BM1 metal line formed below the BV1 level.

[0027] For the sake of clarity, the Figure 2 To better understand the inventive concept of the present disclosure. Additional components may be added in various layers of the memory, and some of the components described may be replaced, modified or eliminated in other embodiments of the memory. Figure 2 This is merely an example and may not reflect an actual cross-sectional view of the SRAM cell 10 discussed in further detail below.

[0028] Now common reference Figure 3 and FIG. 4A to FIG. 4D . Figure 3 shows an exemplary layout of a semiconductor device 200 according to some embodiments of the present disclosure, and Figure 4A , Figure 4B , Figure 4C and Figure 4D They are shown along Figure 3 2 is a cross-sectional view of a semiconductor device 200 taken along lines AA, BB, CC, and DD in FIG. In some embodiments, the semiconductor device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof, and includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof.

[0029] The illustrated portion of the layout of a semiconductor device 200 includes two SRAM cells 100a and 100b (collectively referred to as SRAM cells 100), which may be part of a larger SRAM array, in accordance with the present disclosure. Each SRAM cell 100 may be implemented as Figure 1 1. The cell boundary of the SRAM cell 100 is a rectangular frame that is longer in the Y direction than in the X direction, for example, about 2 times to about 6 times longer. The first dimension of the cell boundary along the X direction is represented as the cell width W, and the second dimension of the cell boundary along the Y direction is represented as the cell height H. Where the SRAM cell 100 is repeated in the memory array, the cell width W can be represented and referred to as the memory cell pitch along the X direction in the memory array, and the cell height H can be represented and referred to as the memory cell pitch along the Y direction in the memory array. In the illustrated embodiment, the cell width W is twice the polysilicon pitch. The polysilicon pitch refers to the minimum center-to-center distance between two adjacent gate structures along the X direction. Two adjacent SRAM cells 100a and 100b are symmetrical with respect to a common boundary line along the Y direction.

[0030] The semiconductor device 200 includes a plurality of active regions 212 (including active regions 212a, 212b, 212c, 212d, and 212e) (each active region is longitudinally oriented along the X direction) and a plurality of gate stacks (or gate structures) 240 (including gate stacks 240a, 240b, 240c, 240d, 240e, 240f, 240g, 240h) longitudinally oriented along the Y direction. The active region of a transistor refers to a region where a source region, a drain region, and a channel region below the gate structure of the transistor are formed. In this context, the active region is also referred to as an "oxide-defined (OD) region". In the illustrated embodiment, the active regions 212b, 212c, and 212d are p-type active regions and are disposed above the N-well region 205; the active regions 212a and 212e are n-type active regions and are disposed above two P-well regions 207a and 207b, respectively. The P-well regions 207 a and 207 b sandwich the N-well region 205 along the Y direction. In some embodiments, the active region 212 is a fin structure and is also referred to as the fin structure 212 .

[0031] Gate stack 240a is disposed over active regions 212a, 212b, and 212d; gate stack 240b is disposed over active region 212a; gate stack 240c is disposed over active region 212e; gate stack 240d is disposed over active regions 212b, 212d, and 212e; gate stack 240e is disposed over active region 212a; gate stack 240f is disposed over active regions 212a, 212c, and 212d; gate stack 240g is disposed over active regions 212c, 212d, and 212e; and gate stack 240h is disposed over active region 212e. At the intersection of active region 212 and gate stack 240, transistors (e.g., pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and pass gate transistors PG-1 and PG-2) are formed. In the context of a GAA transistor formed at the intersection of an active region 212 and a gate stack 240, the active region 212 includes an elongated nanostructure 208 (also referred to as a channel member or channel layer) vertically stacked in a channel region defined in the active region 212 and over a semiconductor substrate 204 of the active region 212. In some embodiments, a portion of the active region 212 not covered by the gate stack 240 serves as a source / drain region. A source / drain feature 214 is formed in the source / drain region defined in the active region 212 and over the semiconductor substrate 204. The source / drain feature 214 abuts two opposite ends of the channel layer 208.

[0032] Different active regions 212 in different transistors of the SRAM cell 100 may have different widths (e.g., dimensions measured in the Y direction) to optimize device performance. In more detail, the active region 212a of the pull-down transistor PD-1 and the pass-gate transistor PG-1 has a width W1, the active region 212b or the active region 212c of the pull-up transistor PU-1 has a width W2, the active region 212d of the pull-up transistor PU-2 has a width W2, and the active region 212e of the pass-gate transistor PG-2 and the pull-down transistor PD-2 has a width W1. The widths W1 and W2 may also be measured in portions of the active region corresponding to the channel region. In other words, these portions of the active region (from which the widths W1 and W2 are measured) are the channel regions of the transistors (e.g., the vertically stacked nanostructures 208 of the GAA device). In order to optimize SRAM performance, in some embodiments, the width W1 is configured to be greater than the width W2 (W1>W2) to balance the speed between the n-type transistor and the p-type transistor. In some embodiments, the ratio of W1 / W2 may be in a range from about 1.1 to about 3. In some other embodiments, the widths W1 and W2 may be the same (W1=W2).

[0033] Each source / drain feature 214 can be suitable for forming a p-type device, or alternatively, an n-type device. The p-type source / drain features of a p-type transistor (e.g., pull-up transistors PU-1 and PU-2) can include one or more epitaxial layers of silicon germanium doped with a p-type dopant (such as boron, germanium, indium, and / or other p-type dopants). The n-type source / drain features of an n-type transistor (e.g., pass-gate transistors PG-1, PG-2, pull-down transistors PD-1, PD-2) can include one or more epitaxial layers of silicon or silicon carbon doped with an n-type dopant (such as arsenic, phosphorus, and / or other n-type dopants). In such a configuration, the source / drain features of the p-type transistors (e.g., pass-gate transistors PG-1, PG-2, pull-down transistors PD-1, PD-2) can include one or more epitaxial layers of silicon or silicon carbon doped with an n-type dopant (such as arsenic, phosphorus, and / or other n-type dopants). Figure 4A and Figure 4DIn the illustrated embodiment shown, the source / drain component 214 is a multilayer structure including epitaxial layers 214a, 214b and 214c. The dopant concentrations of the epitaxial layers 214a, 214b and 214c are different, and the dopant concentration gradient increases from the epitaxial layer 214a to 214c. The epitaxial layer 214a is in direct contact with the end portion of the channel layer 208. The epitaxial layer 214b separates the epitaxial layer 214c from the epitaxial layer 214a. The source / drain component 214 may also include an undoped epitaxial layer 214d below the epitaxial layer 214b / 214c and a dielectric film 214e between the undoped epitaxial layer 214d and the epitaxial layer 214b / 214c. The undoped epitaxial layer 214d and the dielectric film 214e exhibit high resistivity and suppress leakage current from the source / drain component 214 to the semiconductor substrate 204. In some embodiments, the source / drain feature 214 further includes a silicide feature 214f ​​located on top of the epitaxial layer 214b / 214c. The silicide feature 214f ​​reduces the resistivity between the source / drain feature 214 and the source / drain contact 222 formed thereon. The silicide feature 214f ​​may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0034] The gate stack 240 may include a gate dielectric layer 242 and a gate electrode layer 244 (eg, FIG. 4A to FIG. 4C 2. The gate dielectric layer 242 may further include an interface layer formed on a surface of the channel layer 208 interfacing with the gate stack 240 and a high-k dielectric layer formed above the interface layer. The interface layer may include silicon dioxide, silicon oxynitride, or other suitable materials. The high-k dielectric layer may include a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiNO, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO, or other suitable materials. x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials or combinations thereof. High-k dielectric materials generally refer to dielectric materials with high dielectric constants, for example, dielectric constants greater than silicon oxide (k≈3.9). In some embodiments, the gate electrode layer 244 may further include a work function layer 246 that is an n-type or p-type work function layer and a metal filling layer 248 located above the work function layer 246. For example, the n-type work function layer may include a metal having a sufficiently low effective work function, and the p-type work function layer may include a metal having a sufficiently large effective work function. For example, the n-type work function layer may include Ta, titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), TiAlN, or a combination thereof. For example, the p-type work function layer may include TiN, TaN, WN, or a combination thereof. In some embodiments, the work function layer 246 may include a multilayer structure, such as a first work function layer 246a and a second work function layer 246b. For example, the first work function layer 246a may include a metal such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or a combination thereof, and the second work function layer 246b may include a metal such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. In some embodiments, the metal fill layer 248 includes aluminum, tungsten, cobalt, copper, and / or other suitable materials. Since the gate stack 240 includes a high-k dielectric layer and a metal layer, the gate stack 240 is also referred to as a high-k metal gate.

[0035] The semiconductor device 200 also includes a plurality of gate cut dielectric features 216 (including gate cut dielectric features 216a, 216b, 216c, 216d, 216e, and 216f). The gate cut dielectric features 216 divide the originally continuous gate structure into two isolated segments. For example, the gate cut dielectric feature 216c separates the gate stack 240b from the gate stack 240d, and separates the gate stack 240e from the gate stack 240g; the gate cut dielectric feature 216d separates the gate stack 240a from the gate stack 240c; and the gate cut dielectric feature 216e separates the gate stack 240f from the gate stack 240h. The gate cut dielectric features 216 are formed by filling the corresponding cut metal gate (CMG) trenches in the locations of the gate cut dielectric features. The CMG process refers to a manufacturing process in which, after a gate stack (e.g., a high-k metal gate) replaces a dummy gate structure (e.g., a polysilicon gate), the gate stack is cut (e.g., by an etching process) to divide the previously continuous gate stack into two or more separate gate segments. Each gate segment serves as a metal gate for a separate transistor. Isolation material is then filled into the trenches between adjacent portions of the metal gate. These trenches are referred to as cut metal gate trenches or CMG trenches. The dielectric material used to fill the CMG trenches for isolation is referred to as a CMG component. Therefore, the gate cut dielectric component 216 is also referred to as a CMG component. In order to ensure that the gate stack is completely cut, the CMG component is generally further extended into adjacent regions, such as a dielectric layer that fills the space between the metal gates. The CMG component generally has an elongated shape in the top view. In the illustrated embodiment, each gate cut dielectric component 216 extends longitudinally along the X direction. The gate cut dielectric component 216 can extend across the SRAM cell boundary and be shared by adjacent SRAM cells 100. In the illustrated embodiment, each of the gate cut dielectric features 216 c , 216 d , and 216 e is disposed over an interface between an N-well region and a P-well region.

[0036] The semiconductor device 200 further includes an isolation feature 218 (eg, FIG. 4A to FIG. 4D ), to isolate two adjacent active regions 212. The isolation feature 218 may also be referred to as a shallow trench isolation (STI) feature, and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0037] The semiconductor device 200 further includes an internal spacer 254 (eg, a spacer 254 disposed between the source / drain feature 214 and the adjacent gate stack 240). Figure 4A). The inner spacer 254 isolates the source / drain features 214 from the adjacent gate stack 240. In some embodiments, the inner spacer 254 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or carbon oxynitride silicon). In some embodiments, the inner spacer 254 comprises a low-k dielectric material, such as those described herein.

[0038] The semiconductor device 200 further includes a gate spacer 252 (eg, a gate spacer 252 disposed on the sidewall of the gate stack 240). Figure 4A , Figure 4B and Figure 4D ). The gate spacer 252 may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon oxycarbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon oxycarbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicon, zirconium silicide, etc.), other suitable materials, or combinations thereof. The gate spacer 252 may be a single-layer structure or a multi-layer structure (such as layers 252a and 252b as shown). As Figure 4D As shown, the gate spacers 252 may also extend to the source / drain regions of the active region 212 .

[0039] The semiconductor device 200 further includes a dielectric structure 262 (eg, Figure 4A , Figure 4B and Figure 4D ). The dielectric structure 262 may include a contact etch stop layer (CESL) 256 and an interlayer dielectric (ILD) layer 258 formed over the CESL 256. The ILD layer 258 includes a dielectric material such as tetraethyl orthosilicate (TEOS), silicon oxide, a low-k dielectric material, doped silicon oxide (such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), FSG, boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. The ILD layer 258 may include a multilayer structure having a plurality of dielectric materials. The CESL 256 may include silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements, other suitable materials, or combinations thereof. Figure 4A As shown, dielectric structure 262 also fills the trench between two adjacent active regions (such as active regions 212b and 212c) as an isolation feature separating the two adjacent active regions. The portion of dielectric structure 262 that fills the trench between two adjacent active regions is also referred to as a fin cut feature.

[0040] The semiconductor device 200 further includes a front side dielectric structure 266 (eg, a front side dielectric structure 266 disposed over the dielectric structure 262, the gate stack 240, the gate spacer 252, and the gate cut dielectric feature 216. FIG. 4A to FIG. 4D 2 ). In some embodiments, the front side dielectric structure 266 includes a plurality of dielectric layers 264 and an etch stop layer (ESL) 268. The ESL 268 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiN, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials. The dielectric layer 264 may include SiO2, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), low-k dielectric material, other suitable dielectric materials, or combinations thereof.

[0041] The semiconductor device 200 also includes a source / drain contact 222 disposed above the source / drain component 214 and electrically coupled to the source / drain component 214. In an embodiment, the source / drain contact 222 may include a conductive barrier layer and a metal fill layer located above the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru) or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN) or a combination thereof, and may be formed by CVD, PVD, ALD and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru) or other metals. Some source / drain contacts 222 fall on multiple source / drain components and electrically connect multiple source / drain components, and are referred to as long contacts in some cases. For example, as Figure 4D As shown, the source / drain contact 222 on the left side electrically connects the n-type source / drain components 214 of transistors PD-1 and PG-1 and the p-type source / drain component 214 of transistor PU-1; and the source / drain contact 222 on the right side electrically connects the n-type source / drain components 214 of transistors PD-2 and PG-2 and the p-type source-drain component 214 of transistor PU-2. Figure 4B and Figure 4D As shown, source / drain contacts 222 may extend through dielectric structure 262 and portions of dielectric structure 266 (eg, dielectric layer 264 and ESL 268 ).

[0042] The semiconductor device 200 further includes a gate through hole 253 (eg Figure 3), the gate via 253 connects the gate stack 240 and the word line (WL) of the metal line 250 (as shown in Figure 4C and Figure 4D 2. The gate via 253 may be embedded in the dielectric structure 266 as shown. The gate via 253 may include similar materials as the source / drain contact 222 and may be formed similarly to the source / drain contact 222. The semiconductor device 200 also includes a source / drain contact via 257 (as shown). Figure 3 266 ). Source / drain contact vias 257 may be embedded in dielectric structure 266 and connect source / source contact 222 and metal line 250 (e.g., bit line (BL), bit line bar (BLB), VDD, and VSS). Source / drain contact vias 257 may include similar materials as gate vias 253 and may be formed similarly to gate vias 253.

[0043] The semiconductor device 200 further includes a backside dielectric structure 272 (eg, FIG. 4A to FIG. 4D As shown). In some embodiments, the backside dielectric structure 272 includes a plurality of etch stop layers (ESL) 274 and a dielectric layer 275. The ESL 274 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiN, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi or other suitable materials. The dielectric layer 275 may include SiO2, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. FIG. 4A to FIG. 4D In FIG. 1 , only a pair of ESL 274 and dielectric layer 275 in the backside dielectric structure 272 are shown, which correspond to the BV0 level ( Figure 2 The backside dielectric structure 272 may include multiple pairs of dielectric layers 275 and ESL 274 for other backside layers, such as BM0, BV1, BM1 levels, etc.

[0044] In the BV0 level, the semiconductor device 200 includes two types of backside contacts, namely, backside source / drain contacts 277 (including backside source / drain contacts 277a, 277b, and 277c) directly disposed below the corresponding active region 212 and backside butt contacts 279 (including backside butt contacts 279a, 279b, 279c, and 279d) offset from the corresponding active region 112. Each backside contact may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals. In one embodiment, the backside contact includes tungsten (W).

[0045] like Figure 3 As shown, the illustrated portion of the semiconductor device 200 includes two backside source / drain contacts 277a and 277b disposed on the backside of the active region 212a, and one backside source / drain contact 277c disposed on the backside of the active region 212e. Each of the backside source / drain contacts 277 is electrically coupled to a corresponding source / drain contact 222 and a frontside source / drain contact via 257 through a corresponding source / drain feature 214 between the source / drain contact 222 and the frontside source / drain contact via 257. Similar to the function of the corresponding frontside source / drain contact via 257, the backside source / drain contact 277 electrically couples the source regions of the pull-down transistors PD-1 and PD-2 to the electrical ground VSS. Below the BV0 level, the BM0 level includes a plurality of backside VSS lines (not shown). The back side source / drain contact 277 can have the same size (e.g., W1) as the active regions 212a and 212e along the Y direction. This is due to an exemplary back side manufacturing process in which a back side via is formed by etching a fin-shaped semiconductor substrate in the active region from the back side to form a back side trench and filling the back side trench with a conductive material. Therefore, the back side source / drain contact 277 inherits the width of the corresponding active region. In addition, the back side source / drain contact 277 can have the same size as the source / source contact 222 along the X direction. In the illustrated embodiment, the back side source / drain contact 277 has an elongated shape having a longitudinal direction along the Y direction.

[0046] like Figure 3 and FIG. 4B to FIG. 4DAs shown, the illustrated portion of the semiconductor device 200 includes four backside docking contacts 279. Each backside docking contact 279 at least partially lands on the bottom surface of the corresponding gate stack 240 and at least partially lands on the bottom surface of the corresponding source / drain contact 222. Therefore, the backside docking contact 279 provides an electrical connection between the corresponding gate stack 240 and the common source / source region of the PD-1 / PG-1 / PU-1 transistor or the PD-2 / PG-2 / PU-2 transistor through the corresponding source / drain contact 222 and the source / drain feature 214. In particular, from a top view, there is no overlap area between the backside docking contact 279 and the corresponding active area 212, which ensures that the corresponding source / drain feature 214 will not be exposed and therefore will not suffer etching loss and volume loss during the formation of the backside docking contact 279.

[0047] The region 280 containing the backside butt contact 279c is enlarged to show further details. The backside butt contact 279c has an elongated shape having a longitudinal direction along the X direction. The edge between the backside butt contact 279c and the active region 212c is spaced apart by a distance S along the Y direction. The backside butt contact 279c at least partially overlaps the width of the gate stack 240g along the X direction and at least partially overlaps the width of the source / drain contact 222 along the X direction. Figure 4B and Figure 4C As shown, the gate dielectric layer 242 of the gate stack 240g is partially removed, and the gate electrode layer 244 is exposed and in physical contact with the back-side docking contact 279c. In the illustrated embodiment, the first work function layer 246a is exposed and in physical contact with the back-side docking contact 279c. In an optional embodiment, the removal of the gate dielectric layer 242 may also partially remove the first work function layer 246a, and the second work function layer 246 is exposed and in physical contact with the back-side docking contact 279c. In another optional embodiment, the removal of the gate dielectric layer 242 may also partially remove the work function layer 246, and the metal fill layer 248 is exposed and in physical contact with the back-side docking contact 279c. Figure 4C As shown, a portion of the backside docking contact 279c also rests on the bottom surface of the gate cut dielectric feature 216c. Figure 4B and Figure 4DAs shown, the backside docking contact 279c lands on the bottom surface of the source / drain contact 222. Therefore, an electrical path is established between the gate stack 240g and the common source / drain region of the PD-1 / PG-1 / PU-1 transistors of the SRAM cell 100b, which passes through the bottom surface of the gate stack 240g, the backside docking contact 279c, the bottom surface of the source / drain contact 222, the interface between the source / drain contact 222 and the top surface of the source / drain feature 214 (if present, it can be through the silicide feature 214f), and the source / drain feature 214. It should be understood that similar electrical paths are also established for the backside docking contacts 279a, 279b and 279d, respectively, and for simplicity, they are not repeated.

[0048] Still refer to Figure 3In the enlarged region 280 shown, the position and size of the back-side docking contact 279c are defined by its four edges E1, E2, E3 and E4. Each of the four edges can be adjusted independently to determine the position and size of the back-side docking contact 279c based on the device performance requirements as long as the following conditions are still met. First, the distance S between the edge E1 and the active area 212c is at least zero (S≥0). That is, the edge E1 is at most aligned with the opposite edge of the active area 212c (when S=0) without causing an overlap area. The absence of an overlap area protects the bottom surface of the source / drain component 214 from being exposed during the formation of the back-side docking contact 279c, and thus does not lose volume due to etching losses. When the edge E1 is aligned with the opposite edge of the active area 212c (when S=0), the sidewalls of the back-side docking contact 279c and the source / drain component 214 can directly interface with each other. When edge E1 is spaced apart from the opposite edge of active region 212c (when S>0), a dielectric layer is interposed between backside docking contact 279c and sidewalls of source / drain features 214, such as STI features 218, gate spacers 252, and / or dielectric structures 262 (including CESL 256 and / or ILD 258). Second, there is an overlap between gate stack 240g and backside docking contact 279c, which ensures electrical contact therebetween. Edge E2 may be directly below gate stack 240g for partial overlap, or edge E2 may extend beyond gate stack 240 for full overlap with the width of gate stack 240g. Third, there is an overlap between source / drain contacts 222 and backside docking contact 279c, which ensures electrical contact therebetween. The edge E3 may be directly below the source / drain contact 222 for partial overlap, or beyond the source / drain contact 222 for full overlap with the width of the source / drain contact 222. Fourth, the edge E4 is positioned not beyond the edge of the gate cut dielectric feature 216c that interfaces with the gate stack 240e to avoid overlap and thereby avoid electrical shorting between the backside docking contact 279c and the other gate stack 240d.

[0049] Figure 3An alternative embodiment of an enlarged region (denoted as 280') is also depicted in the figure to illustrate one of the combinations of positions of the edges E1, E2, E3, and E4. In the enlarged region 280', the edge E1 is aligned with the opposite edge of the active region 212c (when S=0) without causing an overlap region; the edge E2 exceeds the edge of the gate stack 240g for completely overlapping with the width of the gate stack 240g, so that in the cross-sectional view (BB), the entire bottom surface of the gate stack 240g is in physical contact with the back-side docking contact 279c; the edge E3 is directly below the source / drain contact 222 for partial overlap; and the edge E4 is aligned with the opposite edge of the gate cut dielectric feature 216c without causing an overlap region. It should be understood that the enlarged region 280' is one of the alternative embodiments that meets the four conditions of the above-mentioned edges E1, E2, E3, and E4. For simplicity, not all alternative embodiments are listed.

[0050] Reference now Figure 5 . Figure 5 FIG. 1 is a diagram showing a method of forming a Figure 3 and FIG. 4A to FIG. 4D 300 is a flowchart of a method 300 for a semiconductor device 200 shown in FIG. 300 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 300. Additional steps may be provided before, during, and after method 300, and some of the steps described may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail. Figures 6 to 14 Describe method 300, each diagram includes Figure 5 The embodiment of the method 300 is performed at different manufacturing stages along the Figure 3 The semiconductor device 200 during the manufacturing stage is also referred to as a workpiece 200 .

[0051] refer to Figure 5 and Figure 6 , the method 300 includes block 302, where the workpiece 200 is mounted on the carrier wafer 282 with its top surface and turned upside down. The negative sign in the axis "-Z" indicates a direction.

[0052] Each active region 212 includes a semiconductor substrate 204 and a stack of nanostructures 208 vertically stacked and suspended above the semiconductor substrate 204. In an embodiment, the semiconductor substrate 204 includes silicon, silicon germanium, germanium or other suitable semiconductors, and may be doped with n-type or p-type dopants. The active region 212 may be patterned by any suitable method. For example, the active region 212 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers or mandrels may be used as masking elements for patterning the active region 212. For example, the masking element may be used to etch a groove in a semiconductor layer above or in the semiconductor substrate, thereby leaving the active region 212 on the semiconductor substrate. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may use an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method of forming the active region 212 may be suitable.

[0053] The nanostructure 208 in the stack connects the two source / drain components 214 and serves as a channel layer of the GAA transistor. Therefore, the nanostructure 208 may also be referred to as a channel layer 208. The nanostructure 208 may include a semiconductor material suitable for a transistor channel, such as silicon, silicon germanium, or other semiconductor materials. In various embodiments, the nanostructure 208 may be in the shape of a rod, a strip, a sheet, or other shapes. In an embodiment, the nanostructure 208 is initially part of a stack of semiconductor layers, which includes nanostructures 208 and other sacrificial semiconductor layers alternately stacked layer by layer. The sacrificial semiconductor layer and the nanostructure 208 include different material compositions (such as different semiconductor materials, different composition atomic percentages, and / or different composition weight percentages) to achieve etching selectivity. During the gate replacement process of forming the gate stack 240, the sacrificial semiconductor layer is selectively removed, leaving the nanostructure 208 suspended above the semiconductor substrate 204. It should be noted that in the illustrated embodiment, three (3) nanostructures 208 are vertically stacked, which is for illustrative purposes only and is not intended to limit the specific references in the claims. It is understood that any number of nanostructures may be formed depending on device performance requirements. In some embodiments, the number of vertically stacked nanostructures 208 is between 2 and 10, inclusive.

[0054] Source / drain components 214 are formed in and / or above the source / drain region of the active region 212, each source / drain component 214 being disposed adjacent to the gate stack 240. Depending on the context, the source / drain component 214 may refer to a source or a drain, either individually or collectively. The source / drain component 214 may be formed by any suitable technique, such as an etching process and one or more subsequent epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of the active region 212 to form a recess (not shown) in the source / drain region. A cleaning process may be performed to clean the recess with a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow the source / drain component 214 in the recess.

[0055] The internal spacer 254 can be formed by a deposition and etching process. For example, after etching the source / drain trenches and before epitaxially growing the source region / drain features 214 from the S / D trenches, an etching process can be used to recess the sacrificial layer between adjacent channel layers 208 to vertically form a gap between adjacent channel layers 208. Then, one or more dielectric materials are deposited (e.g., using CVD or ALD) to fill the gap. Another etching process is performed to remove the dielectric material outside the gap, thereby forming the internal spacer 254.

[0056] The gate stack 240 is formed between the two source / drain components 214, disposed above each channel layer 208 and wrapping each channel layer 208. The gate stack 240 includes a gate dielectric layer 242 and a gate electrode layer 244 formed above the gate dielectric layer 242. The interfacial layer in the gate dielectric layer 242 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer in the gate dielectric layer 242 can be formed by ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, and / or other suitable methods. The gate electrode layer 244 can be formed by CVD, PVD, plating, and / or other suitable processes. In some embodiments, the gate stack 240 is formed after manufacturing other components of the workpiece 200 (e.g., the source / drain component 214). This process is generally referred to as a gate replacement process, which includes forming a dummy gate structure (not shown) as a placeholder for the gate stack 240, forming a source / drain feature 214, forming a dielectric structure 262 over the dummy gate structure and the source / drain feature 214, planarizing the semiconductor device 200 to expose a top surface of the dummy gate structure, removing the dummy gate structure in the dielectric structure 262 to form a trench exposing a channel region of the active region 212, removing the sacrificial layer for channel release, and forming a gate stack 240 in the trench and around the channel layer 208 to complete the gate replacement process.

[0057] The composition of the gate spacer 252 is different from the composition of the surrounding dielectric components (e.g., the dielectric structure 262), so that there can be an etch selectivity between the gate spacer 252 and the surrounding dielectric components. In an embodiment, the gate spacer 252 includes SiN. The gate spacer 252 can be formed by first depositing a blanket layer of spacer material over the workpiece 200, and then performing an anisotropic etching process to remove a portion of the spacer material to form the gate spacer 252.

[0058] CESL 256 may be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof. ILD layer 258 may be formed by a deposition process such as, for example, CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof. ILD layer 258 may be deposited after deposition of CESL 256.

[0059] The gate cut dielectric feature 216 may be formed by a patterning process to form a trench and a deposition process to fill the trench with one or more dielectric materials. The patterning process includes a photolithography process and an etching process, and a hard mask may be used to define an area for the gate cut dielectric feature 216. The etching process may include wet etching, dry etching, or a combination thereof to etch the conductive material through the long metal gate structure. The etching process may use one or more etchants. CMP may be performed after the deposition process to remove excess material of the gate cut dielectric feature 216 deposited on the dielectric structure 262 and the gate stack 240, and to planarize the top surface of the workpiece 200.

[0060] The ESL 274 and the dielectric layer 275 are deposited on the back side of the workpiece 200. The ESL 274 may be formed by CVD, PVD, ALD or other suitable methods. The dielectric layer 275 may be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD) or other suitable methods. The thickness of the ESL 274 may be in the range of from about 5 nm to about 15 nm. The thickness of the dielectric layer 275 may be in the range of from about 30 nm to about 50 nm. Before depositing the ESL 274 and the dielectric layer 275, the method 300 may include thinning the workpiece 200 from the back side of the workpiece 200. In some embodiments, after the thinning is completed, the semiconductor substrate 204, the gate cut dielectric component 216, the STI component 218 and the dielectric structure 262 are exposed from the back side of the workpiece 200. The thinning process may include a mechanical grinding process and / or a chemical thinning process. During the mechanical grinding process, a large amount of substrate material may be first removed from the semiconductor substrate. Thereafter, a chemical thinning process may apply an etching chemistry to the backside of the semiconductor substrate to further thin the semiconductor substrate until the semiconductor base 204 , the gate cut dielectric features 216 , the STI features 218 , and the dielectric structures 262 are exposed.

[0061] refer to Figure 5 and Figure 7 The method 300 includes block 304, wherein a trench 284 is formed from the back side of the semiconductor device 200. The trench 284 is located such as Figure 3 The same position of the back side docking contact 279 is shown.

[0062] Forming the trench 284 may include forming a hard mask layer (not shown) on the dielectric layer 275, and performing a photolithographic patterning and etching process to pattern the hard mask layer. The hard mask layer may include SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN or other suitable materials. Then, one or more etching processes are performed using the hard mask layer as a mask to form the trench 284. The one or more etching processes may include multiple steps and involve various etching fluids. The one or more etching processes may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. For example, the dry etching process may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Due to etching losses, the thickness of the dielectric layer 275 may be reduced to about 23 nm to about 40 nm.

[0063] The trench 284 extends through the ESL 274 and partially extends into the gate cut dielectric feature 216 and the dielectric structure 262. After exposing the gate dielectric layer 242 in the trench 284, the etching process also removes the exposed portion of the gate dielectric layer 242 to expose the gate electrode layer 244 in the trench 284. The bottom portion of the source / drain contact 222 extends between two adjacent n-type and p-type source / drain features 214. The trench 284 also exposes portions of the bottom surface and sidewall surfaces of the bottom portion of the source / drain contact 222. The trench 284 also exposes the dielectric structure 262 and the STI feature 218 between two adjacent n-type and p-type source / drain features 214.

[0064] refer to Figure 5 and Figures 8 to 9 , method 300 includes block 306, in which a barrier layer 286 is formed on the sidewalls of trench 284. This step is optional. Barrier layer 286 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, barrier layer 286 includes silicon nitride. For example, Figure 8As shown, the barrier layer 286 can be formed by blanket depositing a dielectric material layer over the back side of the workpiece 200 in a conformal manner using a process such as a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable process. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from the top of the horizontal surface and the sidewall surface of the trench 284. In some embodiments, the etch-back process can include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The dielectric material layer can remain on the sidewalls of the trench 284 as a barrier layer 286. Fig. 9 284. The resulting structure after the etch-back process is shown in . The barrier layer 286 provides electrical isolation between the backside metal fill 288 (to be described below) and other components surrounding the trench 284. In some embodiments, the deposited barrier layer 286 is first treated so that its composition is changed. In this case, the treated portion of the barrier layer 286 is retained during the etch-back process, and the untreated portion is removed by the etch-back process. In a further embodiment, the barrier layer 286 includes silicon oxide, and the treatment process includes an inclined ion implantation using appropriate ions (such as nitrogen ions) so that nitrogen is introduced into the bottom portion of the barrier layer 286. Thereafter, the treated portion of the barrier layer 286 is selectively removed by an etch-back process using an appropriate etchant (such as phosphorous acid).

[0065] refer to Figure 5 and Figure 10 to Figure 11 , the method 300 includes a block 308, in which a backside metal fill 288 is formed in the trench 284. The backside metal fill 288 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the backside metal fill 288 includes W. A planarization operation, such as a CMP process, is performed to remove excess conductive material of the backside metal fill 288. The dielectric layer 275 may be used as a stop layer for the planarization operation so that the planarization operation also removes the hard mask layer. The remaining portion of the backside metal fill 288 in the trench 284 becomes the backside docking contact 279. Fig.11 The resulting structure after the planarization operation is shown in .

[0066] As discussed above, barrier layer 286 is optional. By skipping the formation of barrier layer 286, the contact area between backside butting contact 279 and gate stack 240 and source / drain contacts 222 is increased, which reduces contact resistance. Fig.12 An alternative resulting structure is shown in .

[0067] exist Fig.11 and Fig.12 In the embodiment, the top surface Tc of the backside butt contact 279 is located below the top surface of the semiconductor substrate 204 and below the bottommost channel layer 208. Fig.13 and Fig.14 As shown, the depth of the trench 284 may extend beyond the top surface of the semiconductor substrate 204 at frame 304, so that the top surface Tc of the backside docking contact 279 is located above the top surface of the semiconductor substrate 204. Fig.13 As shown, trench 284 exposes more sidewall surface of source / drain contact 222. As a result, as shown in FIG. Fig.14 As shown, the contact area between the back side butt contact 279 and the source / drain contact 222 is further increased. The larger contact area further reduces the contact resistance. Depending on the depth of the trench 284, the top surface Tc of the back side butt contact 279 can be located above the bottom surface of the bottommost channel layer 208.

[0068] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and their formation. For example, the present disclosure reduces the density of front-side conductive components and provides more freedom for FMLI design by having a back-side docking contact. Therefore, the front-side metal line can have an increased width and reduced resistance, which can reduce the voltage drop and wasted energy during the operation of the semiconductor device. The back-side docking contact is spaced apart from the adjacent source / drain components, thereby avoiding the loss of source / drain components during the formation of the back-side docking contact, and the performance of the semiconductor device can be improved. In addition, embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes. For example, the back-side docking contact can be formed together with other back-side vias of the semiconductor device (e.g., the back-side vias under the source / drain components of the power line).

[0069] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: an epitaxial component disposed in an active region; a front side contact directly disposed above the epitaxial component and electrically coupled to the epitaxial component; a metal gate stack; an internal spacer between the metal gate stack and the epitaxial component; and a back side contact in physical contact with a bottom portion of the metal gate stack and in physical contact with a bottom portion of the front side contact. In some embodiments, in a top view of the semiconductor structure, the back side contact and the active region have no overlap region. In some embodiments, the semiconductor structure further includes a dielectric structure separating the back side contact from physically contacting the epitaxial component. In some embodiments, a sidewall of the back side contact directly interfaces with a sidewall of the epitaxial component. In some embodiments, the semiconductor structure further includes a gate cut dielectric component adjacent to the metal gate stack. In a top view of the semiconductor structure, the gate cut dielectric component overlaps with the front side contact. In some embodiments, in a top view, the back side contact overlaps with the gate cut dielectric component. In some embodiments, the metal gate stack includes a gate dielectric layer and a gate electrode layer, and the back side contact physically contacts the gate electrode layer. In some embodiments, the metal gate stack intersects an end portion of the active region. In some embodiments, the active region is a first active region and the epitaxial component is a first epitaxial component, and the semiconductor structure further includes a second epitaxial component disposed in the second active region. The front side contact is disposed directly above the first epitaxial component and the second epitaxial component and is electrically coupled to the first epitaxial component and the second epitaxial component. In some embodiments, the first epitaxial component is a p-type epitaxial component and the second epitaxial component is an n-type epitaxial component.

[0070] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: an active region, including a semiconductor substrate, a stack of nanostructures located above the semiconductor substrate, and an epitaxial component located above the semiconductor substrate and adjacent to the nanostructure, the active region extending longitudinally in a first direction; an isolation component, disposed on the sidewall of the semiconductor substrate; a metal gate stack, wrapping each nanostructure, the metal gate stack extending longitudinally in a second direction perpendicular to the first direction; a first contact component, disposed directly above the epitaxial component and electrically coupled to the epitaxial component; and a second contact component, disposed directly below the first contact component and the metal gate stack and electrically coupled to the first contact component and the metal gate stack. The isolation component separates the second contact component from physically contacting the semiconductor substrate. In some embodiments, the first contact component extends longitudinally in the second direction, and the second contact component extends longitudinally in the first direction. In some embodiments, in a cross-sectional view of the semiconductor structure cut along the first direction, the second contact component partially covers the bottom surface of the metal gate stack. In some embodiments, in a cross-sectional view of the semiconductor structure cut along the first direction, the second contact component completely covers the bottom surface of the metal gate stack. In some embodiments, in a top view of the semiconductor structure, the second contact component is spaced apart from the active region. In some embodiments, a top surface of the second contact component is below a top surface of the semiconductor substrate. In some embodiments, a top surface of the second contact component is above a top surface of the semiconductor substrate.

[0071] In yet another exemplary aspect, the present disclosure relates to a static random access memory (SRAM) cell. The SRAM cell includes: a first active region and a second active region, extending longitudinally along a first direction; a first metal gate stack, intersecting the first active region when forming a first pull-up transistor of the SRAM cell; a second metal gate stack, intersecting the second active region when forming a second pull-up transistor of the SRAM cell; a first contact component, disposed between the first metal gate stack and the second metal gate stack and extending longitudinally along a second direction perpendicular to the first direction, the first contact component being disposed above a source / drain component of the first pull-up transistor and electrically connected to the source / drain component of the first pull-up transistor; and a second contact component, physically contacting a bottom surface of the first contact component and a bottom surface of the second metal gate stack. In a top view of the SRAM cell, the second contact component is spaced apart from a bottom surface of the source / drain component of the first pull-up transistor. In some embodiments, the second metal gate stack intersects an end portion of the first active region. In some embodiments, the second metal gate stack includes a gate dielectric layer and a gate electrode layer, and the gate electrode layer is exposed in a bottom surface of the second metal gate stack and is in physical contact with the second contact feature.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: An epitaxial component is disposed in the active region; a front side contact disposed directly on the epitaxial component and electrically coupled to the epitaxial component; a metal gate stack; an internal spacer between the metal gate stack and the epitaxial component; as well as A backside contact is in physical contact with a bottom portion of the metal gate stack and in physical contact with a bottom portion of the frontside contact.

2. The semiconductor structure according to claim 1, wherein: In a top view of the semiconductor structure, the backside contact and the active area have no overlapping region.

3. The semiconductor structure according to claim 1, further comprising: A dielectric structure separates the backside contacts from physically contacting the epitaxial features.

4. The semiconductor structure according to claim 1, wherein: The sidewalls of the backside contact directly interface with the sidewalls of the epitaxial feature.

5. The semiconductor structure according to claim 1, further comprising: A gate cut dielectric feature is adjacent to the metal gate stack, wherein the gate cut dielectric feature overlaps the front side contact in a top view of the semiconductor structure.

6. The semiconductor structure according to claim 5, wherein: In the top view, the backside contact overlaps the gate cut dielectric feature.

7. The semiconductor structure according to claim 1, wherein: The metal gate stack includes a gate dielectric layer and a gate electrode layer, and wherein the backside contact physically contacts the gate electrode layer.

8. The semiconductor structure according to claim 1, wherein: The metal gate stack intersects an end portion of the active region.

9. A semiconductor structure comprising: an active region including a semiconductor substrate, a stack of nanostructures located above the semiconductor substrate, and an epitaxial component located above the semiconductor substrate and adjacent to the nanostructures, the active region extending longitudinally in a first direction; An isolation component, disposed on a side wall of the semiconductor substrate; a metal gate stack wrapping each of the nanostructures, the metal gate stack extending longitudinally in a second direction perpendicular to the first direction; a first contact component disposed directly on the epitaxial component and electrically coupled to the epitaxial component; as well as a second contact feature disposed directly below and electrically coupled to the first contact feature and the metal gate stack, The isolation component separates the second contact component from physically contacting the semiconductor substrate.

10. A static random access memory (SRAM) cell comprising: The first active region and the second active region extend longitudinally along a first direction; a first metal gate stack intersecting the first active region when forming a first pull-up transistor of the SRAM cell; a second metal gate stack intersecting the second active region when forming a second pull-up transistor of the SRAM cell; a first contact feature disposed between the first metal gate stack and the second metal gate stack and extending longitudinally along a second direction perpendicular to the first direction, wherein the first contact feature is disposed above a source / drain feature of the first pull-up transistor and is electrically connected to the source / drain feature of the first pull-up transistor; and a second contact feature in physical contact with a bottom surface of the first contact feature and a bottom surface of the second metal gate stack, Wherein, in a top view of the static random access memory cell, the second contact feature is spaced apart from a bottom surface of the source / drain feature of the first pull-up transistor.

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