A power switching transistor

Abstract

The application relates to a power switch transistor and belongs to the field of semiconductor power devices. The transistor comprises a drift region, a semiconductor body region, a terminal voltage resistance region, a floating electrode semiconductor region, a gate insulating medium region, a third electrode polycrystalline semiconductor region, a first insulating passivation layer, a second insulating passivation layer, a second electrode metal region, a floating electrode metal region, a third electrode metal region, a first electrode semiconductor region and a first electrode metal region. The second insulating passivation layer and the second electrode surface metal layer form a terminal metal shielding structure, the influence of a packaging lead or a copper belt on the terminal voltage resistance region of the power switch transistor chip can be effectively eliminated, the breakdown voltage of the chip is ensured not to be disturbed, the length of the packaging lead or the copper belt can be further shortened, even without lead bonding, so that the area occupied by the chip packaging lead and the parasitic inductance introduced by the lead are reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices and relates to a power switching transistor. Background Technology

[0002] Power switching transistors (PSTs) are indispensable basic electronic components in power electronic systems and are among the most widely used power semiconductor devices. Their main function is to control the switching between high voltage and high current. Common power switching transistors include power MOSFETs and IGBTs. In practical applications, power switching transistors can appear as single transistors or in modules. A single transistor typically contains only one power switching transistor chip; while a module often includes multiple chips, such as a single-phase full-bridge inverter module containing four power switching transistor chips. In some switching power modules, power switching transistor chips are used in conjunction with power diode chips. Regardless of whether it is a single transistor or a module, the electrodes on the surface of the power switching transistor chip need to be connected to the electrodes of other chips or the leads of the casing, generally using wire bonding or copper strip bonding. Due to limitations such as electrical isolation and manufacturing processes, longer wires or copper strips occupy space and introduce parasitic inductance, thus affecting switching speed and increasing switching losses. Therefore, advanced packaging technology reduces device area and parasitic inductance by continuously shortening the length of wires or copper strips. However, shortening the length of wires or copper strips may affect the breakdown voltage of the chip.

[0003] Power switching transistors often need to withstand high voltages. Therefore, in addition to the active region used for conduction, power switching transistor chips typically have terminating voltage regions around the active region. Common terminating voltage regions include field-limiting rings, field plates, and junction termination extension injection. When a power switching transistor chip withstands a high blocking voltage, the terminating voltage regions absorb the high voltage distributed along the surface. This high voltage not only appears inside and on the surface of the chip but also forms an electric field above the terminating voltage regions. Conductive materials such as metals (e.g., leads and copper strips) above the terminating voltage regions affect the electric field distribution, ultimately affecting the chip's breakdown voltage. Therefore, during wire bonding for packaging, the leads or copper strips are often curved to maintain a certain distance from the terminating voltage regions of the chip, avoiding interference with the chip's breakdown voltage. However, increasing the length of the curved leads or copper strips occupies more space. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a power switching transistor that, by setting a shielding structure on the voltage withstand region of the transistor terminal, eliminates the influence of the package lead or copper strip on the voltage withstand region of the power switching transistor chip terminal, ensures that the breakdown voltage of the chip is not disturbed, and allows the length of the package lead or copper strip to be further shortened, or even eliminated by wire bonding, thereby reducing the volume occupied by the chip package lead and the parasitic inductance introduced by the lead.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A power switching transistor, the transistor device comprising:

[0007] Drift zone;

[0008] The semiconductor bulk region is formed in the drift region and is flush with the upper surface of the drift region;

[0009] The terminal withstand voltage region is formed in the drift region and distributed on both sides of the semiconductor body region. The upper surface of the terminal withstand voltage region is flush with the upper surface of the drift region.

[0010] The floating electrode semiconductor region is formed in the drift region and distributed on both sides of the semiconductor body region. The upper surface of the floating electrode semiconductor region is flush with the upper surface of the drift region. The floating electrode semiconductor region is located outside the terminal withstand voltage region.

[0011] The gate insulating dielectric region has multiple portions, which are formed alternately on the upper surface of the semiconductor bulk region;

[0012] The third electrode polycrystalline semiconductor region is formed in each part of the gate insulating dielectric region;

[0013] The first insulating passivation layer is formed on the upper surface of the drift region and the terminal withstand voltage region, and is distributed on both sides of the outer gate insulating dielectric region.

[0014] The second insulating passivation layer is formed on the upper surface of the first insulating passivation layer on both sides;

[0015] The second electrode metal region is formed on the upper surface of the drift region and between the first and second insulating passivation layers on both sides, filling the gaps between the gate insulating dielectric regions, and the second electrode metal region extends to the top surface of the transistor device, thereby covering part of the second insulating passivation layer.

[0016] The floating electrode metal region is formed on the upper surface of the floating electrode semiconductor region and is surrounded by the first insulating passivation layer.

[0017] The third electrode metal region is formed in part on the upper surface of the second insulating passivation layer that is not covered by the second electrode metal region, and in another part the third electrode metal region penetrates the second insulating passivation layer and the first insulating passivation layer and extends to the surface of the third electrode polycrystalline semiconductor region.

[0018] The first electrode semiconductor region is formed on the lower surface of the drift region;

[0019] The first electrode metal region is formed on the lower surface of the first electrode semiconductor region.

[0020] The top surface of the transistor device is covered by the second and third electrode metal regions, forming two equipotential surfaces.

[0021] The semiconductor body region may have multiple parts, which are separated by drift regions. A semiconductor source region is formed in each part of the semiconductor body region, and the upper surface of the semiconductor source region is flush with the upper surface of the semiconductor body region. Based on the multiple semiconductor body regions, a gate insulating dielectric region is formed above each pair of adjacent semiconductor body regions. The lower surface of each gate insulating dielectric region is in contact with the upper surfaces of the semiconductor body region, the semiconductor source region, and the drift region, respectively.

[0022] Optionally, a second electrode metal region is formed on the upper surface of the drift region and between the first and second insulating passivation layers on both sides, filling the gaps between the various gate insulating dielectric regions. The second electrode metal region has a groove, with the second electrode metal regions on both sides extending to the top surface of the transistor device and covering the second insulating passivation layers on both sides. In this groove, a first insulating passivation layer and a second insulating passivation layer are formed, stacked sequentially from bottom to top. Based on this structure, a portion of the third electrode metal region is formed on the upper surface of the second insulating passivation layer in the groove, and another portion penetrates the second and first insulating passivation layers in the groove, extending to the surface of the third electrode polycrystalline semiconductor region. Thus, the second and third electrode metal regions form two equipotential surfaces on the top surface of the transistor device.

[0023] Optionally, multiple gate insulating dielectric regions may extend into the drift region, wherein the portions of the gate insulating dielectric regions located in the drift region are respectively in contact with the semiconductor body region on both sides.

[0024] The beneficial effects of this invention are as follows: By introducing an insulating passivation layer to form a terminal metal shielding structure, this invention can effectively eliminate the influence of the packaging leads or copper strips on the terminal withstand voltage area of ​​the power switching transistor chip, ensuring that the breakdown voltage of the chip is not disturbed. Compared with the conventional power switching transistor structure, this invention can further shorten the length of the packaging leads or copper strips, or even eliminate the need for wire bonding, thereby reducing the area occupied by the chip packaging leads and the parasitic inductance introduced by the leads.

[0025] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0027] Figure 1 This is a schematic diagram of the power switching transistor structure provided in Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of the power switching transistor structure provided in Embodiment 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of the power switching transistor structure provided in Embodiment 3 of the present invention;

[0030] Figure 4 This is a schematic diagram of the power switching transistor structure provided in Embodiment 4 of the present invention.

[0031] Reference numerals: 1-First electrode metal region; 2-Second electrode metal region; 3-Third electrode metal region; 4-Floating electrode metal region; 5-First electrode semiconductor region; 6-Drift region; 7-Semiconductor source region; 8-Floating electrode semiconductor region; 9-Semiconductor body region; 10-Terminal withstand voltage region; 11-Gate insulating dielectric region; 12-First insulating passivation layer; 13-Second insulating passivation layer; 14-Third electrode polycrystalline semiconductor region. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0034] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0035] To minimize the impact on the breakdown voltage region of a power switching transistor chip while shortening the length of the package leads or copper strip, this invention proposes a terminal metal shielding structure. This effectively eliminates the influence of the package leads or copper strip on the breakdown voltage region of the power switching transistor chip, ensuring that the chip's breakdown voltage is not disturbed. This allows for further shortening of the package leads or copper strip length, or even eliminating the need for wire bonding, thereby reducing the volume occupied by the chip package leads and the parasitic inductance introduced by the leads. The power switching transistor proposed in this invention will be described in detail below with several embodiments.

[0036] Example 1

[0037] like Figure 1 As shown, the power switching transistor provided in this embodiment includes:

[0038] The first type of conductivity semiconductor lightly doped drift region 6;

[0039] The first electrode semiconductor region 5 is located below the drift region 6. The first electrode semiconductor region 5 is in contact with the drift region 6, and the first electrode semiconductor region 5 is heavily doped compared to the drift region 6. It can be either the first type of conductivity or the second type of conductivity.

[0040] The first electrode metal region 1 is located below the first electrode semiconductor region 5, and the first electrode semiconductor region 5 is in contact with the first electrode metal region 1;

[0041] Multiple semiconductor body regions 9 of the second conductivity type, a terminal withstand voltage region 10 of the second conductivity type, and a floating electrode semiconductor region 8 are disposed inside the drift region 6; wherein, the semiconductor body regions 9 and the terminal withstand voltage region 10 are surrounded by the drift region 6; among the multiple semiconductor body regions 9, the semiconductor body regions on both sides are in contact with the terminal withstand voltage region 10 respectively; multiple semiconductor source regions 7 of the first conductivity type are disposed inside the semiconductor body regions 9, the semiconductor source regions 7 are surrounded by the semiconductor body regions, and the semiconductor source regions 7 are heavily doped;

[0042] A gate insulating dielectric region 11 is disposed on an adjacent semiconductor body region 9, and the gate insulating dielectric region 11 covers part of the semiconductor source region 7, part of the semiconductor body region 9 and part of the drift region 6;

[0043] The third electrode polycrystalline semiconductor region 14 is embedded inside each gate insulating dielectric region 11, wherein the third electrode polycrystalline semiconductor region 14, part of the gate insulating dielectric region 11, part of the semiconductor source region 7, part of the semiconductor body region 9 and part of the drift region 6 constitute the MOS cell structure.

[0044] A second electrode metal region 2 is provided on the MOS cell structure and the terminal withstand voltage region 10. The second electrode metal region 2 covers the top surface and both sides of a portion of the semiconductor source region 7, a portion of the semiconductor body region 9, a portion of the terminal withstand voltage region 10, and the gate insulating dielectric region 11. The second electrode metal region 2 forms a groove.

[0045] The floating electrode semiconductor region 8 is located in the drift region 6 and distributed on both sides of the terminal withstand voltage region 10;

[0046] The floating electrode metal region 4 is disposed above the floating electrode semiconductor region 8 on both sides, and the floating electrode metal region is in contact with the top surface of part of the floating electrode semiconductor region 8.

[0047] The first insulating passivation layer 12 is located above the terminal withstand voltage region 10 on both sides and in the groove of the second electrode metal region 2. The first insulating passivation layer 12 covers part of the floating electrode semiconductor region 8, part of the drift region 6 and part of the terminal withstand voltage region 10. The floating electrode metal region 4 is surrounded by the first insulating passivation layer 12.

[0048] The second insulating passivation layer 13 is located above the three-part first insulating passivation layer 10, and the bottom surface of the second insulating passivation layer 13 is in contact with the top surface of the first insulating passivation layer 12.

[0049] A third electrode metal region 3 is disposed on the upper surface of the second insulating passivation layer 13 located in the groove of the second electrode metal region 2.

[0050] The second electrode metal region is divided into three parts: upper, middle, and lower. The lower part of the second electrode metal region is embedded in the first insulating passivation layer. The middle part of the second electrode metal region passes through the second insulating passivation layer and is embedded in the first insulating passivation layer. The upper part of the second electrode metal region is located on the second insulating passivation layer, and its bottom surface is connected to the top surface of the second insulating passivation layer.

[0051] The third electrode metal region is divided into upper and lower parts. The lower part of the third electrode metal region passes through the second insulating passivation layer, the first insulating passivation layer and the gate insulating dielectric region until the bottom surface of the lower part of the third electrode metal region contacts the top surface of the third electrode polycrystalline semiconductor region. The upper part of the third electrode metal region is located above the second insulating passivation layer, and its bottom surface is connected to the top surface of the second insulating passivation layer.

[0052] This embodiment introduces a thicker second insulating passivation layer into the power switching transistor chip, while simultaneously thickening the second and third electrode metal regions and extending them to the chip surface, making the chip surface two equipotential surfaces. When the power switching transistor withstands a high blocking voltage, the electric field above the chip's terminal withstand voltage region is confined within the insulating passivation layer, determined by the thickness and dielectric constant of the insulating passivation layer. This shields the electric field in the terminal withstand voltage region from the effects of connecting metal lines (such as leads, copper strips, etc.) passing through the chip surface, ensuring that the chip's breakdown voltage is unaffected. The thickness of the second insulating passivation layer must be appropriately set to ensure it is not broken down by high blocking voltages and operates safely and reliably.

[0053] When the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0054] When the first electrode semiconductor region 5 is of the first conductivity type, the power switching transistor is a MOSFET structure, with the first electrode being the drain, the second electrode being the source, and the third electrode being the gate; when the first electrode semiconductor region 5 is of the second conductivity type, the power switching transistor is an IGBT structure, with the first electrode being the collector, the second electrode being the emitter, and the third electrode being the gate.

[0055] The semiconductor region can be made of silicon, or it can be made of germanium, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, diamond, or aluminum nitride, etc.

[0056] The terminal pressure-resistant zone 10 can be a floating field limiting ring, a junction terminal extension, a field plate, or a combination of a floating field limiting ring, a junction terminal extension, and a field plate.

[0057] Example 2

[0058] like Figure 2As shown, compared with the device proposed in Embodiment 1, this embodiment does not have a groove in the second electrode metal region 2 and reduces the width of the second electrode metal region 2 in the lateral direction, thereby increasing the width of the second insulating passivation layer 13 on one side of the second electrode metal region 2 in the lateral direction; at the same time, the third electrode metal region 3 is disposed on the upper surface of the second insulating passivation layer 13 on one side of the second electrode metal region 2, so that the second electrode metal region 2 and the third electrode metal region 3 are still extended to the surface of the transistor chip, making the chip surface into two equipotential surfaces.

[0059] Example 3

[0060] like Figure 3 As shown, compared with the device proposed in Embodiment 1, this embodiment extends the gate insulating dielectric region 11 into the drift region 6 to form a trench-type MOS cell structure, and the left and right sides of the portion of the gate insulating dielectric region 11 located in the drift region 6 are in contact with the semiconductor source region 7 and the semiconductor body region 9. In addition, the polycrystalline semiconductor region 14 located in the gate insulating dielectric region 11 is also extended vertically accordingly, but does not protrude outside the gate insulating dielectric region 11.

[0061] Example 4

[0062] like Figure 4 As shown, compared with the device proposed in Embodiment 2, this embodiment extends the gate insulating dielectric region 11 into the drift region 6 to form a trench-type MOS cell structure, and the left and right sides of the portion of the gate insulating dielectric region 11 located in the drift region 6 are in contact with the semiconductor source region 7 and the semiconductor body region 9. In addition, the polycrystalline semiconductor region 14 located in the gate insulating dielectric region 11 is also extended vertically accordingly, but does not protrude outside the gate insulating dielectric region 11.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A power switching transistor, characterized in that, It includes: Drift zone; A semiconductor body region is formed in the drift region and is flush with the upper surface of the drift region; A terminal withstand voltage region is formed in the drift region and distributed on both sides of the semiconductor body region, and the upper surface of the terminal withstand voltage region is flush with the upper surface of the drift region. A floating electrode semiconductor region is formed in the drift region and distributed on both sides of the semiconductor body region. The upper surface of the floating electrode semiconductor region is flush with the upper surface of the drift region. Gate insulating dielectric regions, wherein a plurality of gate insulating dielectric regions are formed at intervals on the upper surface of the semiconductor body region; The third electrode polycrystalline semiconductor region is formed in a plurality of gate insulating dielectric regions; A first insulating passivation layer is formed on the upper surface of the drift region and the terminal withstand voltage region, and is distributed on both sides of the outer gate insulating dielectric region. A second insulating passivation layer is formed on the upper surface of the first insulating passivation layer on both sides; The second electrode metal region is formed between the first and second insulating passivation layers on the upper surface of the drift region and on both sides, filling the intervals of the plurality of gate insulating dielectric regions, and the second electrode metal region extends to the top surface of the transistor device to cover part of the second insulating passivation layer, and extends to the edge of the upper surface of the device. The floating electrode metal region is formed on the upper surface of the floating electrode semiconductor region on both sides and is surrounded by the first insulating passivation layer. The third electrode metal region is partially formed on the upper surface of the second insulating passivation layer not covered by the second electrode metal region, and the other part of the third electrode metal region penetrates the second insulating passivation layer and the first insulating passivation layer, and extends to the surface of the third electrode polycrystalline semiconductor region. By covering the transistor surface with the second electrode metal region and the third electrode metal region, the transistor surface becomes two equipotential surfaces. At the same time, by introducing the first insulating passivation layer and the second insulating passivation layer, a terminal metal shielding structure is formed to eliminate the influence of the package lead or copper strip on the transistor terminal withstand voltage region, ensure that the breakdown voltage of the transistor is not disturbed, and reduce the area occupied by the transistor package lead and the parasitic inductance introduced by the lead. A first electrode semiconductor region is formed on the lower surface of the drift region; A first electrode metal region is formed on the lower surface of the first electrode semiconductor region; The semiconductor body region has multiple parts, which are separated by the drift region; a semiconductor source region is formed in each semiconductor body region, and the upper surface of the semiconductor source region is flush with the upper surface of the semiconductor body region.

2. The power switching transistor according to claim 1, characterized in that, Multiple gate insulating dielectric regions are formed on the upper surface of the semiconductor body region, wherein a gate insulating dielectric region is formed above each two adjacent semiconductor body regions; the lower surface of each gate insulating dielectric region is in contact with the upper surfaces of the semiconductor body region, the semiconductor source region and the drift region, respectively.

3. The power switching transistor according to claim 1, characterized in that, The second electrode metal region is formed on the upper surface of the drift region and between the first and second insulating passivation layers on both sides, filling the gaps between the plurality of gate insulating dielectric regions. The second electrode metal region has a groove, and the second electrode metal regions on both sides of the groove extend to the top surface of the transistor device and cover the second insulating passivation layers on both sides. The first and second insulating passivation layers are formed in the groove in sequence from bottom to top. A portion of the third electrode metal region is formed on the upper surface of the second insulating passivation layer in the groove, and another portion penetrates the second and first insulating passivation layers in the groove and extends to the surface of the third electrode polycrystalline semiconductor region.

4. The power switching transistor according to claim 1, characterized in that, The plurality of gate insulating dielectric regions extend into the drift region, and the portions of the gate insulating dielectric regions located in the drift region are respectively in contact with the semiconductor body region on both sides.

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