Thin film transistor based on ultra wide band gap semiconductor GeO2 structure and preparation method thereof

Abstract

The thin film transistor based on the ultra wide band gap semiconductor GeO2 structure comprises a gate dielectric layer and a channel layer, the channel layer is arranged above the gate dielectric layer, and the channel layer is a Sn-doped amorphous GeO2 thin film. According to the thin film transistor provided by the embodiment of the invention, the conversion of amorphous GeO2 from an insulator to a semiconductor is successfully realized through Sn doping, and the application of GeO2 in high-performance and high-power electronic devices can be realized. The embodiment of the invention also provides a preparation method of the thin film transistor based on the ultra wide band gap semiconductor GeO2 structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor material technology, and more particularly to a method for producing a semiconductor material based on an ultra-wide bandgap semiconductor GeO 2 Thin film transistor with structure and method for preparing the same. Background Art

[0002] Ultra-wide bandgap (UWBG) semiconductors have been widely studied for their potential applications in power devices and solar-blind detectors. Wide bandgap compound semiconductor materials such as fourth-generation semiconductor gallium oxide have a wide bandgap that leads to a higher breakdown electric field, thereby achieving high-power switching with lower energy loss.

[0003] However, ultra-wide bandgap semiconductors are limited by inherent material properties in terms of doping asymmetry, which hinders their application in CMOS technology. 2 , despite having an ultra-wide bandgap of about 4.7 eV, it still has light electron and hole effective masses, and its electron effective mass is comparable to other n-type such as β-Ga 2 O 3 Similar to GeO, but the effective mass of holes is much smaller than them. This means that it is potentially feasible to dope p-type. At the same time, it has a higher breakdown field and thermal conductivity. 2 The work is still limited to theoretical research and characterization of materials, lacking GeO 2 Exploration of devices as semiconductor channel layers. Summary of the invention

[0004] In view of the problems existing in the above-mentioned related technologies, the present invention provides a method for 2 A thin film transistor with a structure and a method for preparing the same have been successfully realized by Sn doping in amorphous GeO 2 The transition from insulator to semiconductor enables GeO 2 Applications in high performance and high power electronic devices.

[0005] In the first aspect, the present application embodiment proposes a method based on an ultra-wide bandgap semiconductor GeO 2 The thin film transistor of the structure comprises a gate dielectric layer and a channel layer, wherein the channel layer is arranged above the gate dielectric layer, and the channel layer is Sn-doped amorphous GeO 2 film.

[0006] Furthermore, the gate dielectric layer is made of SiO 2 Made.

[0007] Furthermore, it also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

[0008] Furthermore, it also includes a source electrode and a drain electrode, and the source electrode and the drain electrode are arranged above the channel layer.

[0009] Furthermore, it also includes a substrate, which is arranged below the gate electrode layer, and the substrate is made of P-type heavily doped Si and SiO 2 Made.

[0010] In a second aspect, an embodiment of the present application further provides a method for preparing a thin film transistor, which is used to prepare a thin film transistor as described in any one of the above items, comprising the following steps:

[0011] preparing a gate dielectric layer on a surface of a substrate;

[0012] On the surface of the gate dielectric layer, Sn-doped GeO is deposited by sputtering using Sn target and Ge target simultaneously. 2 A thin film is formed to form the channel layer.

[0013] Furthermore, Sn-doped GeO is deposited on the surface of the gate dielectric layer by sputtering using Sn target and Ge target simultaneously. 2 A thin film to form the channel layer, comprising:

[0014] The Sn-doped GeO is deposited on the surface of the gate dielectric layer by magnetron sputtering using Sn target and Ge target simultaneously. 2 A thin film is formed to form the channel layer.

[0015] Furthermore, in the substrate surface, SiO 2 Before the material is made into a gate dielectric layer, it also includes:

[0016] Using P-type heavily doped Si and SiO 2 Material preparation substrate;

[0017] The substrate is cleaned.

[0018] Further, the cleaning of the substrate comprises:

[0019] The substrate is placed in an ultrasonic instrument and ultrasonically cleaned using acetone, anhydrous ethanol and deionized water respectively.

[0020] Furthermore, Sn-doped GeO is deposited on the surface of the gate dielectric layer by sputtering using Sn target and Ge target simultaneously. 2 The thin film, after forming the channel layer, further comprises:

[0021] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0022] The thin film transistor provided in the embodiment of the present application includes a gate dielectric layer and a channel layer. The channel layer is arranged above the gate dielectric layer. The channel layer is made of Sn-doped amorphous GeO 2 Sn doping successfully achieved amorphous GeO 2 The transition from insulator to semiconductor, the prepared device has good field effect and large breakdown voltage, and can synthesize GeO through low-cost and efficient preparation methods 2 Thin films, through appropriate doping, can achieve GeO 2 Applications in high performance and high power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a transfer characteristic curve of a thin film transistor provided in an embodiment of the present application when scanned at different channel lengths;

[0026] Figure 3 A schematic diagram of the breakdown characteristics of a thin film transistor provided in an embodiment of the present application when a voltage is applied to both ends of the source and drain;

[0027] Figure 4 A schematic diagram of a process for preparing a thin film transistor provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the actual preparation process of the thin film transistor provided in an embodiment of the present application.

[0029] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, the singular forms of "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0033] Reference Figure 1 The present application embodiment proposes a method based on an ultra-wide bandgap semiconductor GeO 2 The thin film transistor 100 of the structure of GeO2 includes a gate dielectric layer 110 and a channel layer 120. The channel layer 120 is arranged above the gate dielectric layer 110. The channel layer 120 is made of Sn-doped amorphous GeO 2 (Sn-doped GeO 2 ) is made.

[0034] Specifically, Figure 1 As shown, the thin film transistor 100 includes a gate dielectric layer 110 and a channel layer 120. The channel layer 120 is disposed above the gate dielectric layer 110. The channel layer 120 is made of Sn-doped amorphous GeO 2 Sn doping successfully achieved amorphous GeO 2 The transition from insulator to semiconductor, the prepared device has good field effect and large breakdown voltage, and can synthesize GeO through low-cost and efficient preparation methods 2 Thin films, through appropriate doping, can achieve GeO 2 Applications in high performance and high power electronic devices.

[0035] Reference Figure 2 , Figure 2The transfer characteristic curve diagram of the thin film transistor provided in the embodiment of the present application under different channel lengths is shown in the figure. The test results show that as the channel length decreases, the on-off ratio of the device gradually increases and the subthreshold swing gradually decreases. When the channel length is 10 μm, the on-off ratio reaches 3.87×10 5 , indicating that P-type heavily doped Si / SiO 2 Sn-doped GeO on substrate 2 Amorphous thin film transistors have good field effects, and GeO was first verified by physical vapor deposition. 2 Device feasibility as a channel layer.

[0036] Reference Figure 3 , Figure 3 The schematic diagram of the breakdown characteristics of the thin film transistor provided in the embodiment of the present application when voltage is applied to both ends of the source and drain. The test process is to apply voltage to both ends of the source electrode and the drain electrode. As the voltage between the source and the drain gradually increases, the device is broken down at 260V. 2 The thin film transistor exhibits a large breakdown voltage even though its channel layer thickness is less than 30nm. The above test proves that the embodiment of the present application provides a thin film transistor based on ultra-wide bandgap semiconductor GeO 2 The method for preparing a thin film transistor has good voltage resistance characteristics.

[0037] The above results show that the novel ultra-wide bandgap semiconductor GeO 2 The thin film transistor has the advantages of good field effect and high breakdown voltage and can be applied to power semiconductor devices.

[0038] It should be noted that the length of the channel layer 120 of the thin film transistor 100 is preferably 10 μm, 20 μm, 30 μm and 40 μm, and the thickness of the channel layer 120 does not exceed 28.5 nm.

[0039] Further, refer again to Figure 1 In some embodiments of the present application, the gate dielectric layer 110 is made of SiO 2 Made.

[0040] Specifically, SiO 2 As a gate dielectric layer, it has high insulation performance and stability, and can effectively isolate the gate and the channel to prevent the generation of leakage current.

[0041] Furthermore, if Figure 1 As shown, in some embodiments of the present application, the thin film transistor 100 proposed in the embodiments of the present application further includes a gate electrode layer 130, and the gate electrode layer 130 is arranged below the gate dielectric layer 100, and the gate electrode layer 130 is made of P-type heavily doped Si.

[0042] Specifically, the gate electrode layer 130 controls the current between the drain and the source by changing the gate voltage. When the gate voltage is zero or a negative voltage, the channel is in a closed state, and the current between the drain and the source is almost zero. When the gate voltage is reduced to a certain value, the channel opens, allowing current to pass. Of course, the gate electrode layer 130 of the thin film transistor 100 proposed in the embodiment of the present application can also adopt an enhanced control method to control the opening or closing of the channel. The gate electrode layer 130 of the thin film transistor provided in the embodiment of the present application is made of P-type heavily doped Si.

[0043] Furthermore, in some embodiments of the present application, the thin film transistor 100 provided in the embodiments of the present application further includes a source electrode 140 and a drain electrode 150 , and the source electrode 140 and the drain electrode 150 are disposed above the channel layer 120 .

[0044] Specifically, the source electrode 140 is the output end of the current, and the carriers (electrons) enter from the source electrode. The drain electrode 150 is the input end of the current, and the carriers are discharged from the drain electrode 150. The source electrode 140 and the drain electrode 150 are arranged above the channel layer 120. The materials of the source electrode and the drain electrode are composed of a layer of Ti with a thickness of 10nm and a layer of Au with a thickness of 50nm.

[0045] Furthermore, if Figure 1 As shown, in some embodiments of the present application, the thin film transistor 100 provided in the embodiment of the present application further includes a substrate (not shown), the substrate is arranged below the gate electrode layer 130, and the substrate is composed of P-type heavily doped Si and SiO 2 Made.

[0046] Specifically, the main function of the substrate is to connect various parts of the transistor and play a role of stability and support. The substrate of the thin film transistor 100 provided in the embodiment of the present application is arranged below the gate electrode layer 130. The substrate is composed of P-type heavily doped Si and SiO 2 It is made of two layers of materials, the first layer is Si and the second layer is SiO 2 .

[0047] Second, refer to Figure 4 The present application also provides a method for preparing a thin film transistor, which is used to prepare a thin film transistor as described in any one of the above items, comprising the following steps:

[0048] S101: preparing a gate dielectric layer on the surface of the substrate;

[0049] S101: On the surface of the gate dielectric layer, Sn target and Ge target are simultaneously used to sputter and deposit Sn-doped GeO 2 A thin film is formed to form the channel layer.

[0050] The method for preparing a thin film transistor provided in the embodiment of the present application does not require a complex and difficult-to-control process, and realizes the ultra-wide bandgap semiconductor GeO 2 As a thin film transistor of the channel layer, high-quality semiconductor films can be obtained in a short time at room temperature, and Sn doping can successfully realize amorphous GeO 2 The transition from insulator to semiconductor, the prepared device has good field effect and large breakdown voltage, and GeO can be synthesized through low-cost and efficient preparation methods. 2 thin film, promoting the 2 Exploration of application as device channel layer in high performance and high power electronic devices.

[0051] The method for preparing a thin film transistor provided in an embodiment of the present application is to heavily dope Si / SiO 2 Sn-doped GeO is set on the substrate 2 The channel layer of the film forms a three-terminal transistor device with a bottom-gate structure; on the one hand, the present invention is based on a new ultra-wide bandgap semiconductor GeO 2 The method for preparing a thin film transistor using a P-type heavily doped Si / SiO 2 As a substrate, it has a highly mature process and good Si / SiO 2 interface characteristics; on the other hand, by selecting appropriate doping (Sn doping) and its doping power, GeO 2 The transition of the film from an insulator to a semiconductor can accurately simulate the switching behavior of the field effect transistor, has good electrical properties, and has a high breakdown voltage. Finally, Ti / Au electrodes are prepared by photolithography and electron beam evaporation to form ohmic contact between the electrode and the semiconductor film interface, thereby enhancing the electrical properties and device reliability.

[0052] Further, refer to Figure 5 In some embodiments of the present application, Sn-doped GeO is deposited on the surface of the gate dielectric layer by sputtering using Sn target and Ge target at the same time. 2 A thin film to form the channel layer, comprising:

[0053] The Sn-doped GeO is deposited on the surface of the gate dielectric layer by magnetron sputtering using a Sn target and a Ge target at the same time. 2 Thin film (Sn-doped GeO 2 A thin film) is formed to form the channel layer.

[0054] Figure 5 The ultra-wide bandgap semiconductor GeO provided in this embodiment 2Schematic diagram of the actual preparation process of the room temperature co-sputtering growth channel layer involved in the preparation method of the thin film transistor of the structure. During the preparation process, it is necessary to adjust the distance from the target to the substrate and the sputtering angle within a suitable range to promote the uniformity and quality of the film. If the distance between the target and the substrate is short, the sputtered atoms with high kinetic energy will destroy the film, and the narrow sputtering area will reduce the uniformity of the film. When the distance between the target and the substrate is long, more impurities will be deposited, thereby reducing the quality of the grown film.

[0055] In the above steps, the vacuum degree of the chamber where the film is grown during sputtering is less than 10 -4 Pa, working pressure is 1Pa, Sn sputtering power is 8W, Ge sputtering power is 30W, sputtering gas Ar is introduced with a flow rate of 20sccm, and reaction gas O is introduced 2 , flow rate 4sccm, time 3600s, target materials are Sn target and Ge target. Among them, in the process of setting the two sputtering power parameters, it is found that when the sputtering power of the Sn target is low, the conductivity is very poor and it behaves as an insulator. When the sputtering power of the Sn target is too high, the conductivity is too strong and it behaves as a conductor; both have no normal semiconductor characteristics. When the sputtering power of the Ge target is lower than 30W, it cannot be ignited normally. Increasing the sputtering power of the Ge target will reduce the conductivity of the film. Therefore, the sputtering power of the Ge target is fixed, and the semiconductor characteristics are adjusted by adjusting the sputtering power of the Sn target. At the same time, in the process of setting the film deposition time parameters, it is found that if the sputtering time is too short, it is difficult to form a uniform film, which affects the device characteristics. If the sputtering time is too long, the surface roughness becomes larger, the film defects increase, the device field control becomes weaker, and the characteristics deteriorate.

[0056] Furthermore, in some embodiments of the present application, SiO 2 Before the material is made into a gate dielectric layer, it also includes:

[0057] Using P-type heavily doped Si and SiO 2 Material preparation substrate; and

[0058] The substrate is cleaned.

[0059] Specifically, substrate cleaning is a crucial step in semiconductor processing. The purpose of cleaning is to remove contaminants on the substrate surface, which may include dust, grease, metal ions, organic matter, etc. These contaminants will affect the quality of subsequent process steps, such as lithography, etching, ion implantation, etc., thereby affecting the performance and reliability of the final device.

[0060] The cleaning step usually includes multiple sub-steps, such as chemical cleaning (using acidic or alkaline solutions to remove organic matter and metal ions), physical cleaning (using ultrasonic or sandblasting to remove solid particles), deionized water rinsing (removing residual chemicals and ions), etc. The specific methods and steps of cleaning depend on the type of substrate material, the type and concentration of contaminants, and the requirements of subsequent processes.

[0061] Further, in some embodiments of the present application, the cleaning of the substrate comprises:

[0062] The substrate is placed in an ultrasonic instrument and ultrasonically cleaned using acetone, anhydrous ethanol and deionized water respectively.

[0063] Specifically, the substrate is placed in an ultrasonicator and ultrasonically cleaned with acetone, anhydrous ethanol and deionized water in sequence to ensure that the substrate surface is thoroughly cleaned. This step is critical in semiconductor processing because it directly affects the quality of subsequent process steps and the performance of the final device.

[0064] After cleaning, the substrate usually needs to be dried to ensure that there is no residual moisture on the surface of the substrate. The drying method may include natural drying, hot air drying or vacuum drying, etc. The specific method depends on the type of substrate material and the requirements of the subsequent process.

[0065] Furthermore, in some embodiments of the present application, Sn-doped GeO is sputtered and deposited on the surface of the gate dielectric layer using both Sn and Ge targets. 2 The thin film, after forming the channel layer, further comprises:

[0066] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0067] Specifically, an electrode pattern is formed on the channel layer by photolithography, and then a layer of Ti film is deposited by electron beam evaporation, and then a layer of Au film is deposited on the Ti film by electron beam evaporation to form source and drain electrodes, wherein the source electrode and the drain electrode are both rectangular in shape, preferably 300 μm in length, and preferably 100 μm in width.

[0068] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A thin film transistor based on an ultra-wide bandgap semiconductor GeO2 structure, characterized in that: It comprises a gate dielectric layer and a channel layer. The channel layer is arranged above the gate dielectric layer and is a Sn-doped amorphous GeO2 film.

2. The thin film transistor according to claim 1, wherein: The gate dielectric layer is made of SiO2.

3. The thin film transistor according to claim 2, wherein: It also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

4. The thin film transistor according to claim 2, wherein: Also included is a source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed above the channel layer.

5. The method according to claim 2, characterized in that It also includes a substrate, which is arranged below the gate electrode layer and is made of P-type heavily doped Si and SiO2.

6. A method for preparing a thin film transistor, for preparing the thin film transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: preparing a gate dielectric layer on a surface of a substrate; On the surface of the gate dielectric layer, a Sn-doped GeO2 film is sputtered and deposited simultaneously using a Sn target and a Ge target to form the channel layer.

7. The method according to claim 6, characterized in that The method of simultaneously sputtering and depositing a Sn-doped GeO2 film on the surface of the gate dielectric layer using a Sn target and a Ge target to form the channel layer comprises: By adopting the magnetron sputtering method, Sn target and Ge target are simultaneously used to sputter and deposit Sn-doped GeO2 film on the surface of the gate dielectric layer to form the channel layer.

8. The method according to claim 6, characterized in that Before the gate dielectric layer is formed by using SiO2 material on the surface of the substrate, the method further comprises: The substrate is prepared by using P-type heavily doped Si and SiO2 materials; and The substrate is cleaned.

9. The method according to claim 8, characterized in that The step of cleaning the substrate comprises: The substrate is placed in an ultrasonic instrument and ultrasonically cleaned using acetone, anhydrous ethanol and deionized water respectively.

10. The method according to claim 6, characterized in that After simultaneously using a Sn target and a Ge target to sputter and deposit a Sn-doped GeO2 film on the surface of the gate dielectric layer to form the channel layer, the method further includes: An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

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