Thin film transistor based on high-k gate dielectric and GeO2 structure and preparation method thereof

Abstract

The thin film transistor comprises a gate dielectric layer and a channel layer, the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of high-K gate dielectric, and the channel layer is made of Sn-doped GeO2. According to the thin film transistor provided by the embodiment of the invention, the high-k gate medium is combined with the ultra-wide band gap semiconductor GeO2, so that the thermal stability and reliability of a device can be enhanced, the charge of the channel layer can be effectively controlled, and the electrical performance is remarkably improved. The embodiment of the invention also provides a preparation method of the thin film transistor.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor material technology, and in particular relates to a thin film transistor based on a high-k gate dielectric and GeO2 structure and a preparation method thereof. Background Art

[0002] As Moore's Law continues to drive the size of silicon-based transistors, this trend has led to a rapid increase in computing performance, but it has also posed unprecedented challenges to the manufacturing and design of semiconductor devices. As a key component in transistors, the continuous reduction in the thickness of the gate oxide layer has directly led to a series of problems such as increased tunneling current, increased power consumption, and reduced reliability.

[0003] The traditional Si / SiO2 structure has been unable to meet the future device's demand for low power consumption and high performance in the context of the continuous reduction in transistor size. As the size of the transistor decreases, the thickness of the gate oxide layer also needs to be reduced accordingly to maintain the performance of the device. However, when the thickness of the gate oxide layer is reduced to a certain extent, its mechanical stability and chemical stability will be affected, resulting in a decrease in the reliability of the device. In the Si / SiO2 structure, the tunneling effect is an unavoidable problem. As the size of the transistor decreases, the tunneling effect becomes more and more obvious, making it difficult to control the performance and power consumption of the device. Summary of the invention

[0004] In response to the problems existing in the above-mentioned related technologies, the present invention provides a thin film transistor based on a high-k gate dielectric and GeO2 structure and a preparation method thereof. By combining the high-k gate dielectric with the ultra-wide bandgap semiconductor GeO2, the thermal stability and reliability of the device can be enhanced, and the charge of the channel layer can be effectively controlled, thereby significantly improving the electrical performance.

[0005] In the first aspect, an embodiment of the present application proposes a thin film transistor based on a high-k gate dielectric and GeO2 structure, comprising a gate dielectric layer and a channel layer, wherein the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of a high-K gate dielectric, and the channel layer is made of Sn-doped GeO2.

[0006] Furthermore, the gate dielectric layer is made of HfLaO.

[0007] Furthermore, it also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

[0008] Furthermore, it also includes a source electrode and a drain electrode, and the source electrode and the drain electrode are arranged above the channel layer.

[0009] Furthermore, it also includes a substrate, which is arranged below the gate electrode layer and is made of P-type heavily doped Si.

[0010] In a second aspect, an embodiment of the present application further provides a method for preparing a thin film transistor, which is used to prepare a thin film transistor as described in any one of the above items, comprising the following steps:

[0011] A HfLaO film is deposited on the surface of the substrate by sputtering La target and Hf target simultaneously to form a high-k gate dielectric layer;

[0012] Performing annealing on the substrate surface after the HfLaO film is deposited; and

[0013] A Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer.

[0014] Furthermore, the method of simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a high-k gate dielectric layer includes:

[0015] The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.

[0016] Furthermore, the annealing treatment is performed on the substrate surface after the HfLaO film is deposited, comprising:

[0017] The substrate after the HfLaO film is deposited is placed in a high-temperature annealing furnace for annealing treatment. The annealing treatment is carried out in an O2 atmosphere at a temperature of 400°C and an annealing time of 30 minutes.

[0018] Furthermore, the method of simultaneously sputtering and depositing a Sn-doped GeO2 film on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer includes:

[0019] The channel layer is formed by simultaneously sputtering and depositing a Sn-doped GeO2 film on the surface of the HfLaO film using a Sn target and a Ge target by a magnetron sputtering method.

[0020] Further, after the Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer, the method further includes:

[0021] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0022] The thin film transistor provided in the embodiment of the present application adopts high-k material as the gate dielectric layer, which can significantly improve the gate capacitance, reduce the leakage current, and enhance the thermal stability and reliability of the device. By combining the high-k material with the channel layer of the ultra-wide bandgap semiconductor GeO2, they complement each other and passivate the oxide defects, which can more effectively control the charge of the channel layer, significantly improve the electrical performance, and significantly reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram comparing device transfer characteristic curves of thin film transistors provided in an embodiment of the present application under different gate dielectrics (SiO2 / HfLaO);

[0026] Figure 3 A schematic diagram of output characteristics of 15 devices randomly selected from an array of thin film transistors provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of a process for preparing a thin film transistor provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the AFM surface morphology of the high-k gate dielectric HfLaO before and after oxygen annealing involved in the method for preparing a thin-film transistor provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of a CV scanning curve of a high-k gate dielectric HfLaO before and after oxygen annealing in a method for preparing a thin film transistor provided in an embodiment of the present application;

[0030] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0033] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, the singular forms of "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0034] Reference Figure 1 The embodiment of the present application proposes a thin film transistor 100 based on a high-k gate dielectric and GeO2 (germanium dioxide) structure, including a gate dielectric layer 110 and a channel layer 120, wherein the gate dielectric layer 110 is arranged below the channel layer 120, the gate dielectric layer 110 is made of a high-k gate dielectric, and the channel layer 120 is made of Sn-doped GeO2.

[0035] Specifically, Figure 1As shown, the gate dielectric layer 110 is made of a high-k gate dielectric. High-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium-based oxides (such as HfO2), aluminum-based oxides (Al2O3) and zirconium-based oxides (ZrO2). The characteristics of high-k materials include higher dielectric constants, good thermal stability and wide band gaps, which make them perform well in semiconductor devices. The channel layer 120 is made of Sn-doped GeO2, and the transformation of GeO2 from an insulator to a semiconductor is successfully achieved through appropriate doping (Sn doping) and appropriate doping power. The thin film transistor 100 provided in the embodiment of the present application uses a high-k material as the gate dielectric layer 110, which can significantly improve the gate capacitance, reduce the leakage current, enhance the thermal stability and reliability of the device, and combine the high-k material with the channel layer 120 of the ultra-wide band gap semiconductor GeO2, so that they complement each other, passivate oxide defects, and more effectively control the charge of the channel layer, significantly improve the electrical performance, and significantly reduce power consumption.

[0036] Reference Figure 2 , compared with transistors with SiO2 gate dielectric, high-k gate dielectric transistors exhibit sharper transfer curves, indicating an improvement in switching speed. At the same time, the driving voltage of high-k gate dielectric transistors is also significantly reduced, which is attributed to the enhanced field effect provided by the high-k gate dielectric. The successful transition of the device from depletion mode to enhancement mode is further supported by the significant reduction in threshold voltage from -93.0V to 5.0V.

[0037] Reference Figure 3 By randomly selecting 15 test results on the prepared device array, it is shown that the thin film transistor 100 based on high-k gate dielectric / ultra-wide bandgap semiconductor GeO2 provided in the embodiment of the present application has excellent uniformity.

[0038] The above results show that the thin film transistor 100 based on high-k gate dielectric / ultra-wide bandgap semiconductor GeO2 provided in the embodiment of the present application has the advantages of good field effect and low threshold voltage, and it combines the advantages of high-k gate dielectric and new ultra-wide bandgap semiconductor GeO2.

[0039] Further, refer again to Figure 1 In some embodiments of the present application, the gate dielectric layer 110 is made of HfLaO (hafnium dioxide, hafnium lanthanum oxide).

[0040] As mentioned above, high-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium-based oxides (such as HfO2), aluminum-based oxides (Al2O3), and zirconium-based oxides (ZrO2). The properties of high-k materials include higher dielectric constants, good thermal stability, and wide band gaps, which enable them to perform well in semiconductor devices.

[0041] In addition, in some embodiments of the present application, the thickness of the gate dielectric layer 110 is preferably 90nm, and the thickness of the gate dielectric layer 100 is moderate to avoid large leakage of the device or weakening of the gate control ability. The channel layer 120 is a Sn-doped GeO2 film, and the thickness is preferably less than or equal to 28.5nm. According to the latest experimental results, the thinner the thickness, the better the characteristics, but it cannot be too thin, that is, the thickness should not exceed 28.5nm.

[0042] Furthermore, if Figure 1 As shown, in some embodiments of the present application, the thin film transistor 100 proposed in the embodiments of the present application further includes a gate electrode layer 130, and the gate electrode layer 130 is arranged below the gate dielectric layer 100, and the gate electrode layer 130 is made of P-type heavily doped Si.

[0043] Specifically, the gate electrode layer 130 controls the current between the drain and the source by changing the gate voltage. When the gate voltage is zero or negative, the channel is in a closed state, and the current between the drain and the source is almost zero. When the gate voltage increases to a certain value, the channel opens, allowing current to pass. The gate electrode layer 130 of the thin film transistor provided in the embodiment of the present application is made of P-type heavily doped Si.

[0044] Furthermore, in some embodiments of the present application, the thin film transistor 100 provided in the embodiments of the present application further includes a source electrode 140 and a drain electrode 150 , and the source electrode 140 and the drain electrode 150 are disposed above the channel layer 120 .

[0045] Specifically, the source electrode 140 is an output terminal of the current, carriers (electrons) enter from the source electrode, and the drain electrode 150 is an input terminal of the current, carriers are discharged from the drain electrode 150 . The source electrode 140 and the drain electrode 150 are disposed above the channel layer 120 .

[0046] Furthermore, if Figure 1 As shown, in some embodiments of the present application, the thin film transistor 100 provided in the embodiments of the present application further includes a substrate (not shown), which is disposed below the gate electrode layer 130 and is made of P-type heavily doped Si.

[0047] Specifically, the main function of the substrate is to connect various parts of the transistor and play a role of stability and support. The substrate of the thin film transistor 100 provided in the embodiment of the present application is arranged below the gate electrode layer 130, and the substrate is made of P-type heavily doped Si.

[0048] In a second aspect, an embodiment of the present application further provides a method for preparing a thin film transistor, which is used to prepare a thin film transistor as described in any one of the above items, comprising the following steps:

[0049] A HfLaO film is deposited on the surface of the substrate by sputtering La target and Hf target simultaneously to form a high-k gate dielectric layer;

[0050] Performing annealing on the substrate surface after the HfLaO film is deposited; and

[0051] A Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer.

[0052] The method for preparing the thin film transistor provided in the embodiment of the present application does not require complex and difficult to control processes, and can realize the device realization of a new ultra-wide bandgap semiconductor GeO2 as a channel layer combined with a high-k gate dielectric through a simple process method, and can be effectively applied to the field of power semiconductor devices, and is suitable for promotion and application.

[0053] In addition, in some embodiments of the present application, before preparing the gate dielectric layer, it is also necessary to prepare the gate electrode layer, that is, the substrate of the P-type heavily doped Si material is placed in an ultrasonic instrument and ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for at least 15 minutes respectively, and then the P-type heavily doped Si is selected as the gate electrode layer.

[0054] Furthermore, in some embodiments of the present application, the method of simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a high-k gate dielectric layer includes:

[0055] The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.

[0056] Specifically, in the above steps, the vacuum degree of the chamber for growing the HfLaO film is less than 10 -4 Pa, working pressure is 1Pa, La target sputtering power is 45W, Hf target sputtering power is 8W, the sputtering gas is Ar with a flow rate of 24sccm, the sputtering gas is N2 with a flow rate of 1sccm, the reaction gas is O2 with a flow rate of 6sccm, and the sputtering time is 6000s, thereby ensuring that the high-k gate dielectric layer can be stably generated.

[0057] Furthermore, in some embodiments of the present application, the annealing treatment is performed on the substrate surface after the HfLaO film is deposited, comprising:

[0058] The substrate after the HfLaO film is deposited is placed in a high-temperature annealing furnace for annealing treatment. The annealing treatment is carried out in an O2 atmosphere at a temperature of 400°C and an annealing time of 30 minutes.

[0059] Specifically, in the process of setting the annealing temperature and annealing time, it was found that when the annealing temperature was low, such as less than 300°C, the optimization was not obvious; when the annealing time was short, the optimization was not obvious either; and when the temperature and time were much larger than the set parameters, the film quality deteriorated. Figure 5 , Figure 5 The AFM surface morphology of the high-k gate dielectric HfLaO before and after oxygen annealing in the method for preparing the thin film transistor provided in the embodiment of the present application shows that the surface roughness of the gate dielectric film after annealing in an oxygen atmosphere is lower, and there are fewer defects, which optimizes the interface characteristics between the subsequent channel layer and the gate dielectric. The test process is to apply voltage to any one of the source and drain electrodes, and the P-type heavily doped Si gate electrode is grounded. Figure 6 , Figure 6 A schematic diagram of the CV scanning curve of the high-k gate dielectric HfLaO before and after oxygen annealing in the method for preparing a thin-film transistor provided in an embodiment of the present application. Annealing the gate dielectric layer HfLaO at 400°C for 30 minutes in an oxygen atmosphere significantly improves the mutation of the transition zone in the CV curve, which means that the interface traps are significantly reduced. In addition, the fixed oxide charge is also suppressed because the CV curve offset from zero voltage is very small. This also shows that the accumulated capacitance of the sample annealed in an oxygen atmosphere has increased significantly.

[0060] Further, in some embodiments of the present application, the Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer, comprising:

[0061] The channel layer is formed by simultaneously sputtering and depositing a Sn-doped GeO2 film on the surface of the HfLaO film using a Sn target and a Ge target by a magnetron sputtering method.

[0062] Specifically, a Sn-doped GeO2 film is deposited on the surface of the HfLaO film above the substrate by magnetron sputtering using a Sn target and a Ge target to form a channel layer. The vacuum degree of the chamber in which the film is grown during sputtering is less than 10 - 4Pa, working pressure is 1Pa, Sn target sputtering power is 8W, Ge target sputtering power is 30W, sputtering gas Ar is introduced, flow rate is 20sccm, reaction gas O2 is introduced, flow rate is 4sccm, time is 3600s, target materials are Sn target and Ge target. Among them, the sputtering power parameters of Sn target and Ge target are the optimal parameters. If the sputtering power of Sn target is low, the conductivity is very poor, and it behaves as an insulator. If the sputtering power of Sn target is too high, the conductivity is too strong, and it behaves as a conductor. There is no normal semiconductor property. If the sputtering power of Ge target is lower than 30W, it cannot be ignited normally. Increasing the sputtering power of Ge target will reduce the conductivity of the film. Therefore, the sputtering power of Ge target is fixed, and the semiconductor properties are regulated by adjusting the sputtering power of Sn target. In the process of setting the sputtering time, it is found that if the sputtering time is too short, it is difficult to form a uniform film, which affects the device characteristics. If the sputtering time is too long, the surface roughness increases, the defects increase, the field control of the device becomes weak, and the characteristics deteriorate.

[0063] Further, in some embodiments of the present application, after the Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer, the method further includes:

[0064] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0065] Specifically, an electrode pattern is formed on the channel layer by photolithography, and then a layer of Ti film is deposited by electron beam evaporation, and then a layer of Au film is deposited on the Ti film by electron beam evaporation to form source and drain electrodes; wherein the source and drain electrodes are rectangular in shape, 300 μm long and 100 μm wide; the channel length of the thin film transistor finally obtained is 10 μm.

[0066] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A thin film transistor based on a high-k gate dielectric and GeO2 structure, characterized in that: The invention comprises a gate dielectric layer and a channel layer. The gate dielectric layer is arranged below the channel layer. The gate dielectric layer is made of a high-k gate dielectric, and the channel layer is made of Sn-doped GeO2.

2. The thin film transistor according to claim 1, wherein: The gate dielectric layer is made of HfLaO.

3. The thin film transistor according to claim 2, wherein: It also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

4. The thin film transistor according to claim 2, wherein: Also included is a source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed above the channel layer.

5. The method according to claim 2, characterized in that The invention also includes a substrate, which is arranged below the gate electrode layer and is made of P-type heavily doped Si.

6. A method for preparing a thin film transistor, for preparing the thin film transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: A HfLaO film is deposited on the surface of the substrate by sputtering La target and Hf target simultaneously to form a high-k gate dielectric layer; Performing annealing on the substrate surface after the HfLaO film is deposited; and A Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer.

7. The method according to claim 6, characterized in that The method of simultaneously sputtering and depositing a HfLaO film on the surface of a substrate using a La target and a Hf target to form a high-k gate dielectric layer comprises: The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.

8. The method according to claim 6, characterized in that The annealing treatment is performed on the substrate surface after the HfLaO film is deposited, comprising: The substrate after the HfLaO film is deposited is placed in a high-temperature annealing furnace for annealing treatment. The annealing treatment is carried out in an O2 atmosphere at a temperature of 400°C and an annealing time of 30 minutes.

9. The method according to claim 6, characterized in that The method of simultaneously sputtering and depositing a Sn-doped GeO2 film on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer comprises: The channel layer is formed by simultaneously sputtering and depositing a Sn-doped GeO2 film on the surface of the HfLaO film using a Sn target and a Ge target by a magnetron sputtering method.

10. The method according to claim 6, characterized in that After the Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film by using a Sn target and a Ge target to form a channel layer, the method further includes: An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

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