Thin film transistor based on high-k gate dielectric and IGTO structure and preparation method thereof

Abstract

The thin film transistor based on the high-k gate dielectric and the IGTO structure comprises a gate dielectric layer and a channel layer, the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of the high-k gate dielectric, and the channel layer is made of In-doped IGTO. According to the thin film transistor provided by the embodiment of the invention, through the combination of the high-k gate material and the oxide semiconductor IGTO, the charge of the channel layer can be effectively controlled, the electrical performance of a device is improved, and meanwhile, the power consumption can be reduced. The embodiment of the invention also provides a preparation method of the thin film transistor.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor material technology, and in particular relates to a thin film transistor based on a high-k gate dielectric and an IGTO structure and a preparation method thereof. Background Art

[0002] As Moore's Law continues to drive the size of silicon-based transistors, this trend has led to a rapid increase in computing performance, but it has also posed unprecedented challenges to the manufacturing and design of semiconductor devices. As a key component in transistors, the continuous reduction in the thickness of the gate oxide layer has directly led to a series of problems such as increased tunneling current, increased power consumption, and reduced reliability.

[0003] The traditional Si / SiO2 structure has been unable to meet the future device's demand for low power consumption and high performance in the context of the continuous reduction in transistor size. As the size of the transistor decreases, the thickness of the gate oxide layer also needs to be reduced accordingly to maintain the performance of the device. However, when the thickness of the gate oxide layer is reduced to a certain extent, its mechanical stability and chemical stability will be affected, resulting in a decrease in the reliability of the device. In the Si / SiO2 structure, the tunneling effect is an unavoidable problem. As the size of the transistor decreases, the tunneling effect becomes more and more obvious, making it difficult to control the performance and power consumption of the device. Summary of the invention

[0004] In response to the problems existing in the above-mentioned related technologies, the present invention provides a thin film transistor based on high-k gate dielectric and IGTO structure and a preparation method thereof. By combining the high-k gate material with the oxide semiconductor IGTO, the charge of the channel layer can be effectively controlled, the electrical performance of the device can be improved, and the power consumption can be reduced.

[0005] In a first aspect, an embodiment of the present application proposes a thin film transistor based on a high-k gate dielectric and an IGTO structure, comprising a gate dielectric layer and a channel layer, wherein the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of a high-K gate dielectric, and the channel layer is made of In-doped IGTO.

[0006] Furthermore, the gate dielectric layer is made of HfLaO.

[0007] Furthermore, it also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

[0008] Furthermore, it also includes a source electrode and a drain electrode, and the source electrode and the drain electrode are arranged above the channel layer.

[0009] Furthermore, it also includes a substrate, which is arranged below the gate electrode layer and is made of P-type heavily doped Si.

[0010] In a second aspect, an embodiment of the present application further provides a method for preparing a thin film transistor, which is used to prepare a thin film transistor as described in any one of the above items, comprising the following steps:

[0011] A HfLaO film is deposited on the surface of the substrate by sputtering using a La target and a Hf target simultaneously to form a gate dielectric layer;

[0012] Performing oxygen plasma treatment on the surface of the substrate after the HfLaO film is deposited; and

[0013] An In-doped IGTO film is simultaneously sputtered and deposited on the surface of the gate dielectric layer on which the HfLaO film is deposited, using an In target and an IGTO target, to form a channel layer.

[0014] Furthermore, the method of simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a gate dielectric layer includes:

[0015] The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the gate dielectric layer.

[0016] Furthermore, before the HfLaO film is deposited on the substrate surface by sputtering using a La target and a Hf target simultaneously to form a gate dielectric layer, the method further includes:

[0017] A P-type heavily doped Si material is used as a substrate and the substrate is cleaned, and the P-type heavily doped Si is selected as a gate electrode layer.

[0018] Furthermore, the method of simultaneously sputtering and depositing an In-doped IGTO film on the surface of the gate dielectric layer on which the HfLaO film is deposited using an In target and an IGTO target to form a channel layer comprises:

[0019] The In-doped IGTO thin film is deposited on the surface of the HfLaO thin film by sputtering simultaneously using an In target and an IGTO target by magnetron sputtering to form the channel layer.

[0020] Further, after the In-doped IGTO film is simultaneously sputtered and deposited on the surface of the gate dielectric layer on which the HfLaO film is deposited by using an In target and an IGTO target to form a channel layer, the method further includes:

[0021] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0022] The thin film transistor provided in the embodiment of the present application uses high-k material as the gate dielectric layer, which can significantly improve the gate capacitance, reduce leakage current, and enhance the thermal stability and reliability of the device. By combining the high-k material with the channel layer of the oxide semiconductor IGTO, the charge of the channel layer can be effectively controlled, the electrical performance of the device can be improved, and the power consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of test results of thin film transistors selected on an array provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram showing a performance comparison between the thin film transistor provided in the embodiment of the present application and a device prepared by a similar process;

[0027] Figure 4 A schematic diagram of a process for preparing a thin film transistor provided in an embodiment of the present application.

[0028] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0031] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, the singular forms of "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0032] Reference Figure 1 The embodiment of the present application proposes a thin film transistor 100 based on a high-k gate dielectric and an IGTO (indium gallium tin oxide) structure, comprising a gate dielectric layer 110 and a channel layer 120, wherein the gate dielectric layer 110 is arranged below the channel layer 120, the gate dielectric layer 110 is made of a high-k gate dielectric, and the channel layer 120 is made of In (metal indium)-doped IGTO.

[0033] Specifically, Figure 1 As shown, the gate dielectric layer 110 is made of a high-k gate dielectric. High-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium-based oxides (such as HfO2), aluminum-based oxides (Al2O3) and zirconium-based oxides (ZrO2). The characteristics of high-k materials include higher dielectric constants, good thermal stability and wide band gap, which enable them to perform well in semiconductor devices. The channel layer 120 is made of In-doped IGTO, and the mobility of the device can be improved by In doping. The thin-film transistor 100 provided in the embodiment of the present application uses a high-k material as the gate dielectric layer 110, which can significantly improve the gate capacitance, reduce the leakage current, and enhance the thermal stability and reliability of the device. By combining the high-k material with the channel layer 120 of the oxide semiconductor IGTO, the charge of the channel layer 120 can be effectively controlled, and its electrical performance can be improved, while reducing power consumption.

[0034] Reference Figure 2 , Figure 2 Figures a, b, and c are the test results of In-doped 0W, 4W, and 8W devices respectively, which are selected on the prepared device array, showing that the thin film transistor of the high-mobility semiconductor IGTO provided in the embodiment of the present application has good uniformity. The test results show that the thin film transistor of the high-mobility semiconductor IGTO provided in the embodiment of the present application has the advantages of good field effect and low threshold voltage, and combines the advantages of high-k gate dielectric and oxide semiconductor IGTO.

[0035] Figure 3 The performance comparison between the embodiment of the present application and the device prepared by a similar process is shown, and it can be seen that the IGTO device prepared at room temperature in the embodiment of the present application has high mobility and low subthreshold swing (SS).

[0036] Further, refer again to Figure 1 In some embodiments of the present application, the gate dielectric layer 110 is made of HfLaO (lanthanum-doped hafnium-based oxide).

[0037] As mentioned above, high-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium-based oxides (such as HfO2), aluminum-based oxides (Al2O3) and zirconium-based oxides (ZrO2). The characteristics of high-k materials include higher dielectric constants, good thermal stability and wide band gaps, which enable them to perform well in semiconductor devices. The gate dielectric layer 110 of the thin film transistor 100 provided in the embodiment of the present application is preferably made of HfLaO.

[0038] In addition, in some embodiments of the present application, the gate dielectric layer 110 is preferably 90 nm thick, and the gate dielectric layer 100 is moderately thick to avoid large device leakage or weakened gate control capability. The channel layer 120 is an In-doped IGTO film, and the thickness is preferably 30 nm.

[0039] Furthermore, if Figure 1 As shown, in some embodiments of the present application, the thin film transistor 100 proposed in the embodiments of the present application further includes a gate electrode layer 130, and the gate electrode layer 130 is arranged below the gate dielectric layer 100, and the gate electrode layer 130 is made of P-type heavily doped Si.

[0040] Specifically, the gate electrode layer 130 controls the current between the drain and the source by changing the gate voltage. When the gate voltage is zero or negative, the channel is in a closed state, and the current between the drain and the source is almost zero. When the gate voltage increases to a certain value, the channel opens, allowing current to pass. The gate electrode layer 130 of the thin film transistor provided in the embodiment of the present application is made of P-type heavily doped Si.

[0041] Furthermore, in some embodiments of the present application, the thin film transistor 100 provided in the embodiments of the present application further includes a source electrode (Source) 140 and a drain electrode (Drain) 150 , and the source electrode 140 and the drain electrode 150 are disposed above the channel layer 120 .

[0042] Specifically, the source electrode 140 is an input terminal of current, carriers (electrons or holes) enter from the source electrode, and the drain electrode 150 is an output terminal of current, carriers are discharged from the drain electrode 150 . The source electrode 140 and the drain electrode 150 are arranged above the channel layer 120 .

[0043] Furthermore, if Figure 1As shown, in some embodiments of the present application, the thin film transistor 100 provided in the embodiments of the present application further includes a substrate, which is disposed below the gate electrode layer 130 and is made of P-type heavily doped Si.

[0044] Specifically, the main function of the substrate is to connect various parts of the transistor and play a role of stability and support. The substrate of the thin film transistor 100 provided in the embodiment of the present application is arranged below the gate electrode layer 130, and the substrate is made of P-type heavily doped Si.

[0045] Second, refer to Figure 4 The present application also provides a method for preparing a thin film transistor, which is used to prepare a thin film transistor as described in any one of the above items, comprising the following steps:

[0046] S101: sputtering and depositing a HfLaO thin film on the surface of the substrate using a La target and a Hf target simultaneously to form a gate dielectric layer;

[0047] S102: performing oxygen plasma treatment on the surface of the substrate after the HfLaO film is deposited; and

[0048] S103: using an In target and an IGTO target to simultaneously sputter and deposit an In-doped IGTO film on the surface of the gate dielectric layer on which the HfLaO film is deposited to form a channel layer.

[0049] The method for preparing the thin film transistor provided in the embodiment of the present application does not require complex and difficult to control processes, and can achieve the realization of a high-mobility semiconductor IGTO as a device combining a channel layer and a high-k gate dielectric through a simple process method, and can be effectively applied to the field of power semiconductor devices, and is suitable for promotion and application.

[0050] Furthermore, in some embodiments of the present application, the method of simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a gate dielectric layer includes:

[0051] The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the gate dielectric layer.

[0052] Specifically, in the above steps, the vacuum degree of the cavity for growing the thin film is less than 10-4Pa, the working pressure is 1Pa, the La target sputtering power is 45W, and the Hf target sputtering power is 8W; the sputtering gas Ar is introduced with a flow rate of 24sccm; the sputtering gas N2 is introduced with a flow rate of 1sccm; the reaction gas O2 is introduced with a flow rate of 6sccm; and the sputtering time is 6000s.

[0053] Furthermore, in some embodiments of the present application, before the HfLaO film is deposited on the substrate surface by sputtering using a La target and a Hf target simultaneously to form a gate dielectric layer, the method further includes:

[0054] A P-type heavily doped Si material is used as a substrate and the substrate is cleaned, and the P-type heavily doped Si is selected as a gate electrode layer.

[0055] Specifically, a P-type heavily doped Si material is used as a substrate and placed in an ultrasonic instrument and ultrasonically cleaned for 15 minutes using anhydrous ethanol and deionized water, respectively, and then the P-type heavily doped Si is selected as a gate electrode. In semiconductor technology, substrate cleaning is a crucial step. The purpose of cleaning is to remove contaminants on the surface of the substrate, which may include dust, grease, metal ions, organic matter, etc. These contaminants will affect the quality of subsequent process steps, such as photolithography, etching, ion implantation, etc., thereby affecting the performance and reliability of the final device.

[0056] The cleaning step usually includes multiple sub-steps, such as chemical cleaning (using acidic or alkaline solutions to remove organic matter and metal ions), physical cleaning (using ultrasonic or sandblasting to remove solid particles), deionized water rinsing (removing residual chemicals and ions), etc. The specific methods and steps of cleaning depend on the type of substrate material, the type and concentration of contaminants, and the requirements of subsequent processes.

[0057] Placing the substrate in an ultrasonicator and using anhydrous ethanol and deionized water for ultrasonic cleaning in sequence can ensure that the substrate surface is thoroughly cleaned. This step is crucial in semiconductor processing because it directly affects the quality of subsequent process steps and the performance of the final device.

[0058] After cleaning, the substrate usually needs to be dried to ensure that there is no residual moisture on the surface of the substrate. The drying method may include natural drying, hot air drying or vacuum drying, etc. The specific method depends on the type of substrate material and the requirements of the subsequent process.

[0059] Further, in some embodiments of the present application, the step of simultaneously sputtering and depositing an In-doped IGTO film on the surface of the gate dielectric layer on which the HfLaO film is deposited using an In target and an IGTO target to form a channel layer comprises:

[0060] The In-doped IGTO film is deposited on the surface of the HfLaO film by sputtering simultaneously using an In target and an IGTO target by magnetron sputtering to form the channel layer.

[0061] Specifically, a magnetron sputtering method is adopted to simultaneously sputter and deposit an In-doped IGTO film on the surface of the HfLaO film using an In target and an IGTO target to form the channel layer. During sputtering, the vacuum degree of the cavity for growing the film is less than 10-4Pa, the working pressure is 1Pa, the sputtering power of the In target is 6W, and the sputtering power of the IGTO target is 60W; the sputtering gas Ar is introduced with a flow rate of 20sccm; the reaction gas O2 is introduced with a flow rate of 1sccm; and the sputtering time is 2000s.

[0062] It should be noted that the surface of the substrate after the In-doped IGTO film is deposited is treated with argon plasma. Argon plasma treatment can cause lattice vibration and structural reorganization on the surface, reduce lattice defects and scattering centers, improve contact with subsequent electrodes, and enhance the mobility of the device. Specifically, the substrate after the In-doped IGTO film is deposited is placed in a plasma treatment machine for plasma treatment; the plasma treatment is carried out in an Ar atmosphere, the power is 50W, and the treatment time is 1min.

[0063] Furthermore, in some embodiments of the present application, after the In-doped IGTO film is simultaneously sputtered and deposited on the surface of the gate dielectric layer on which the HfLaO film is deposited by using an In target and an IGTO target to form a channel layer, the method further includes:

[0064] An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0065] Specifically, an electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation, and then an Au film is deposited on the Ti film by electron beam evaporation to form a source-drain electrode. The source-drain electrode is rectangular in shape, 300 μm long and 100 μm wide, and the channel length of the final thin-film transistor is 40 μm.

[0066] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A thin film transistor based on a high-k gate dielectric and an IGTO structure, characterized in that: The invention comprises a gate dielectric layer and a channel layer, wherein the gate dielectric layer is arranged below the channel layer, the gate dielectric layer is made of a high-K gate dielectric, and the channel layer is made of In-doped IGTO.

2. The thin film transistor according to claim 1, wherein: The gate dielectric layer is made of HfLaO.

3. The thin film transistor according to claim 2, wherein: It also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

4. The thin film transistor according to claim 2, wherein: Also included is a source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed above the channel layer.

5. The method according to claim 2, characterized in that The invention also includes a substrate, which is arranged below the gate electrode layer and is made of P-type heavily doped Si.

6. A method for preparing a thin film transistor, for preparing the thin film transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: A HfLaO film is deposited on the surface of the substrate by sputtering using a La target and a Hf target simultaneously to form a gate dielectric layer; Performing oxygen plasma treatment on the surface of the substrate after the HfLaO film is deposited; and An In-doped IGTO film is simultaneously sputtered and deposited on the surface of the gate dielectric layer on which the HfLaO film is deposited, using an In target and an IGTO target, to form a channel layer.

7. The method according to claim 6, characterized in that The method of simultaneously sputtering and depositing a HfLaO film on the surface of a substrate using a La target and a Hf target to form a gate dielectric layer comprises: The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the gate dielectric layer.

8. The method according to claim 6, characterized in that Before the HfLaO film is deposited on the surface of the substrate by sputtering La target and Hf target simultaneously to form the gate dielectric layer, the method further includes: A P-type heavily doped Si material is used as a substrate and the substrate is cleaned, and the P-type heavily doped Si is selected as a gate electrode layer.

9. The method according to claim 6, characterized in that The method of simultaneously sputtering and depositing an In-doped IGTO film on the surface of the gate dielectric layer on which the HfLaO film is deposited by using an In target and an IGTO target to form a channel layer comprises: The In-doped IGTO film is deposited on the surface of the HfLaO film by sputtering simultaneously using an In target and an IGTO target by magnetron sputtering to form the channel layer.

10. The method according to claim 6, characterized in that After the In target and the IGTO target are used to simultaneously sputter and deposit the In-doped IGTO film on the surface of the gate dielectric layer on which the HfLaO film is deposited to form a channel layer, the method further includes: An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

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