Oxide thin film transistor and preparation process thereof
By adopting the structure of the gate isolation layer, the oxide channel layer and the metal source and drain layer in the oxide thin film transistor, combined with the cover layer patterning and oxygen annealing treatment, the problem of poor bias stability of the oxide thin film transistor is solved, and high stability and large open current are achieved.
Patent Information
- Application Number
- CN202411890061.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-11
AI Technical Summary
The bias voltage stability of existing oxide thin film transistors is poor, and high stability and large open-state current cannot be achieved simultaneously.
The structure includes a gate isolation layer, an oxide channel layer, and a metal source and drain layer deposited around the oxide channel layer pattern, and the stability of the transistor is improved by overlay patterning and oxygen annealing treatment.
Through simplifying the process, batch production is achieved, which significantly improves the bias stability of the oxide thin film transistor, ensuring that the stability of the transistor is greatly improved under conditions such as threshold voltage, subthreshold swing and mobility temperature.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic technology, and in particular to an oxide thin film transistor and a preparation process thereof. Background Art
[0002] Thin-film transistor devices have attracted much attention from the industry and scientific research community in the field of three-dimensional integration due to their advantages such as low preparation temperature and large-scale integration. Among them, since optimizing the defect state of the material will simultaneously lead to a decrease in its own carrier concentration and a decrease in device stability, it is often impossible to make the oxide thin-film transistor have both high stability and a large on-state current. At present, in order to improve the stability of oxide thin-film transistors, the dielectric layer in the oxide thin-film transistor is usually processed. However, the processing of the dielectric layer is relatively cumbersome and cannot be produced on a large scale. The defect state concentration in the source and drain contact area is still large, which makes the bias stability of the oxide thin-film transistor poor. Summary of the invention
[0003] In view of this, the present application provides an oxide thin film transistor and a preparation process thereof, the main purpose of which is to solve the problem of poor bias stability of existing oxide thin film transistors.
[0004] According to one aspect of the present application, an oxide thin film transistor is provided, comprising: a gate isolation layer, an oxide channel layer deposited on the gate isolation layer, and a metal source and drain layer deposited around a pattern of the oxide channel layer, wherein the pattern is formed by oxygen annealing after patterning a covering layer.
[0005] Furthermore, the gate isolation layer is an insulator.
[0006] Furthermore, the oxide channel layer is any one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide.
[0007] Furthermore, the covering layer is metal molybdenum or metal aluminum.
[0008] Furthermore, the oxide thin film transistor also includes a substrate, a substrate isolation layer and a gate metal layer deposited on the substrate isolation layer, and the gate isolation layer is deposited on the gate metal layer.
[0009] According to another aspect of the present application, a process for preparing an oxide thin film transistor is provided, comprising:
[0010] After depositing an oxide channel layer on the gate isolation layer, depositing a capping layer on the oxide channel layer and performing a patterning process;
[0011] Performing oxygen annealing on the oxide channel layer with the cover layer, and removing the cover layer;
[0012] A metal source and drain layer is deposited around the pattern of the oxide channel layer to obtain an oxide thin film transistor.
[0013] Further, depositing a metal source and drain layer around the pattern of the oxide channel layer includes:
[0014] A metal source-drain layer is deposited on the oxide channel layer, and the metal source-drain layer is patterned, wherein the pattern of the metal source-drain layer can completely expose the pattern of the cover layer.
[0015] Furthermore, before depositing the oxide channel layer on the gate isolation layer, the preparation process includes:
[0016] A substrate isolation layer is deposited on a substrate of an oxide thin film transistor to be prepared, and a gate metal is deposited on the substrate isolation layer, so as to deposit an oxide channel layer on the gate metal layer.
[0017] Furthermore, the oxide channel layer is any one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide.
[0018] Furthermore, the gate isolation layer is an insulator, and the covering layer is metal molybdenum or metal aluminum.
[0019] By means of the above technical solution, the technical solution provided by the embodiment of the present application has at least the following advantages:
[0020] The present application provides an oxide thin film transistor and a preparation process thereof. Compared with the prior art, the oxide thin film transistor in the embodiment of the present application includes a gate isolation layer, an oxide channel layer deposited on the gate isolation layer, and a metal source and drain layer deposited around a pattern of the oxide channel layer, wherein the pattern is formed by oxygen annealing after patterning the covering layer. The preparation process is simple, and the purpose of batch production is achieved, ensuring that the bias stability of the transistor is greatly improved under the premise of threshold voltage, subthreshold swing, mobility temperature, etc.
[0021] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0023] Figure 1 A schematic diagram showing the main structure of an oxide thin film transistor provided in an embodiment of the present application is shown;
[0024] Figure 2 A process flow chart of preparing an oxide thin film transistor provided in an embodiment of the present application is shown;
[0025] Figure 3 A schematic diagram of preparing a first oxide thin film transistor provided in an embodiment of the present application is shown;
[0026] Figure 4 A schematic diagram of preparing a second oxide thin film transistor provided in an embodiment of the present application is shown;
[0027] Figure 5 A schematic diagram of preparing a third oxide thin film transistor provided in an embodiment of the present application is shown;
[0028] Figure 6 A schematic diagram of preparing a fourth oxide thin film transistor provided in an embodiment of the present application is shown;
[0029] Figure 7 A schematic diagram of preparing a fifth oxide thin film transistor provided in an embodiment of the present application is shown;
[0030] Figure 8 A schematic diagram of preparing a sixth oxide thin film transistor provided in an embodiment of the present application is shown;
[0031] Fig. 9 A schematic diagram of preparing a seventh oxide thin film transistor provided in an embodiment of the present application is shown;
[0032] Fig.10 A schematic diagram of preparing the eighth oxide thin film transistor provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0033] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0034] The present application embodiment provides an oxide thin film transistor, such as Figure 1 As shown, the method includes: a gate isolation layer 11, an oxide channel layer 12 deposited on the gate isolation layer, and a metal source and drain layer 13 deposited around the pattern of the oxide channel layer.
[0035] Among them, the gate isolation layer is an isolation layer deposited on the substrate isolation layer when the oxide thin film transistor is to be manufactured. The substrate isolation layer can be deposited on the substrate isolation layer by plasma enhanced chemical vapor deposition PECVD, plasma chemical vapor deposition LTPECVD, atomic layer deposition ALD and other processes. At this time, the gate isolation layer is an insulator, which can be molybdenum, aluminum, titanium nitride-tungsten, etc., to play the role of a gate dielectric isolating the gate and the channel layer, and the embodiment of the present application is not specifically limited. In addition, an oxide channel layer is deposited on the gate isolation layer. At this time, the oxide channel layer is at least one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide, that is, any one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide can be deposited alone, or a layer of indium gallium zinc oxide can be deposited first and then a layer of indium tin oxide can be deposited for combination, or three layers can be deposited separately, and the thickness of the oxide layer channel is less than 40 nanometers, which is not specifically limited in the embodiment of the present application.
[0036] Furthermore, in order to reduce the defect state concentration in the source-drain contact area, a covering layer is deposited on the oxide channel layer. At this time, the covering layer is patterned as needed, and the formed pattern can be a rectangle, a square, etc. with a middle hole, which can be made by dry etching technology, and the embodiment of the present application is not specifically limited. After the patterning is completed, the oxide channel layer covered with the covering layer is annealed. At this time, the annealing treatment selects oxygen annealing, the temperature is below 350 degrees, and the time is more than 30 minutes, which is not specifically limited in the embodiment of the present application. Among them, in order to ensure that the covering part of the oxide channel layer will not be oxidized to improve the bias stability of the transistor, the covering layer is metal molybdenum and metal aluminum, and the thickness of the covering layer is less than 20 nanometers, so as to achieve the purpose of isolating the annealing effect. Furthermore, the metal source and drain layer deposited around the pattern of the oxide channel layer, at this time, the covering layer after annealing can be removed by immersion, and the immersion solution can be a mixed solution of water + hydrogen peroxide + ammonia water, and the solution ratio is preferably 20:4:1, which is not specifically limited in the embodiment of the present application. Finally, a metal source and drain layer is deposited on the oxide channel layer. At this time, during deposition, the metal source and drain layer is deposited around the pattern on the oxide channel layer, thereby ensuring that the defect state concentration in the source and drain contact area is reduced while stabilizing the bias voltage. The thickness of the metal source and drain layer can be less than 40 nanometers, which is not specifically limited in the embodiment of the present application.
[0037] In another embodiment of the present application, the oxide thin film transistor further includes a substrate 14 , a substrate isolation layer 15 , and a gate metal layer 16 deposited on the substrate isolation layer 15 , and the gate isolation layer 11 is deposited on the gate metal layer 16 .
[0038] In order to facilitate the manufacture and mass production of transistors, the oxide thin film transistor also includes a substrate, a substrate isolation layer and a gate metal layer deposited on the substrate isolation layer, and the gate metal thickness is less than 60 nanometers. Among them, the gate isolation layer is deposited on the gate metal layer. The substrate isolation layer can be silicon oxide, silicon nitride, aluminum oxide, etc. The substrate can be a silicon-based substrate, a glass substrate, an organic substrate, etc., and the embodiments of the present application are not specifically limited.
[0039] An embodiment of the present application provides an oxide thin film transistor, which includes a gate isolation layer, an oxide channel layer deposited on the gate isolation layer, and a metal source and drain layer deposited around a pattern of the oxide channel layer, wherein the pattern is formed by oxygen annealing after patterning the covering layer. The preparation process is simple, and the purpose of batch production is achieved, ensuring that the bias stability of the transistor is greatly improved under the premise of threshold voltage, subthreshold swing, mobility temperature, etc.
[0040] Furthermore, as a response to the above Figure 1 The implementation of the method shown, such as Figure 2 As shown, the embodiment of the present application provides a process for preparing an oxide thin film transistor, including:
[0041] 201. After depositing an oxide channel layer on the gate isolation layer, depositing a capping layer on the oxide channel layer, and performing a patterning process;
[0042] 202. Perform oxygen annealing on the oxide channel layer with the cover layer, and remove the cover layer;
[0043] 203. Deposit a metal source and drain layer around the pattern of the oxide channel layer to obtain an oxide thin film transistor.
[0044] In the embodiment of the present application, the gate isolation layer is an isolation layer deposited on the substrate isolation layer when the oxide thin film transistor is to be manufactured. The substrate isolation layer can be deposited on the substrate isolation layer by plasma enhanced chemical vapor deposition PECVD, plasma chemical vapor deposition LTPECVD, atomic layer deposition ALD and other processes. At this time, the gate isolation layer is an insulator, which can be molybdenum, aluminum, titanium nitride-tungsten, etc., to play the role of a gate dielectric isolating the gate and the channel layer, and the embodiment of the present application is not specifically limited. An oxide channel layer is deposited on the gate isolation layer. At this time, the oxide channel layer is at least one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide, that is, any one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide can be deposited alone, or a layer of indium gallium zinc oxide can be deposited first and then a layer of indium tin oxide can be deposited for combination, or three layers can be deposited separately, and the embodiment of the present application is not specifically limited. To reduce the defect state concentration in the source-drain contact area, a covering layer is deposited on the oxide channel layer. At this time, the covering layer is patterned as needed, and the formed pattern can be a rectangle, square, etc. with a middle hole, which can be made by dry etching technology, and the embodiment of the present application does not make specific restrictions. After the patterning is completed, the oxide channel layer covered with the covering layer is annealed. At this time, the annealing treatment selects oxygen annealing, the temperature is below 350 degrees, and the time is more than 30 minutes. The embodiment of the present application does not make specific restrictions. Among them, in order to ensure that the covering part of the oxide channel layer will not be oxidized to improve the bias stability of the transistor, the covering layer is metal molybdenum and metal aluminum to achieve the purpose of isolating the annealing effect. Furthermore, the metal source and drain layer deposited around the pattern of the oxide channel layer, at this time, the covering layer after annealing can be removed by immersion. The immersion solution can be a mixed solution of water + hydrogen peroxide + ammonia water, and the solution ratio is preferably 20:4:1, which is not specifically limited in the embodiment of the present application. Finally, a metal source and drain layer is deposited on the oxide channel layer. At this time, during deposition, the metal source and drain layer is deposited around the pattern on the oxide channel layer, thereby ensuring that the defect state concentration in the source and drain contact area is reduced while stabilizing the bias voltage. The thickness of the metal source and drain layer can be less than 40 nanometers, which is not specifically limited in the embodiment of the present application.
[0045] In another embodiment of the present application, depositing a metal source and drain layer around the pattern of the oxide channel layer includes:
[0046] A metal source-drain layer is deposited on the oxide channel layer, and the metal source-drain layer is patterned.
[0047] In order to ensure the functionality of the transistor, when depositing the metal source and drain layer around the pattern of the oxide channel layer, the metal source and drain layer is first deposited on the oxide channel layer, and the metal source and drain layer is patterned, wherein the pattern of the metal source and drain layer can fully expose the pattern of the cover layer, such as Figure 2 The shaded area shown, ie, the pattern on the metal source and drain layer is complementary to the pattern of the capping layer or the oxide channel layer that has not been annealed, and is the same as the pattern of the oxide channel layer that has been annealed.
[0048] In another embodiment of the present application, before depositing an oxide channel layer on the gate isolation layer, the preparation process includes:
[0049] A substrate isolation layer is deposited on the substrate of the oxide thin film transistor to be prepared, and a gate metal is deposited on the substrate isolation layer, so as to deposit an oxide channel layer on the gate metal layer.
[0050] In order to facilitate the manufacture and mass production of transistors, the oxide thin film transistor also includes a substrate, a substrate isolation layer and a gate metal layer deposited on the substrate isolation layer, wherein the gate isolation layer is deposited on the gate metal layer. The substrate isolation layer can be silicon oxide, silicon nitride, aluminum oxide, etc. The substrate can be a silicon substrate, which is not specifically limited in the embodiments of the present application.
[0051] In a specific implementation scenario, when manufacturing an oxide thin film transistor, such as Figure 3 As shown, firstly, a substrate isolation layer is deposited on the substrate Substrate, as shown in FIG. Figure 4 As shown, a gate metal layer Gate is deposited on the substrate isolation layer, as shown in FIG. Figure 5 As shown, a gate isolation layer is deposited on the gate metal layer. Figure 6 As shown, an oxide channel layer is deposited on the gate isolation layer. Figure 7 As shown, a capping layer is deposited on the oxide channel layer and patterned, as shown in FIG. Figure 8 As shown, the patterned capping layer and the oxide channel layer are subjected to oxygen annealing treatment, as shown in FIG. Fig. 9 As shown, remove the covering layer, such as Fig.10 As shown, a metal source and drain layer is deposited and patterned.
[0052] The embodiment of the present application provides a process for preparing an oxide thin film transistor. After depositing an oxide channel layer on a gate isolation layer, the embodiment of the present application deposits a covering layer on the oxide channel layer and performs a patterning process; oxygen annealing is performed on the oxide channel layer with the covering layer, and the covering layer is removed; a metal source and drain layer is deposited around the pattern of the oxide channel layer to obtain an oxide thin film transistor. The preparation process is simple and achieves the purpose of batch production, ensuring that the bias stability of the transistor is greatly improved under the premise of threshold voltage, subthreshold swing, mobility temperature, etc.
[0053] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.
[0054] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. An oxide thin film transistor, characterized in that: include: A gate isolation layer, an oxide channel layer deposited on the gate isolation layer, and a metal source and drain layer deposited around a pattern of the oxide channel layer, wherein the pattern is formed by performing an oxygen annealing treatment after patterning the cover layer.
2. The transistor according to claim 1, characterized in that The gate isolation layer is an insulator.
3. The transistor according to claim 1, characterized in that The oxide channel layer is any one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide.
4. The transistor according to claim 1, characterized in that The covering layer is metal molybdenum or metal aluminum.
5. The transistor according to claim 1, characterized in that The oxide thin film transistor further comprises a substrate, a substrate isolation layer and a gate metal layer deposited on the substrate isolation layer, wherein the gate isolation layer is deposited on the gate metal layer.
6. A process for preparing an oxide thin film transistor, characterized in that: include: After depositing an oxide channel layer on the gate isolation layer, depositing a capping layer on the oxide channel layer and performing a patterning process; Performing oxygen annealing on the oxide channel layer with the cover layer, and removing the cover layer; A metal source and drain layer is deposited around the pattern of the oxide channel layer to obtain an oxide thin film transistor.
7. The preparation process according to claim 1, characterized in that: Depositing a metal source / drain layer around the pattern of the oxide channel layer comprises: A metal source-drain layer is deposited on the oxide channel layer, and the metal source-drain layer is patterned, wherein the pattern of the metal source-drain layer can completely expose the pattern of the cover layer.
8. The preparation process according to claim 1, characterized in that: Before depositing an oxide channel layer on the gate isolation layer, the preparation process includes: A substrate isolation layer is deposited on a substrate of an oxide thin film transistor to be prepared, and a gate metal is deposited on the substrate isolation layer, so as to deposit an oxide channel layer on the gate metal layer.
9. The preparation process according to claim 1, characterized in that: The oxide channel layer is any one of indium gallium zinc oxide, indium tin oxide, and indium tungsten oxide.
10. The preparation process according to claim 1, characterized in that: The gate isolation layer is an insulator, and the covering layer is metal molybdenum or metal aluminum.