A gallium ion implantation-based oxide thin film transistor and a method for manufacturing the same

Abstract

The application discloses a kind of oxide thin film transistor based on gallium ion implantation and preparation method thereof, belong to thin film transistor technical field.The preparation method provided by the application includes the following steps: S1, provide substrate, form a layer of transparent conductive oxide film on the substrate;S2, in the preset channel region of the transparent conductive oxide film, gallium ion is selectively implanted using focused ion beam, so that the film of the preset channel region is converted into gallium-containing oxide semiconductor, to form semiconductor channel region and source-drain electrode region on the same transparent conductive oxide film.The application selectively implants gallium ion on single transparent conductive oxide film, converts part of area in situ into semiconductor channel, while the remaining area remains as high-conductivity electrode, so as to realize single-layer integrated preparation of thin film transistor, which can effectively simplify the process and realize local precise control of channel characteristics.

Description

Technical Field

[0001] This invention relates to the field of thin-film transistor technology, and in particular to an oxide thin-film transistor based on gallium ion implantation and its fabrication method. Background Technology

[0002] The information disclosed in the background section of this invention is intended only to enhance the understanding of the overall background of the invention and is not necessarily to be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

[0003] Transparent amorphous oxide semiconductors such as indium gallium zinc oxide (IGZO) have become key materials for thin-film transistors (TFTs) in large-area integrated circuits, flexible and transparent electronic devices due to their high mobility, high uniformity, and excellent visible light transmittance. To achieve high-performance devices, electrode materials with low contact resistance are required, and metals or transparent conductive oxides are currently commonly used. However, traditional device structures and fabrication processes have inherent limitations.

[0004] At the structural level, traditional methods construct devices by separately depositing semiconductor active layers and conductive power / drain electrode layers. This heterogeneous stacking structure has inherent limitations. When using metal electrodes, the necessary subsequent annealing process can easily induce metal oxidation, potentially stripping oxygen atoms from adjacent active layers. This leads to an increase in oxygen vacancy defects in the active layers, impairing the device's electrical stability and causing threshold voltage drift. Simultaneously, a Schottky barrier easily forms at the metal-semiconductor interface, increasing contact resistance and limiting mobility. While transparent conductive oxide electrodes can avoid oxidation problems, their poor etching selectivity with the semiconductor layer typically necessitates a stripping process. During this process, organic residues such as photoresist can contaminate the semiconductor channel surface, introducing additional defects and further degrading the device's subthreshold characteristics and mobility.

[0005] Furthermore, when using traditional deposition methods, the composition and proportion of semiconductor thin films cannot be locally controlled after fabrication. Simultaneously, once the channel pattern defined by photolithography and etching is formed, it is difficult to change. This limits the ability to flexibly optimize channel size, shape, and carrier concentration distribution during the research and development process. Such capabilities are crucial for improving research and development efficiency and providing device optimization solutions through precise nanoscale control.

[0006] At the fabrication process level, existing technologies typically deposit the active layer and source / drain electrode layers separately, supplemented by corresponding patterning steps (such as photolithography and etching). This multi-step, multi-layered process flow is not only complex and lengthy, but also significantly increases the risk of introducing impurities, defects, and interface contamination during repeated deposition and patterning, which is detrimental to cost control and stable improvement of device performance. Therefore, there is an urgent need for a fabrication method for indium gallium zinc oxide thin-film transistors that can simplify the process, reduce interface problems, and enable flexible control of channel characteristics. Summary of the Invention

[0007] In view of this, the present invention provides an oxide thin film transistor based on gallium ion implantation and its fabrication method. The present invention selectively implants gallium ions into a single transparent conductive oxide thin film, transforming a portion of the region in situ into a semiconductor channel, while the remaining region remains a high-conductivity electrode, thereby realizing the monolayer integrated fabrication of the thin film transistor. This can effectively simplify the process and achieve localized and precise control of the channel characteristics.

[0008] In a first aspect, the present invention provides a method for fabricating an oxide thin-film transistor based on gallium ion implantation, comprising the following steps: S1. Provide a substrate and form a transparent conductive oxide thin film on the substrate; S2. In the preset channel region of the transparent conductive oxide film, gallium ions are selectively implanted using a focused ion beam, so that the film in the preset channel region is transformed into a gallium oxide semiconductor, thereby forming a semiconductor channel region and a source / drain electrode region on the same transparent conductive oxide film.

[0009] Preferably, the material of the transparent conductive oxide film includes indium zinc oxide or indium tin oxide.

[0010] Preferably, the thickness of the transparent conductive oxide film is 10~50nm.

[0011] Preferably, in step S1, the transparent conductive oxide film is formed using plasma-enhanced atomic layer deposition or magnetron sputtering.

[0012] Preferably, in step S2, the accelerating voltage of the focused ion beam is 1~30kV and the beam current is 1pA~1nA.

[0013] Preferably, in step S2, the doping concentration of the gallium ions after implantation is (6~7) × 10⁻⁶. 15 atom / cm 2 .

[0014] Preferably, step S2 is followed by an annealing step; the annealing temperature is 300~400℃ and the annealing time is 0.5~2h.

[0015] Preferably, after step S2, the method further includes forming a gate dielectric layer and a top gate electrode on the semiconductor channel region and the source / drain electrode region to form a top gate structure.

[0016] Preferably, before step S1, the method further includes the step of forming a bottom gate electrode and a gate dielectric layer on the substrate; in step S1, the transparent conductive oxide film is formed on the gate dielectric layer, and then step S2 is performed; after step S2, a passivation layer is deposited to form a bottom gate structure.

[0017] Secondly, the present invention provides an oxide thin-film transistor based on gallium ion implantation, which is prepared by the above-described preparation method.

[0018] Compared with the prior art, the present invention has achieved the following beneficial effects: (1) This invention utilizes the precise scanning and programmable control of a focused ion beam to flexibly adjust the channel shape and length by modifying the injection region pattern, beam current, accelerating voltage, and number of scans, thereby achieving nanoscale local control of gallium ion doping concentration and distribution. This directly solves the problem that the composition and pattern of thin films cannot be flexibly adjusted in traditional deposition processes, providing a highly flexible technical means for optimizing device performance (such as threshold voltage and carrier mobility).

[0019] (2) This invention utilizes focused ion beam selective gallium ion implantation on the same transparent conductive oxide thin film to transform the preset channel region in situ into an oxide semiconductor, while the unimplanted region retains high conductivity, thereby forming a semiconductor channel and source / drain electrodes in one step. This method directly simplifies the complex process of separately depositing and patterning the active layer and electrode layer in traditional processes, significantly reducing photolithography, etching, and stripping steps, effectively reducing interface defects in the active layer, lowering the risk of contamination introduced by complex processes and organic residues, and improving fabrication efficiency and device reliability.

[0020] (3) The thin-film transistor prepared by the present invention has its channel region and source / drain electrode region originating from the same material layer, forming a single-layer integrated structure, reducing the device thickness and avoiding the use of metal electrodes. This not only eliminates the Schottky barrier and contact resistance problems caused by the metal-semiconductor contact interface in traditional heterogeneous stacking, improving carrier transport efficiency and device mobility, but also avoids the influence of metal oxidation on stability due to the use of transparent oxide materials throughout the process, providing a foundation for realizing high-performance, high-stability fully transparent electronic devices. Attached Figure Description

[0021] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation thereof. Obviously, those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This is a schematic diagram of the top grid structure in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the bottom grid structure in a specific embodiment of the present invention; Figure 3 This is a schematic flowchart of the preparation method of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of FIB scanning before and after in Embodiment 1 of the present invention, where (a) is before scanning and (b) is after scanning; Figure 5 This is the transmission characteristic curve of the top gate device when the FIB beam current is 24pA in Embodiment 1 of the present invention; Figure 6 This is a comparison of the performance of various devices fabricated under different FIB beam currents in Example 2 of the present invention; Figure 7 This is the transmission characteristic curve of the bottom gate device when the FIB beam current is 41pA in Embodiment 2 of the present invention. Detailed Implementation

[0023] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0024] In one embodiment of the present invention, a method for fabricating an oxide thin-film transistor based on gallium ion implantation is provided, comprising the following steps: S1. Provide a substrate and form a transparent conductive oxide thin film on the substrate; S2. In the preset channel region of the transparent conductive oxide film, gallium ions are selectively implanted using a focused ion beam, so that the film in the preset channel region is transformed into a gallium oxide semiconductor, thereby forming a semiconductor channel region and a source / drain electrode region on the same transparent conductive oxide film.

[0025] The above-described preparation method of the present invention starts from a single-layer transparent conductive oxide thin film. It selectively implants gallium ions into a predetermined channel region using a focused ion beam. Utilizing the property that gallium and oxygen can form relatively stable gallium-oxygen bonds, the implanted region of the thin film is transformed from a high-conductivity conductor in situ into a semiconductor, while the unimplanted region retains its original high-conductivity characteristics. Thus, a semiconductor channel region and source / drain electrode regions are formed on the same thin film layer.

[0026] In optional embodiments of the present invention, the substrate may be a rigid or flexible substrate suitable for semiconductor device fabrication, such as, but not limited to, a silicon wafer with a thermally oxidized silicon dioxide layer on its surface, a glass substrate (such as quartz glass, borosilicate glass), or a polymer thin film substrate (such as polyimide, polyethylene terephthalate). Before use, the substrate must undergo a standard cleaning process, such as ultrasonic cleaning sequentially with Decon solution, water, isopropanol, and anhydrous ethanol, followed by drying with nitrogen gas to remove surface organic matter and particulate contamination.

[0027] In this invention, forming the transparent conductive oxide thin film is fundamental. This film, as the sole starting material layer for subsequent processing, needs to simultaneously meet two initial conditions: first, it must possess sufficiently high conductivity to function as a source / drain electrode; second, its chemical composition must be effectively transformed into a high-performance semiconductor through gallium doping. Preferred thin film materials are indium zinc oxide or indium tin oxide. These materials typically exhibit degenerate semiconductor or conductor characteristics due to high oxygen vacancies and the substitution between metal cations during doping, possessing high carrier concentration and low sheet resistance, fully meeting the requirements for a conductive electrode.

[0028] In an optional embodiment of the present invention, the thickness of the transparent conductive oxide film is 10~50 nm. During focused ion beam (FIB) implantation, ion bombardment causes certain losses to the film. Therefore, if the thickness is too thin, it may not leave enough margin for thinning the film; if the thickness is too thick, higher implantation energy is required to affect the overall channel thickness, which may increase lattice damage to the film and reduce the gate's control efficiency over the channel.

[0029] In an optional embodiment of the present invention, the transparent conductive oxide thin film is formed using plasma-enhanced atomic layer deposition (PEALD) or magnetron sputtering. PEALD technology allows for precise control of film thickness down to the atomic level, enabling the growth of high-quality, highly uniform films at lower temperatures, and allows for flexible modulation of film growth parameters. Magnetron sputtering, on the other hand, offers advantages such as high deposition rates, mature technology, and ease of large-area production.

[0030] In step S2 of this invention, the focused ion beam (FIB) system utilizes liquid gallium metal as an ion source. Under a strong electric field, gallium ions form sharp Taylor cones and gain sufficient kinetic energy to emit a high-speed gallium ion beam. By using advanced electromagnetic lenses and deflection systems to focus and scan the ion beam, it can be precisely bombarded on specific areas of the thin film. In this invention, "selective implantation" refers to controlling the scanning pattern of the FIB by setting the coordinates and direction of the scanning system, so that it only scans the region corresponding to the future TFT channel (i.e., the "preset channel region"), while avoiding regions planned as source and drain electrodes. For example, a long, narrow rectangular region can be defined as the channel using vector scanning. This patterned implantation method replaces the traditional process of patterning the semiconductor layer and source / drain electrodes through photolithography and etching.

[0031] In this invention, after gallium ions are injected into the thin film at high speed, the transformation from conductor to semiconductor is mainly achieved through two mechanisms. First, the chemical bonding effect: the injected gallium atoms occupy certain lattice sites in the thin film, replace other metal ions, or enter interstitial sites. Due to the high strength of the chemical bond between gallium (Ga) and oxygen (O), the formation of oxygen vacancies can be more effectively suppressed. Oxygen vacancies are the main source of free electrons in transparent conductive oxides, and their concentration directly leads to a decrease in the carrier concentration of the thin film. Second, the structural modification effect: the impact of high-energy ions also produces local lattice damage. These damages may recombine during subsequent annealing, further altering the microstructure and defect state density of the thin film.

[0032] In an optional embodiment of the present invention, the accelerating voltage of the focused ion beam is 1~30kV. The accelerating voltage determines the ion implantation depth and the lateral scattering range. If the voltage is too low, the ion implantation depth may be insufficient; if the voltage is too high, the ion implantation will be too deep, which may damage the underlying substrate or gate dielectric layer and produce significant lateral scattering, reducing pattern accuracy. In an optional embodiment of the present invention, the beam current of the focused ion beam is 1pA~1nA. When the beam current is too low, the mobility is low and the transfer characteristics are hysteretic; when the beam current is too high, the threshold voltage rises rapidly and the subthreshold characteristics deteriorate.

[0033] In an optional embodiment of the present invention, the gallium ion doping concentration is (6~7) ×10⁻⁶. 15 atom / cm 2 When the doping concentration is too low, the incorporated gallium is insufficient to effectively suppress oxygen vacancies, and the thin film cannot achieve a complete transition from conductor to semiconductor, resulting in insufficient decrease in conductivity. Conversely, excessively high concentrations may introduce excessive lattice damage and gallium aggregation, leading to a sharp decrease in carrier mobility. To achieve stable, controllable, and high carrier concentration semiconductor characteristics, the preferred gallium ion doping concentration is (6.4~6.8)×10⁻⁶. 15 atom / cm2 The optimal value is (6.6~6.7)×10. 15 atom / cm 2 Through systematic experiments, the corresponding curves of thin film resistivity, carrier concentration, and final TFT mobility and threshold voltage under different concentrations can be established, thereby enabling precise design of device performance.

[0034] In an optional embodiment of the present invention, annealing is preferably performed after gallium ion implantation. Annealing has three main functions: First, it repairs implantation damage: the heat energy provided by annealing helps repair lattice defects caused by high-energy ion bombardment and reduces the trap state density. Second, it activates dopant atoms: it enables implanted gallium atoms to more effectively enter suitable lattice positions and exert their chemical effect of suppressing oxygen vacancies. Third, it stabilizes the thin film structure.

[0035] In an optional embodiment of the present invention, the annealing temperature is 300~400℃, more preferably 330~370℃. At this temperature, damage repair and atomic activation can be effectively achieved, while avoiding potential thin film crystallization (amorphous IGZO performs better) or substrate (especially flexible substrate) damage that may occur due to excessively high temperatures. The annealing time is preferably 0.5~2h, more preferably 0.5~1.5h, and is carried out in an oxygen atmosphere. An oxygen atmosphere helps to further adjust the oxidation stoichiometry of the thin film.

[0036] After completing the fabrication of the channel and source / drain electrodes, this invention can continue to construct a complete thin-film transistor (TFT).

[0037] For the top-gate structure, in this invention, a gate dielectric layer (such as SiO2 or SiN deposited by PECVD) is sequentially deposited on the semiconductor channel region and source / drain electrode region formed in step S2. x The top gate electrode (e.g., deposited by sputtering a 50nm thick layer of ITO or IZO) and patterned form a thin-film transistor with a top gate structure. A schematic diagram is shown below. Figure 1 As shown.

[0038] For bottom-gate structures, before step S1, a bottom gate electrode (such as sputtered and patterned ITO, IZO, tungsten, etc.) and a gate dielectric layer (such as Al2O3 deposited by ALD, SiO2 deposited by PECVD, etc.) must first be formed on the substrate. Then, the transparent conductive oxide film from step S1 is directly deposited on this gate dielectric layer before proceeding to step S2. After step S2, a passivation layer is deposited to cover the device to protect the back channel and improve stability. A schematic diagram is shown below. Figure 2 As shown.

[0039] In another embodiment of the present invention, an oxide thin-film transistor prepared by the above-described method is provided. The semiconductor channel region and the conductive source / drain electrode regions of this thin-film transistor are physically derived from the same continuous transparent conductive oxide thin-film material. The channel region is a region modified by selective gallium ion implantation, and its composition is oxide semiconductor (such as IGZO or IGTO); while the source / drain electrode regions are regions that are not implanted or have extremely low implantation doses, retaining the high conductivity characteristics of the original transparent conductive oxide (such as IZO or ITO). This unique single-layer integrated structure eliminates the contact barrier and interface states at the semiconductor / electrode interface in traditional multilayer structures, which is beneficial for reducing contact resistance and improving carrier transport efficiency. Simultaneously, the entire channel + source / drain electrode region is composed of transparent oxide, laying the foundation for realizing high-performance fully transparent electronic devices.

[0040] The technical solution of the present invention will be further described below with reference to specific embodiments.

[0041] Example 1 This embodiment provides an IZO oxide thin-film transistor based on gallium ion implantation and its fabrication method. A schematic flowchart is shown below. Figure 3 As shown. This embodiment is a top-gate structure.

[0042] (1) Substrate cleaning: A silicon wafer with 100 nm silicon dioxide thermally grown on its surface is provided as the substrate. It is placed in Decon solution, deionized water, isopropanol and anhydrous ethanol in sequence, and ultrasonic cleaning is performed at a power of 90 W for 10 minutes to thoroughly remove organic contaminants and particles from the surface. After cleaning, it is dried with high-purity nitrogen.

[0043] (2) Defining the TCO pattern (first photolithography): Positive photoresist is spin-coated onto a clean substrate. After pre-baking, exposure (using a mask that defines the channel region), and development, the pattern of the IZO thin film (which will serve as the channel + source / drain electrodes) is transferred onto the photoresist to form a patterned mask. In this embodiment, the IZO thin film pattern is a rectangle with a width-to-length ratio (W / L) of 20 μm / 100 μm.

[0044] (3) Deposition of a transparent conductive oxide thin film: An IZO thin film was deposited on the patterned substrate formed in step (2) at room temperature using an RF magnetron sputtering system and an indium zinc oxide target. The key sputtering process parameters were optimized as follows: the working gas was argon, and its flow rate was set to 30 sccm; the working gas pressure of the sputtering chamber was controlled to 0.4 Pa; and the RF power was set to 60 W. Under these optimized conditions, an IZO thin film with uniform thickness, low surface roughness, and excellent conductivity could be deposited. In this embodiment, the deposition thickness of the IZO thin film was precisely controlled to be 30 nm.

[0045] (4) Stripping to form TCO pattern: The sample with completed film deposition is immersed in acetone solution and ultrasonically stripped to remove the photoresist defined in step (2) and the IZO film covering it. After this step, IZO conductive patterns as source and drain electrodes and pre-defined channel regions are left on the substrate. Then rinse with ethanol and blow dry.

[0046] (5) Selective implantation of gallium ions using focused ion beam: The sample obtained in step (4) is placed in a focused ion beam (FIB) system, using liquid gallium metal as the ion source. The ion beam is selectively scanned and implanted according to the preset channel region coordinates. For example... Figure 4 As shown, during the scanning process, four scanning points (ABCD) are first determined, and the scanning direction is set within this area. The FIB system heats the gallium ion source to a liquid state and forms a Taylor cone on the tungsten needle as the ion emission point. The ions are accelerated by a high-voltage electric field to gain sufficient kinetic energy, and then deflected and focused by multiple layers of electrodes and lenses. Finally, a precise scan is performed within the set area to implant the high-speed gallium ions onto the surface of the IZO thin film, forming an IGZO thin film. The key implantation parameters are: accelerating voltage 30 kV, beam current 24 pA, and gallium ion doping concentration of 6.63 × 10⁻⁶. 15 atom / cm 2 Through this step, the injected IZO suppresses oxygen vacancies due to the formation of Ga-O strong bonds, significantly reducing the carrier concentration and transforming from a conductor into an IGZO semiconductor channel; while the uninjected region retains the high conductivity of IZO and directly serves as the source and drain of the transistor.

[0047] (6) First rapid thermal annealing: The implanted sample is placed in a rapid thermal annealing furnace and annealed at 350°C in an oxygen atmosphere for 1 hour. This process is used to repair lattice damage caused by ion implantation and stabilize the semiconductor properties of the IGZO channel.

[0048] (7) Deposition of gate dielectric layer: A 100 nm thick silicon dioxide film was deposited as the gate dielectric layer on the sample surface containing IGZO channels and IZO electrodes at a temperature of 250 °C using a plasma-enhanced chemical vapor deposition system. The deposition power was 350 W.

[0049] (8) Gate dielectric layer annealing: The sample with the deposited gate dielectric layer is annealed in an oxygen atmosphere at 350°C for 1 hour to further reduce the defect density of the gate dielectric layer, optimize its insulation characteristics, and improve its interface quality with the underlying active layer.

[0050] (9) Define source and drain contact holes (second photolithography): spin-coat photoresist on the gate dielectric layer and define the contact hole pattern that needs to be opened to the IZO source and drain electrodes below through the second photolithography (exposure and development).

[0051] (10) Etching the contact holes: Using inductively coupled plasma dry etching technology, with the photoresist from step (9) as a mask, the silicon dioxide gate dielectric layer in the contact hole area is selectively etched away to expose the underlying IZO electrode surface. After etching, the residual photoresist is removed with acetone.

[0052] (11) Define the top gate electrode (third photolithography): spin-coat photoresist on the sample surface again, and form the pattern of the top gate electrode through the third photolithography.

[0053] (12) Deposition of top gate electrode: A 50 nm thick indium tin oxide film was deposited as the top gate electrode by radio frequency magnetron sputtering at a power of 60 W.

[0054] (13) Stripping to form the gate: Acetone is used to strip the photoresist and the ITO covering it to form the final top gate electrode pattern.

[0055] (14) Final post-annealing: The prepared device is post-annealed in an air atmosphere at 300°C for 1 hour to complete the preparation of the top gate device of IGZO oxide thin film transistor.

[0056] Figure 5 This is the transmission characteristic curve of the top-gate device prepared in this embodiment. It can be seen that the hysteresis of the transmission characteristic curve is very small. The measured mobility is 16.86 cm⁻¹. 2 / (V·s), the subthreshold swing is 219mV / dev, and the threshold voltage is 0.534V.

[0057] Example 2 This embodiment provides an IZO oxide thin-film transistor based on gallium ion implantation and its fabrication method. This embodiment features a bottom-gate structure.

[0058] (1) Substrate cleaning and bottom gate electrode fabrication: A silicon wafer with 100 nm of silicon dioxide thermally grown on its surface was used as a substrate. It was sequentially immersed in Decon solution, deionized water, isopropanol, and anhydrous ethanol, and ultrasonically cleaned at a power of 90 W for 10 minutes each time, followed by drying with high-purity nitrogen. Subsequently, a 50 nm thick tungsten film was deposited on the substrate as the bottom gate electrode using an RF magnetron sputtering system. The sputtering power was 50 W, and the argon working pressure was 0.4 Pa. The tungsten film was patterned into the desired bottom gate electrode pattern through a first ultraviolet lithography and subsequent wet etching (using a 15% hydrogen peroxide solution).

[0059] (2) Deposition gate medium layer: A plasma-enhanced chemical vapor deposition (PECVD) system was used to deposit a 100 nm thick silicon dioxide film as the gate dielectric layer on the patterned bottom gate electrode and the entire substrate surface at 250 °C. The deposition power was 350 W. This ensured that the dielectric layer had good insulation, high density, and perfect coverage of the bottom gate electrode.

[0060] (3) Define the IZO pattern (second photolithography): Positive photoresist is spin-coated onto a clean substrate. After pre-baking, exposure (using a mask defining the source / drain electrode and channel regions), and development, the pattern of the IZO thin film (which will serve as the channel and source / drain electrodes) is transferred onto the photoresist to form a patterned mask. In this embodiment, the IZO thin film pattern is a rectangle with a width / length ratio (W / L) of 20 μm / 100 μm.

[0061] (4) Deposition of transparent conductive oxide thin film: An IZO thin film was directly deposited on the gate dielectric layer at room temperature using an RF magnetron sputtering system. The key sputtering process parameters were optimized to match those in Example 1: argon flow rate of 30 sccm, operating pressure of 0.4 Pa, and RF power of 60 W. The deposition thickness was precisely controlled to 12 nm, forming a continuous initial conductive film.

[0062] (5) Peeling to form TCO pattern: The sample with the completed film deposition was immersed in an acetone solution and ultrasonically peeled off to remove the photoresist defined in step (2) and the IZO film covering it. After this step, an IZO conductive pattern as the source and drain and the pre-defined channel region was left on the substrate. It was then rinsed with ethanol and dried.

[0063] (6) Focused ion beam selective implantation of gallium ions (defining the channel and electrodes): The sample is placed in a focused ion beam system, and without prior photolithography, gallium ion beams are selectively implanted into specific preset channel regions based on the designed device layout coordinates. Through this step, the IZO in the implanted region suppresses oxygen vacancies due to the formation of strong Ga-O bonds, resulting in a significant reduction in carrier concentration and transforming it from a conductor into an IGZO semiconductor channel; while the unimplanted region retains the high conductivity of IZO and directly serves as the source and drain of the transistor.

[0064] (7) Annealing: The implanted sample from step (4) was placed in a rapid thermal annealing furnace and annealed at 350°C in an oxygen atmosphere for 1 hour. This process is used to repair lattice damage caused by ion implantation and stabilize the semiconductor properties of the IGZO channel.

[0065] (8) Deposited passivation layer: For the bottom-gate structure, a passivation layer needs to be deposited to protect the IGZO channel from subsequent processes and environmental influences. A plasma-enhanced chemical vapor deposition system was used to deposit a 40 nm thick silicon dioxide layer as a passivation layer on the sample surface at 250 °C, with a deposition power of 350 W.

[0066] (9) Define and etch source / drain contact holes: Photoresist was spin-coated onto the passivation layer, followed by a third photolithography step to define the contact hole patterns that needed to open to the underlying IZO source and drain electrodes. Subsequently, inductively coupled plasma dry etching was used to remove the silicon dioxide passivation layer in the contact hole region, exposing the contact surfaces of the IZO electrodes.

[0067] (10) Deposition and patterning of source and drain metal electrodes: A layer of stacked metal is deposited on the sample surface using electron beam evaporation or magnetron sputtering. In this embodiment, 50 nm tungsten is sputtered by magnetron sputtering to form source and drain metal electrodes connected to the underlying IZO electrode, thereby reducing external lead resistance. Finally, the photoresist is stripped with acetone.

[0068] (11) Final back annealing: The fabricated bottom-gate structure device was post-annealed at 350°C in an oxygen atmosphere for 1 hour to optimize the metal-IZO contact interface, stabilize device performance, and finally complete the fabrication of the IZO oxide thin film transistor bottom-gate device.

[0069] In step (6) of this embodiment, the injected parameters are: accelerating voltage 5 kV, beam current 1.3~68 pA. The final device performance is as follows: Figure 6 and Figure 7 As shown, at lower beam currents, the mobility is lower and the transfer characteristic curve exhibits greater hysteresis, indicating a high defect state density and severe damage to the device's back channel. At higher beam currents, the carrier concentration decreases rapidly, leading to a faster rise in the threshold voltage, worsening subthreshold characteristics, and a decrease in mobility. The device exhibits superior overall performance when the beam current is between 7 and 41 pA. When the beam current is 41 pA, the transfer characteristic curve shows very little hysteresis, and relatively ideal mobility, threshold voltage, and subthreshold characteristics are achieved. At this point, the gallium ion doping concentration is 6.62 × 10⁻⁶. 15 atom / cm 2 .

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating an oxide thin-film transistor based on gallium ion implantation, characterized in that, Includes the following steps: S1. Provide a substrate and form a transparent conductive oxide thin film on the substrate; S2. In the preset channel region of the transparent conductive oxide film, gallium ions are selectively implanted using a focused ion beam, so that the film in the preset channel region is transformed into a gallium oxide semiconductor, thereby forming a semiconductor channel region and a source / drain electrode region on the same transparent conductive oxide film.

2. The preparation method according to claim 1, characterized in that, The material of the transparent conductive oxide film includes indium zinc oxide or indium tin oxide.

3. The preparation method according to claim 1, characterized in that, The thickness of the transparent conductive oxide film is 10~50nm.

4. The preparation method according to claim 1, characterized in that, In step S1, the transparent conductive oxide film is formed using plasma-enhanced atomic layer deposition or magnetron sputtering.

5. The preparation method according to claim 1, characterized in that, In step S2, the accelerating voltage of the focused ion beam is 1~30kV, and the beam current is 1pA~1nA.

6. The preparation method according to claim 1, characterized in that, In step S2, the gallium ion doping concentration is (6~7) × 10⁻⁶. 15 atom / cm 2 .

7. The preparation method according to claim 1, characterized in that, Step S2 is followed by an annealing step; the annealing temperature is 300~400℃ and the annealing time is 0.5~2h.

8. The preparation method according to claim 1, characterized in that, After step S2, the method further includes forming a gate dielectric layer and a top gate electrode on the semiconductor channel region and the source / drain electrode region to form a top gate structure.

9. The preparation method according to claim 1, characterized in that, Before step S1, the method further includes forming a bottom gate electrode and a gate dielectric layer on the substrate; in step S1, the transparent conductive oxide thin film is formed on the gate dielectric layer to form a bottom gate structure.

10. An oxide thin-film transistor based on gallium ion implantation, characterized in that, It is prepared by the preparation method described in any one of claims 1 to 9.

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