Fabrication methods of stacked transistors, stacked transistors, devices and equipment

Abstract

This application provides a method for fabricating stacked transistors, stacked transistors, devices, and apparatus. The method includes: forming a semiconductor structure on a substrate, the semiconductor structure including at least a sacrificial layer, a first semiconductor structure, and a second semiconductor structure stacked sequentially; etching the semiconductor structure in source / drain regions and filling insulating material in regions corresponding to the sacrificial layer in the source / drain regions to form a placeholder structure; forming a first portion of a first transistor on the placeholder structure based on the first semiconductor structure using a front-end process, the first portion including at least a first source / drain structure; forming a second transistor based on the second semiconductor structure; flipping the second transistor to expose the placeholder structure; removing the placeholder structure to form a first source / drain contact metal for the first transistor; and forming a first metal interconnect layer of the first transistor on the first source / drain contact metal using a back-end process. This application can achieve self-aligned contacts between the top and bottom transistors.

Description

Technical Field

[0001] This application relates to the field of integrated semiconductors, and more particularly to a method for fabricating stacked transistors, transistors, devices, and equipment. Background Technology

[0002] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, by integrating two or more layers of transistors in a vertical space, further increase transistor integration density and have become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] In related technologies, the source / drain contact metals and metal interconnect layers of the top and bottom transistors of a stacked transistor are fabricated separately by wafer flipping. However, wafer flipping also introduces the problem of misalignment of the source / drain contact metals of the top and bottom transistors. Summary of the Invention

[0004] This application provides a method for fabricating stacked transistors, stacked transistors, devices, and apparatus, which can achieve self-aligned contact between the top transistor and the bottom transistor.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a stacked transistor. The method includes: forming a semiconductor structure on a substrate, the semiconductor structure including at least a sacrificial layer, a first semiconductor structure, and a second semiconductor structure stacked sequentially; etching the semiconductor structure in a source / drain region and filling an insulating material in the region corresponding to the sacrificial layer in the source / drain region to form a placeholder structure; forming a first portion of a first transistor on the placeholder structure based on the first semiconductor structure using a front-end process, the first portion including at least a first source / drain structure; forming a second transistor based on the second semiconductor structure; performing a flip-flop operation on the second transistor to expose the placeholder (PH) structure; removing the placeholder structure to form a first source / drain contact metal of the first transistor; and forming a first metal interconnect layer of the first transistor on the first source / drain contact metal using a back-end process.

[0006] In one possible implementation, removing the occupant structure to form a first source-drain contact metal for the first transistor includes: removing the occupant structure to expose the first source-drain structure; and depositing a metal material on the first source-drain structure to form the first source-drain contact metal.

[0007] In one possible implementation, exposing the occupant structure includes: removing a substrate to expose a sacrificial layer in the gate region and a occupant structure in the source / drain region; forming a first metal interconnect layer of the first transistor on the first source / drain contact metal by a back-end process, including: removing the sacrificial layer in the gate region to form a first trench; filling the first trench with a metal material to form a gate contact metal of the first transistor; forming a first metal interconnect layer on the gate contact metal and the first source / drain contact metal, wherein one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnect layer.

[0008] In one possible implementation, after forming the first source / drain contact metal, the method further includes: depositing a dielectric material on the first source / drain contact metal to form a first isolation structure, one side of the first isolation structure contacting the first source / drain contact metal in a first direction, the first direction being a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure; filling an insulating material on the gate region to form a second isolation structure, the second isolation structure contacting the other side of the first isolation structure in the first direction; and removing a sacrificial layer in the gate region to form a first groove, including: anisotropically etching a portion of the second isolation structure and the sacrificial layer to form the first groove.

[0009] In one possible implementation, before etching the first semiconductor structure in the source / drain region, the method further includes: depositing semiconductor material in the gate region to form a dummy gate structure surrounding the first semiconductor structure and the second semiconductor structure; forming a first portion of a first transistor based on the first semiconductor structure, including: epitaxially growing a first source / drain structure on the first semiconductor structure; forming a first interlayer dielectric layer on the first source / drain structure; forming a second transistor based on the second semiconductor structure, including: epitaxially growing a second source / drain structure on the second semiconductor structure; forming a second interlayer dielectric layer on the second source / drain structure; removing the dummy gate structure to expose the semiconductor structure in the gate region; forming a gate structure based on the semiconductor structure in the gate region, the gate structure including a first gate structure corresponding to the first semiconductor structure and a second gate structure corresponding to the second semiconductor structure; etching the second interlayer dielectric layer to expose the second source / drain structure; depositing metal material on the second source / drain structure to form a second source / drain contact metal for the second transistor; and forming a second metal interconnect layer for the second transistor on the second source / drain contact metal by a subsequent process.

[0010] In one possible implementation, after forming the gate structure based on the semiconductor structure within the gate region, the method further includes: forming gate cut-off structures on both sides of the gate structure, the gate cut-off structures being used to isolate the gate region of the stacked transistor from the gate region of an adjacent stacked transistor.

[0011] In a second aspect, embodiments of this application provide a stacked transistor, which is fabricated using the fabrication method described in the first aspect and any of its embodiments, comprising: a first transistor; a second transistor, wherein the first transistor and the second transistor are stacked; wherein the first source-drain contact metal of the first transistor and the second source-drain contact metal of the second transistor are self-aligned.

[0012] In one possible implementation, one side of the first source-drain contact metal is connected to the first source-drain structure of the first transistor, and the other side of the first source-drain contact metal is connected to the first metal interconnect layer of the first transistor. One side of the second source-drain contact metal is connected to the second source-drain structure of the second transistor, and the other side of the second source-drain contact metal is connected to the second metal interconnect layer of the second transistor.

[0013] In one possible implementation, the first transistor includes a gate contact metal, one side of which is connected to a first gate structure of the first transistor, and the other side of which is connected to a first metal interconnect layer of the first transistor.

[0014] Thirdly, embodiments of this application provide a semiconductor device comprising: stacked transistors as described in the second aspect above.

[0015] Fourthly, embodiments of this application provide an electronic device, which includes: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is disposed on the circuit board.

[0016] In this embodiment, a sacrificial layer, a first semiconductor structure, and a second semiconductor structure are sequentially stacked on a substrate. Then, the semiconductor structures within the source / drain regions are etched, and insulating material is filled into the regions corresponding to the sacrificial layer in the source / drain regions to form a placeholder structure. This placeholder structure is used to locate the source / drain contact metal of the bottom transistor. On the placeholder structure, a first portion of the first transistor is formed based on the first semiconductor structure using a front-end process. A second transistor is formed based on the second semiconductor structure. The placeholder structure is then flipped and exposed. The placeholder structure is removed to form the first source / drain contact metal of the first transistor. Finally, a first metal interconnect layer of the first transistor is formed on the first source / drain contact metal using a back-end process. After flipping the transistor, it is not necessary to use photolithography to select the region where the source / drain contact metal is located. The placeholder structure can be directly removed selectively using material selection. Metal material is then filled into the groove after removing the placeholder structure to form a source / drain contact metal that is self-aligned with the source / drain contact metal of the top transistor. Therefore, this embodiment can achieve self-aligned contact between the top and bottom transistors, while avoiding short-circuit failures caused by misalignment between the top and bottom transistors.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram of an implementation process of the method for fabricating stacked transistors in this application.

[0020] Figure 2 This is a top view of the stacked transistors in an embodiment of this application;

[0021] Figures 3A to 3M This is a schematic diagram of the stacked transistors during the fabrication process in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the stacked transistor structure in an embodiment of this application.

[0023] The above images:

[0024] 10. Stacked transistor; 11. First transistor (bottom transistor); 111. First nanosheet structure; 112. First source / drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 1141. First gate dielectric layer; 1142. First gate electrode layer; 115. First source / drain contact metal; 116. First metal interconnect layer; 12. Second transistor (top transistor); 121. Second nanosheet structure; 122. Second source / drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 1241. Second gate dielectric layer; 1242. Second gate electrode layer; 125. Second source / drain contact metal; 126. Second metal interconnect layer; 13. Insulating layer; 14. Carrier wafer; 20. Substrate Bottom; 21, First sacrificial layer; 22, Stacked layer; 23, Semiconductor structure; 231, First semiconductor structure; 232, Second semiconductor structure; 24, Second sacrificial layer; 25, Third isolation structure; 26, Oxide layer; 27, Pseudo-gate structure; 28, Sidewall; 29, Inner sidewall; 30, Protective layer; 31, Second trench; 32, Placement structure; 33, Source / drain isolation dielectric layer; 34, Third trench; 35, First BDI layer; 36, Gate cut-off structure; 361, SDB structure; 37, Fourth trench; 38, Fourth isolation structure; 39, Insulating structure; 40, Bottom dielectric layer; 41, Fifth trench; 42, First isolation structure; 43, Second isolation structure; 44, First trench; 45, Gate contact metal. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0027] In one embodiment, there are two fabrication methods for stacked transistors: a monolithic stacking method and a sequential stacking method. However, both methods have certain technical problems. To solve these problems, a stacked transistor method is proposed. This method involves etching to form the active regions of homogeneous transistors in the upper and lower layers, and then fabricating the stacked transistors on both sides of the wafer through wafer flipping, thus overcoming the shortcomings of the two methods mentioned above. However, wafer flipping also introduces the problem of misalignment of the source and drain contact metals between the top and bottom transistors, leading to short-circuit failures between the device electrodes.

[0028] To address the aforementioned technical problems, this application provides a method for fabricating stacked transistors, which enables self-aligned contact between the top and bottom transistors, while avoiding short-circuit failures caused by misalignment between the top and bottom transistors.

[0029] In the embodiments of this application, the stacked transistors described above can be applied to semiconductor devices such as memory and processors.

[0030] In some embodiments, the stacked transistors may include at least two transistors. For example, the first transistor and the second transistor are stacked together, and the first source-drain contact metal of the first transistor and the second source-drain contact metal of the second transistor are self-aligned in the vertical direction.

[0031] In some embodiments, the first transistor includes a gate contact metal, one side of which is connected to a first gate structure of the first transistor, and the other side of which is connected to a first metal interconnect layer of the first transistor.

[0032] In the embodiments of this application, the first transistor and the second transistor in the stacked transistors are transistors of the same type, which may include, but are not limited to: fin field effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), planar transistor, vertical field effect transistor (VFET), etc.

[0033] Figure 1 This is a schematic diagram illustrating one implementation process of the stacked transistor fabrication method in this application. Figure 1 As shown, the method for fabricating stacked transistors in this application includes the following steps.

[0034] Step S110: Form a semiconductor structure on the substrate.

[0035] In some embodiments, the semiconductor structure includes a sacrificial layer (second sacrificial layer), a first semiconductor structure, and a second semiconductor structure stacked sequentially.

[0036] In some embodiments, the implementation process of step S110 can be divided into the following three steps: providing a substrate; sequentially forming a sacrificial layer and a first material layer on the substrate; etching the sacrificial layer and the first material layer to form a semiconductor structure, wherein the etched first sacrificial layer serves as a second sacrificial layer, the etched first material layer close to the substrate serves as a first semiconductor structure, and the etched first material layer away from the substrate serves as a second semiconductor structure.

[0037] For example, the substrate can be any semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate.

[0038] After providing a substrate, semiconductor materials can be stacked on the substrate to form a first sacrificial layer and a first material layer, and certain areas of the first sacrificial layer and the first material layer can be etched to form several semiconductor structures standing upright on the substrate. The material forming the first sacrificial layer is different from the material forming the first material layer, so that the etched first sacrificial layer (second sacrificial layer) can be removed subsequently by material selectivity. The role of the second sacrificial layer will be explained later. The etching process can, for example, be at least one of dry etching, wet etching, or reactive ion etching.

[0039] Here, each semiconductor structure includes a first part (first semiconductor structure) and a second part (second semiconductor structure). The first part is closer to the substrate than the second part. That is, the etched first material layer is divided into two parts, with the lower half closer to the substrate serving as the first semiconductor structure and the upper half farther from the substrate serving as the second semiconductor structure.

[0040] In some embodiments, the first material layer may include a first semiconductor material, or the first material layer may include at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along the arrangement direction of the semiconductor structure. For example, the first semiconductor material may be silicon, and the second semiconductor material may be silicon-germanium.

[0041] Understandably, the first material layer can be a single layer formed by depositing one material, or it can be a stacked layer formed by alternating deposition of two different materials.

[0042] In one example, when the stacked transistor is a FinFET, the substrate material can be silicon, the second sacrificial layer material can be silicon-germanium, and the material forming the first material layer in the first and second semiconductor structures can be silicon. Here, the first and second semiconductor structures can also be referred to as the first and second active structures. When the stacked transistor is a GAAFET, the substrate material can be silicon, the second sacrificial layer material can be silicon-germanium, and the material forming the first material layer in the first and second semiconductor structures can be silicon-germanium and silicon alternately deposited. Subsequently, the silicon-germanium material in the first and second semiconductor structures can be removed to form the first and second active structures. The germanium content in the silicon-germanium material forming the second sacrificial layer is different from the germanium content in the silicon-germanium material forming the first and second semiconductor structures. For example, SiGe 1 can be used to prepare the second sacrificial layer, and SiGe 2 can be used to prepare the first and second semiconductor structures.

[0043] In some embodiments, after forming the semiconductor structure, an insulating material can be deposited on the substrate to form an isolation structure. For ease of distinction, this isolation structure is referred to as the third isolation structure.

[0044] Understandably, after forming the semiconductor structure, an insulating material can be deposited on the substrate, and the oxide material can be thinned so that the upper surface of the formed third isolation structure is flush with the upper surface of the second sacrificial layer to expose the first semiconductor structure.

[0045] In one example, the third isolation structure can be shallow trench isolation (STI). For example, the oxide material forming the third isolation structure can be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc. The thinning process can be a process such as chemical-mechanical planarization (CMP).

[0046] In some embodiments, after forming the semiconductor structure, semiconductor material can be deposited in the gate region to form a pseudo-gate structure surrounding the first semiconductor structure and the second semiconductor structure.

[0047] To distinguish it from the first and second semiconductor materials mentioned above, the semiconductor material here is referred to as the third semiconductor material. The third semiconductor material can be, for example, polycrystalline silicon (poly Si), amorphous silicon, or similar materials.

[0048] Understandably, after forming the semiconductor structure and the third isolation structure, the gate region can be opened by photolithography, and a third semiconductor material such as polysilicon can be deposited in the gate region as a pseudo-gate structure shared by the top and bottom transistors. That is, in this embodiment, the gate regions of the top and bottom transistors in the stacked transistors are defined by the pseudo-gate structure, thus enabling self-alignment of the upper and lower transistors in the gate region. The height of the pseudo-gate structure is greater than the height of the semiconductor structure.

[0049] In some embodiments, after the pseudo-gate structure is formed, sidewalls (spacers) can be formed on both sides of the pseudo-gate structure. For example, the sidewalls may have a single-layer structure and be made entirely of the same material, such as porous silicon carbide (SICOH).

[0050] In some embodiments, after forming the semiconductor structure, an oxide material can be deposited on the substrate to form an oxide layer that covers the semiconductor structure. After forming the oxide layer, a dummy gate can be formed on the oxide layer.

[0051] Understandably, when depositing oxides to form an oxide layer, a very thin film can be deposited on the surface of the substrate using atomic layer deposition (ALD).

[0052] Step S120: Etch the semiconductor structure of the source / drain region and fill the region corresponding to the sacrificial layer of the source / drain region with insulating material to form a placeholder structure.

[0053] Understandably, the dummy gate structure, oxide layer, first semiconductor structure, and second semiconductor structure within the source / drain region can be etched to expose the second sacrificial layer and the third isolation structures on both sides of the second sacrificial layer within the source / drain region. Then, the second sacrificial layer is etched further, and insulating material is filled into the groove formed after the second sacrificial layer is etched to form a placeholder structure. Since the location of the second sacrificial layer is the location of the source / drain contact metal of the top transistor, this embodiment uses a placeholder structure to pre-position the location of the source / drain contact metal of the bottom transistor. This avoids misalignment of the transistor's position due to wafer bending after subsequent wafer flipping, preventing misalignment of the photolithography and thus ensuring the misalignment of the source / drain contact metals of the bottom transistor with those of the top transistor. For example, the insulating material can be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc.

[0054] In some embodiments, when etching the dummy gate structure, oxide layer, first semiconductor structure, and second semiconductor structure, a portion of the bottom dummy gate structure and oxide layer may be retained as a guide oxide layer. Thus, when forming the placeholder structure, the upper surface of the placeholder structure is flush with the upper surface of the guide oxide layer.

[0055] In some embodiments, when the semiconductor structure of the stacked transistor includes Si and SiGe2 stacked sequentially, before etching the second sacrificial layer to form a placeholder structure, a portion of the SiGe2 in the first semiconductor structure and the second semiconductor structure can be laterally etched, and the etched area is filled with insulating material to form a first inner spacer on both sides of the SiGe2 in the first semiconductor structure and a second inner spacer on both sides of the SiGe2 in the second semiconductor structure.

[0056] In some embodiments, after forming the first inner sidewall and the second inner sidewall, protective layers may also be formed on both sides of the stacked layer of the top transistor to avoid affecting the top transistor when fabricating the bottom transistor.

[0057] Step S130: On the occupancy structure, a first portion of the first transistor is formed based on the first semiconductor structure through a front-end process.

[0058] Understandably, after the placeholder structure is formed, a portion of the bottom transistor (first transistor) can be formed on the placeholder structure.

[0059] In some embodiments, step S130 can be implemented as follows: epitaxially growing a first source / drain structure on a first semiconductor structure; forming a first interlayer dielectric layer on the first source / drain structure;

[0060] Understandably, after the aforementioned steps etch the first semiconductor structure in the source / drain region, a source / drain groove will be formed. Therefore, source / drain epitaxial growth can be performed at the source / drain groove to form the first source / drain structure.

[0061] For example, strained materials such as silicon germanium or silicon carbide can be selectively epitaxially grown in the source-drain trench to fill the source-drain trench of the bottom transistor (first transistor), and then the first source-drain structure can be formed on the strained material by a heavy doping process.

[0062] After forming the first source / drain structure, an interlayer dielectric can be deposited on the first source / drain structure, and the interlayer dielectric can be thinned to the upper surface of the first source / drain structure to form a first interlayer dielectric layer. The interlayer dielectric can, for example, be SiO2.

[0063] For ease of explanation, the first source / drain structure mentioned in the embodiments of this application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. Furthermore, the first source / drain contact metal, the second source / drain structure, the second source / drain contact metal, etc., are all similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0064] In some embodiments, after forming the first interlayer dielectric layer, an insulating material may be deposited on the first interlayer dielectric layer and CMP may be performed to form a source-drain isolation dielectric layer, which is used to isolate the first source-drain structure of the first transistor from the second source-drain structure of the second transistor. In this case, a top transistor (second transistor) may be formed on the first interlayer dielectric layer.

[0065] Step S140: Form a second transistor based on the second semiconductor structure.

[0066] In some embodiments, step S140 can be implemented as follows: epitaxially growing a second source / drain structure on a second semiconductor structure; forming a second interlayer dielectric layer on the second source / drain structure; removing the dummy gate structure to expose the semiconductor structure in the gate region; forming a gate structure based on the semiconductor structure in the gate region, the gate structure including a first gate structure corresponding to the first semiconductor structure and a second gate structure corresponding to the second semiconductor structure; etching the second interlayer dielectric layer to expose the second source / drain structure; depositing metal material on the second source / drain structure to form the second source / drain contact metal of the second transistor; and forming the second metal interconnect layer of the second transistor on the second source / drain contact metal through a subsequent process.

[0067] Understandably, after the second semiconductor structure in the etched region is formed, a source / drain trench is created. Therefore, source / drain epitaxial growth can be performed at this trench to form a second source / drain structure. Then, an interlayer dielectric is deposited on the second source / drain structure, and the interlayer dielectric is thinned to the upper surface of the second source / drain structure to form a second interlayer dielectric layer. Afterward, the aforementioned dummy gate structure can be removed to form the first gate structure of the first transistor and the second gate structure of the second transistor. A gate trench is obtained after the dummy gate structure, and a gate structure shared by the bottom and top transistors is formed at the gate trench. The gate structure includes a gate dielectric layer formed by depositing insulating material at the gate trench and a gate electrode layer formed by depositing metal material on the gate dielectric layer. Accordingly, the first gate structure includes a first gate dielectric layer and a first gate electrode layer, and the second gate structure includes a second gate dielectric layer and a second gate electrode layer.

[0068] For example, the gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor.

[0069] For example, the gate electrode layer may be composed of multiple layers of electrode materials, each layer of which includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0070] In the case of a GAAFET stacked transistor, the first material layer forming the first and second semiconductor structures is an alternating deposition of silicon-germanium and silicon. Therefore, when removing the dummy gate structure, the silicon-germanium material in both the first and second semiconductor structures can be removed simultaneously, forming a nanosheet structure. The nanosheet structure includes a first nanosheet structure for the bottom transistor and a second nanosheet structure for the top transistor.

[0071] Understandably, after forming the gate structure, a portion of the second interlayer dielectric layer can be etched to expose the second source / drain structure. Subsequently, metal material is deposited on the second source / drain structure to form the second source / drain contact metal. After forming the second source / drain contact metal, subsequent processes can be performed to form the second metal interconnect layer.

[0072] Understandably, the subsequent process can be, for example, inter-interconnect dielectric deposition, metal line formation, lead-out pad formation, etc. For example, the second metal interconnect layer can contain power lines and signal lines.

[0073] In some embodiments, when etching the second interlayer dielectric layer to expose the second source / drain structure, a portion of the second source / drain structure can be etched at an angle before forming the second source / drain contact metal, thereby increasing the contact area.

[0074] The above describes a scenario where the gate structures of the bottom and top transistors are formed in a single process. Alternatively, the gate structures of the bottom and top transistors can be formed separately. In this case, after removing the dummy gate structure to form a shared gate structure for both the bottom and top transistors, the gate structure can be etched back to the bottom of the top transistor. The retained gate structure serves as the first gate structure of the bottom transistor, and metal material is filled into the exposed gate region to form the second gate structure of the top transistor. In this case, the metal material in the second gate structure can be different from the metal material in the first gate structure.

[0075] In some embodiments, after forming the gate structure and before forming the second source / drain contact metal, gate cut structures can be formed on both sides of the gate structure. These gate cut structures isolate the gate region of the stacked transistor from the gate regions of adjacent stacked transistors. Accordingly, the gate cut structures include a first gate cut structure corresponding to the first gate structure and a second gate cut structure corresponding to the second gate structure.

[0076] Understandably, by cutting the gate at the edge of the gate structure, that is, at both ends along the extension direction of the gate structure, two grooves are formed, and then insulating material is filled into these two grooves to form a gate cut-off structure.

[0077] In some embodiments, after forming the gate cut-off structure and before forming the second source-drain contact metal, a single-diffusion break (SDB) structure can also be formed at the edge of the stacked transistors. The single-diffusion break structure can electrically isolate the stacked transistors from adjacent stacked transistors.

[0078] Understandably, by removing the structures located at the edges of the stacked transistors through an etching process and depositing insulating material at the removed locations, a single-diffusion barrier structure can be formed.

[0079] In some embodiments, while removing the dummy gate structure, a portion of the third isolation structure in the gate region may also be removed, then the second sacrificial layer located between the third isolation structures may be removed, and an insulating dielectric may be deposited in the groove after the removal of the second sacrificial layer to form a bottom dielectric isolation (BDI) layer.

[0080] Understandably, when depositing the insulating medium, it is deposited from the bottom up on the surface of the substrate. Therefore, there will also be a part of the insulating medium on the retained third isolation structure. This part of the insulating medium can then be removed to ensure that the BDI layer is located in the middle of the retained third isolation structure.

[0081] Step S150: Flip the second transistor and expose the placeholder structure.

[0082] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the second metal interconnect layer to form an insulating layer, and the insulating layer may be bonded to a carrier wafer, followed by a wafer flipping process to place the substrate on top.

[0083] In some embodiments, after wafer flipping, the overlying substrate can be removed to expose the sacrificial layer in the gate region and the occupant structures in the source / drain regions. It should be noted that, in the case where a BDI layer is formed as described above, the exposed area in the gate region is the BDI layer; in the case where a BDI layer is not formed as described above, the exposed area in the gate region is the second sacrificial layer.

[0084] In some embodiments, where a BDI layer is exposed in the gate region, the BDI layer can be selectively removed, and a fourth isolation structure can be formed on both sides of the occupier structure at the removed location to isolate it from the sidewalls in contact with the gate region. Insulating material can then be deposited at the remaining removed locations to form an insulating structure.

[0085] In some embodiments, where the second sacrificial layer is exposed in the gate region, the second sacrificial layer can be selectively removed, and a fourth isolation structure can be formed on both sides of the occupier structure at the removed location. Insulating material can then be deposited at the remaining removed locations to form an insulating structure.

[0086] Step S160: Remove the placeholder structure to form the first source-drain contact metal of the first transistor.

[0087] In some embodiments, step S160 can be implemented by: removing the occupant structure to expose the first source / drain structure, and depositing a metal material on the first source / drain structure to form a first source / drain contact metal.

[0088] Understandably, since the placeholder structure is used to locate the source and drain contact metal of the bottom transistor, after the transistor is flipped, there is no need to select the location of the source and drain contact metal by photolithography. The placeholder structure can be removed directly by selective material removal, and the groove after the placeholder structure is removed is filled with metal material to form a source and drain contact metal that is self-aligned with the source and drain contact metal of the top transistor.

[0089] In some embodiments, when removing the occupier structure to expose the first source / drain structure, a portion of the first source / drain structure can be etched at an angle, and then the first source / drain contact metal can be formed to increase the contact area.

[0090] In some embodiments, before removing the occupant structure, an insulating material may be deposited over the first transistor to form a bottom dielectric layer. The bottom dielectric layer is then photolithographically patterned to form the source / drain contact metal of the bottom transistor, exposing the underlying occupant structure. The occupant structure is then selectively etched to expose the first source / drain structure. Next, metal material is deposited on the first source / drain structure and CMP is performed to form the first source / drain contact metal, the upper surface of which is flush with the bottom dielectric layer. In this case, the formed first source / drain contact metal has a relatively high height.

[0091] In the presence of a bottom dielectric layer, the bottom dielectric layer is removed after the first source / drain contact metal is formed.

[0092] In some embodiments, after forming the first source-drain contact metal, a dielectric material can be deposited on the first source-drain contact metal and etched back to form a first isolation structure. One side of the first isolation structure contacts the first source-drain contact metal in a first direction, which is a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure. An insulating material is filled on the gate region to form a second isolation structure, which contacts the other side of the first isolation structure in the first direction.

[0093] Understandably, after forming the first source / drain contact metal, an isotropic dielectric material can be deposited, with the deposited dielectric material structure located above and to both sides of the first source / drain contact metal. Anisotropic etching can then be performed to remove the dielectric material above the first source / drain contact metal, forming a first isolation structure. This first isolation structure serves as a sidewall separating the gate metal of the gate region from the source / drain contact metal of the source / drain region. After forming the first isolation structure, an insulating material can be deposited in the exposed area and CMP (Chemical Motion Processing) can be performed to form a second isolation structure. The second isolation structure contacts the first isolation structure, and the height of the second isolation structure is the same as the height of the first isolation structure.

[0094] Step S170: Form the first metal interconnect layer of the first transistor on the first source-drain contact metal through a subsequent process.

[0095] In some embodiments, step S170 can be implemented by: removing the sacrificial layer in the gate region to form a first groove; filling the first groove with metal material to form the gate contact metal of the first transistor; forming a first metal interconnect layer on the gate contact metal and the first source / drain contact metal, wherein one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnect layer.

[0096] Understandably, in the case where the second sacrificial layer in the aforementioned gate region forms an insulating structure, the gate structure in the gate region is above an insulating structure and a third isolation structure. Therefore, the insulating structure can be etched, and metal material can be deposited at the etched location to form a gate contact metal. Then, a first metal interconnect layer is formed through subsequent processes. For example, the first metal interconnect layer may contain power lines and signal lines. The embodiments of this application are compatible with other signal line arrangements, such as the metal interconnect layer of the top transistor containing both signal lines and power lines, and the metal interconnect layer of the bottom transistor containing only power lines and signal lines for internal winding only. The embodiments of this application do not limit the arrangement of signal lines in the metal interconnect layers of the top and bottom transistors.

[0097] In the case where the second isolation structure is formed in the aforementioned step S160, a portion of the second isolation structure and the insulating structure can be anisotropically etched to form the first groove, and then a metal material can be deposited to form the gate contact metal.

[0098] In this embodiment, a sacrificial layer, a first semiconductor structure, and a second semiconductor structure are sequentially stacked on a substrate. Then, the semiconductor structures within the source / drain regions are etched, and insulating material is filled into the regions corresponding to the sacrificial layer in the source / drain regions to form a placeholder structure. This placeholder structure is used to locate the source / drain contact metal of the bottom transistor. On the placeholder structure, a first portion of the first transistor is formed based on the first semiconductor structure using a front-end process. A second transistor is formed based on the second semiconductor structure. The placeholder structure is then flipped and exposed. The placeholder structure is removed to form the first source / drain contact metal of the first transistor. Finally, a first metal interconnect layer of the first transistor is formed on the first source / drain contact metal using a back-end process. After flipping the transistor, it is not necessary to use photolithography to select the region where the source / drain contact metal is located. The placeholder structure can be directly removed selectively using material selection. Metal material is then filled into the groove after removing the placeholder structure to form a source / drain contact metal that is self-aligned with the source / drain contact metal of the top transistor. Therefore, this embodiment can achieve self-aligned contact between the top and bottom transistors, while avoiding short-circuit failures caused by misalignment between the top and bottom transistors. The proposed solution improves process success rate and transistor electrical performance, and facilitates further miniaturization of standard cells.

[0099] The following describes the fabrication method of the stacked transistor provided in this application, taking the active structure in the stacked transistor as a nanosheet structure as an example. Figure 2 This is a top view of the stacked transistors in an embodiment of this application. Figure 2(a) is the front view of the top-view schematic, and (b) is the back view. It should be noted that, for ease of understanding, only the nanosheet structure, gate structure, and source / drain structure are shown in the top view. Specifically, AA' is the direction along the tangent of the gate structure of the stacked transistor; BB' is the direction along the tangent of the source / drain structure of the stacked transistor; and CC' is the direction along the tangent of the nanosheet structure of the stacked transistor.

[0100] The fabrication process of the stacked transistors provided in the embodiments of this application is described below. Figures 3A to 3M This is a schematic diagram of the stacked transistor in the fabrication process according to an embodiment of this application. Figure 4 This is a schematic diagram of the stacked transistor structure according to an embodiment of this application.

[0101] Step 1: Form a first sacrificial layer 21 on the original substrate 20, and form a stacked layer 22 on the first sacrificial layer 21 (see...). Figure 3A (a) in the middle.

[0102] For example, a Si layer 20 can be provided, on which SiGe 1 material is deposited to form a first sacrificial layer 21; then, SiGe 2 material and Si material are alternately deposited on the first sacrificial layer 21 to form a stacked layer 22 of a predetermined thickness. It should be noted that the SiGe 1 material and SiGe 2 material here are only illustrative examples, and other materials can actually be used.

[0103] Step 2: Sequentially etch the stacked layer 22 and the first sacrificial layer 21 down to the substrate 20 to form the semiconductor structure 23 and the second sacrificial layer 24 (see...). Figure 3A (b) in the middle.

[0104] The second sacrificial layer 24, the first semiconductor structure 231 close to the substrate, and the second semiconductor structure 232 far from the substrate can be formed by etching.

[0105] Step 3: Deposit oxide material on substrate 20 to form third isolation structure 25, and perform CMP and etching to the upper surface of second sacrificial layer 24 (see...). Figure 3A (c) in the middle.

[0106] Step 4: Form oxide layer 26 on substrate 20 (see...) Figure 3B (a) in the middle.

[0107] Understandably, oxide layer 26 is a thin film deposited on the surface of semiconductor structure 23 and second sacrificial layer 24.

[0108] Step 5: Deposit polysilicon or other materials on oxide layer 26 to form a dummy gate structure 27 shared by the front and back sides, and form sidewalls (spacers) 28 on both sides of the dummy gate structure and the semiconductor structure (see...). Figure 3B (b) in the middle.

[0109] Understandably, by defining the gate regions of the top and bottom transistors in a stacked transistor using a pseudo-gate structure, self-alignment of the upper and lower transistors in the gate regions can be achieved.

[0110] Step 6: Etch the stacked layer (semiconductor structure) of the top and bottom transistors in the source and drain regions, and retain part of the spacer as a guiding oxide layer (see...). Figure 3B (c) in the middle.

[0111] Step 7: Laterally etch a portion of the SiGe2 material of the top and bottom transistors, fill with insulating material, and etch again to form the inner spacer 29 (see...). Figure 3C (a) in the middle.

[0112] Understandably, the inner walls include the first inner walls located on both sides of the SiGe2 of the bottom transistor and the second inner walls located on both sides of the SiGe2 of the top transistor.

[0113] Step 8; Form a protective layer 30 covering the inner wall of the top transistor (see...) Figure 3C (b) in the middle.

[0114] Step 9: Anisotropic etching removes the second sacrificial layer 24 from the source / drain region to form the second groove 31 (see...). Figure 3C (c) in the middle.

[0115] Step 10: Deposit insulating material between the first groove 31 and the retained spacer and etch back to form the placeholder structure 32 for the bottom transistor to make back contact in the source-drain region (see...). Figure 3D (a) in the middle.

[0116] Understandably, the occupant structure 32 will be selectively etched away and deposited to form the source and drain contact metal of the bottom transistor, thus achieving self-aligned contact between the top and bottom transistors.

[0117] Step 11: Epitaxial growth of the first semiconductor structure 231 on the occupant structure 32 to form the first source / drain structure 112 of the bottom transistor (see...) Figure 3D (b) in the middle.

[0118] Step 12: Remove protective layer 30 (see...) Figure 3D (c) in the middle.

[0119] Step 13: Deposit interlayer medium in the source / drain region and etch back to form the first interlayer medium layer 113 (see...) Figure 3E (a) in the middle.

[0120] Step 14: Form source / drain isolation dielectric layer 33 on the first interlayer dielectric layer 113 (see...) Figure 3E (b) in the middle.

[0121] Step 15: Epitaxially grow the second source / drain structure 122 of the top transistor on the second semiconductor structure 232 on the source / drain isolation dielectric layer 33 (see...). Figure 3E (c) in the middle.

[0122] Step 16: Deposit interlayer medium and etch back to form second interlayer medium layer 123 (see...) Figure 3F (a) in the middle.

[0123] Step 17: Remove the dummy gate structure 27 and a portion of the third isolation structure 25 in the gate region (see...). Figure 3F (b) in the middle.

[0124] Step 18: Remove the second sacrificial layer 24 in the gate region to form the third recess 34 (see...) Figure 3F (c) in the middle.

[0125] Step 19: Deposit an insulating dielectric on the third groove 24 and a portion of the retained third isolation structure 25 to form the BDI layer 35 (see...) Figure 3G (a) in the middle.

[0126] Understandably, the sum of the height of the fourth isolation structure 35 in the gate region and the height of a portion of the third isolation structure is the same as the height of the third isolation structure in the source / drain region.

[0127] Step 20: Anisotropically etch the BDI layers on both sides of the semiconductor structure 23 to ensure subsequent deposition of the gate contact metal (see...). Figure 3G (b) in the middle.

[0128] Step 21: Remove the SiGe2 material from the first semiconductor structure and the second semiconductor structure to form a first nanosheet structure 111 and a second nanosheet structure 121, and form a first gate structure 114 based on the first nanosheet structure 111, and a second gate structure 124 based on the second nanosheet structure 121 (see...). Figure 3G (c) in the middle.

[0129] Understandably, an insulating material can be deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141. A metal material can then be deposited on the first gate dielectric layer 1141 within the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute the first gate structure 114. Similarly, an insulating material can be deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241. A metal material can then be deposited on the second gate dielectric layer 1241 within the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute the second gate structure 124. Therefore, in this embodiment, the gate structure of the bottom transistor and the gate structure of the top transistor are formed in a single step.

[0130] Step 22: Form gate cut-off structures 36 on both sides of the gate structure (see...) Figure 3H (a) in the middle.

[0131] It is understandable that the gate cut-off structure includes the first gate cut-off structure corresponding to the first gate structure and the second gate cut-off structure corresponding to the second gate structure.

[0132] Step 23: Forming the SDB structure 361 (see...) Figure 3H (b) in the middle.

[0133] Step 24: Form the second source / drain contact metal 125 of the top transistor (see...) Figure 3H (c) in the middle.

[0134] Step 25: Form the second metal interconnect layer 126 (see...) Figure 3I (a) in the middle.

[0135] Understandably, the second metal interconnect layer contains both signal lines and power lines.

[0136] Step 26: Deposit insulating material on the second metal interconnect layer 126 to form an insulating layer 13. After bonding the carrier wafer 14 to the insulating layer 13, flip the second transistor 12 and remove the substrate 20 (see...). Figure 3I (b) in the middle.

[0137] Step 27: Selectively remove the bottom BDI layer 35 to form the fourth groove 37 and expose a portion of the placeholder structure 32 (see...). Figure 3I (c) in the middle.

[0138] Step 28: On the gate cut-off structure 36, a fourth isolation structure 38 is formed on both sides of the exposed occupant structure to isolate it from the sidewalls in contact with the gate region (see...). Figure 3J (a) in the middle.

[0139] Step 29: Deposit insulating material in the fourth groove 37 to form insulating structure 39 (see...) Figure 3J (b) in the middle.

[0140] Step 30: Form the bottom dielectric layer 40 (see...) Figure 3J (c) in the middle.

[0141] Step 31: Photolithography is used to form the pattern of the bottom transistor source and drain contact metal to obtain the fifth groove 41 (see...). Figure 3K (a) in the middle.

[0142] Step 32: Selective etching of the site structure 32 (see...) Figure 3K (b) in the middle.

[0143] Step 33: Fill the fifth groove 41 and the groove formed after etching the placeholder structure with metal material to form the first source / drain contact metal 115 (see...). Figure 3K (c) in the middle.

[0144] Step 34: Remove the bottom dielectric layer 40 (see...) Figure 3L (a) in the middle.

[0145] Step 35: An isotropic isolation medium is deposited above and on both sides of the first source-drain contact metal 115 to form the first isolation structure 42 (see...). Figure 3L (b) in the middle.

[0146] Step 36: Anisotropic etching to remove the first isolation structure on the first source / drain contact metal 115 (see...) Figure 3L (c) in the middle.

[0147] Understandably, the first isolation structure located on both sides of the first source / drain contact metal serves as a sidewall isolation between the gate metal and the source / drain metal.

[0148] Step 37: Deposit insulating material and CMP form second isolation structure 43 (see...) Figure 3M (a) in the middle.

[0149] Step 38: Photolithography forms the bottom interconnect groove of the gate (first groove 44) (see...) Figure 3M (b) in the middle.

[0150] Understandably, a portion of the second isolation structure and the insulating structure 39 can be anisotropically etched to form the first groove.

[0151] Step 39: Deposit metal material in the first groove 44 and perform CMP to form the gate contact metal 45 (see...) Figure 3M (c) in the middle.

[0152] Step 40: Form the first metal interconnect layer 116 (see...) Figure 4 ).

[0153] Understandably, the first metal interconnect layer contains both signal lines and power lines.

[0154] In the embodiments of this application, the first gate structure and the second gate structure in the stacked transistor can be formed in one step or separately. Correspondingly, the first gate cut-off structure and the second gate cut-off structure can be formed in one step or separately. The above embodiments employ the BDI process, specifically as shown in steps seventeen to nineteen. Alternatively, the BDI process can be omitted, and the second sacrificial layer can be selectively removed directly after wafer flipping. Moreover, in the embodiments of this application, after removing the placeholder structure in step thirty-two, a portion of the first source / drain structure can be etched at an angle to increase the contact area. The second source / drain structure can also be operated accordingly. In addition, in the above embodiments, both the metal interconnect layer of the bottom transistor and the metal interconnect layer of the top transistor have signal lines and power lines. In some embodiments, they can also be compatible with other signal line arrangements, such as the metal interconnect layer of the bottom transistor having both signal lines and power lines, and the metal interconnect layer of the top transistor having only power lines and signal lines for internal winding only. The embodiments of this application do not limit the arrangement of signal lines in the metal interconnect layers of the top and bottom transistors.

[0155] Furthermore, the stacked transistors provided in this application embodiment can be inspected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this application embodiment can use TEM slicing to inspect the structure of the stacked transistors. The back side of the stacked transistors forms contact metals at the gate region and source / drain region of the bottom transistor simultaneously through self-alignment, eliminating misalignment issues between the source / drain and gate of the top transistor and the bottom transistor.

[0156] This application provides a semiconductor device, including: a stacked transistor as described in the above embodiments.

[0157] This application provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board and the semiconductor device includes the stacked transistors described above.

[0158] In the description of the embodiments in this application, the terms "an embodiment," "an example," "a specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0159] The above description is merely a preferred embodiment of this application and is not intended to limit the application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating stacked transistors, characterized in that, The method includes: A semiconductor structure is formed on a substrate, the semiconductor structure comprising a sacrificial layer, a first semiconductor structure, and a second semiconductor structure stacked sequentially; The semiconductor structure of the source and drain regions is etched, and insulating material is filled in the region corresponding to the sacrificial layer of the source and drain regions to form a placeholder structure; On the occupancy structure, a first portion of a first transistor is formed based on the first semiconductor structure through a front-end process, the first portion including at least a first source-drain structure; A second transistor is formed based on the second semiconductor structure; The second transistor is flipped and the substrate is removed to expose the sacrificial layer in the gate region and the placeholder structure in the source and drain regions; Remove the occupying structure to form the first source-drain contact metal of the first transistor; Remove the sacrificial layer in the gate region to form a first groove; The first groove is filled with metal material to form the gate contact metal of the first transistor; A first metal interconnect layer of the first transistor is formed on the gate contact metal and the first source / drain contact metal, wherein one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnect layer.

2. The method according to claim 1, characterized in that, The removal of the occupier structure to form the first source-drain contact metal of the first transistor includes: Remove the placeholder structure to expose the first source / drain structure; Metallic material is deposited on the first source / drain structure to form the first source / drain contact metal.

3. The method according to claim 1, characterized in that, After forming the first source-drain contact metal, the method further includes: A dielectric material is deposited on the first source-drain contact metal and etched back to form a first isolation structure. One side of the first isolation structure is in contact with the first source-drain contact metal in a first direction, which is perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure. An insulating material is filled on the gate region to form a second isolation structure, the second isolation structure being in contact with the other side of the first isolation structure in the first direction; The removal of the sacrificial layer in the gate region to form the first groove includes: A portion of the second isolation structure and the sacrificial layer are anisotropically etched to form the first groove.

4. The method according to claim 3, characterized in that, Before etching the first semiconductor structure within the source / drain region, the method further includes: Semiconductor material is deposited in the gate region to form a pseudo-gate structure surrounding the first semiconductor structure and the second semiconductor structure; The first portion of forming the first transistor based on the first semiconductor structure includes: A first source / drain structure is epitaxially grown on the first semiconductor structure; A first interlayer dielectric layer is formed on the first source-drain structure; The process of forming a second transistor based on the second semiconductor structure includes: A second source / drain structure is epitaxially grown on the second semiconductor structure; A second interlayer dielectric layer is formed on the second source / drain structure; Remove the dummy gate structure to expose the semiconductor structure within the gate region; A gate structure is formed based on the semiconductor structure within the gate region, the gate structure including a first gate structure corresponding to the first semiconductor structure and a second gate structure corresponding to the second semiconductor structure; The second interlayer dielectric layer is etched to expose the second source / drain structure; Metal material is deposited on the second source-drain structure to form the second source-drain contact metal of the second transistor; A second metal interconnect layer of the second transistor is formed on the second source / drain contact metal using a back-end process.

5. The method according to claim 4, characterized in that, After forming the gate structure based on the semiconductor structure within the gate region, the method further includes: Gate cut-off structures are formed on both sides of the gate structure, and the gate cut-off structures are used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor.

6. A stacked transistor, fabricated using the fabrication method according to any one of claims 1 to 5, characterized in that, include: First transistor; The second transistor is stacked with the first transistor. The first source-drain contact metal of the first transistor is self-aligned with the second source-drain contact metal of the second transistor.

7. The stacked transistor according to claim 6, characterized in that, The first transistor includes a gate contact metal, one side of which is connected to a first gate structure of the first transistor, and the other side of which is connected to a first metal interconnect layer of the first transistor.

8. A semiconductor device, characterized in that, include: The stacked transistor as described in claim 6 or 7.

9. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 8, wherein the semiconductor device is disposed on the circuit board.

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