Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor device. By etching a part of the second interlayer dielectric layer and a part of the first interlayer dielectric layer, a first type of trench is formed on the side of the gate structure, and at the same time, a part of the first interlayer dielectric layer is etched to form a second type of trench above the gate structure; the second interlayer dielectric layer is etched to form a convex structure, a first wiring trench, and a second wiring trench, wherein one side of the convex structure is the first wiring trench and the other side of the convex structure is the second wiring trench; the first interlayer dielectric layer and the second interlayer dielectric layer are etched to deepen the first type of trench and the second type of trench until the first type of trench is connected to the metal silicide of the semiconductor structure and the second type of trench is connected to the gate oxide layer of the gate structure; a part of the second type of trench is filled to form a metal gate, and at the same time, the first type of trench and a part of the second type of trench are filled to form a contact plug; and the first wiring trench and the second wiring trench are filled to form a metal layer.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and particularly relates to a manufacturing method of a semiconductor device and a semiconductor device. Background Art

[0002] In the manufacturing of complementary metal oxide semiconductor (CMOS), the forming quality of the gate and contact holes is an important factor affecting the device yield and reliability. In the manufacturing processes of the gate and contact holes, etching and polishing result in depressions on the surface of the contact etch stop layer, and the surface of the dielectric layer is uneven. Moreover, in the manufacturing processes of the gate and contact holes, after gate polishing, there may be metal residues, thereby increasing the possibility of contact hole open circuit and gate short circuit. And, in the manufacturing processes of the gate and contact holes, due to the possible bulging of the patterned load metal gate surface, the turn-on voltage of the metal gate increases. Therefore, the forming yield of the manufacturing processes of the gate and contact holes is low, resulting in low device reliability. Summary of the Invention

[0003] The purpose of the present invention is to provide a manufacturing method of a semiconductor device and a semiconductor device, which can improve the forming yield of CMOS semiconductor devices and enhance device reliability.

[0004] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0005] The present invention provides a manufacturing method of a semiconductor device, including the following steps:

[0006] Provide a semiconductor structure, the semiconductor structure includes a substrate and a gate structure, and the gate structure is disposed on the substrate;

[0007] Form a first interlayer dielectric layer on the semiconductor structure, and form a second interlayer dielectric layer on the first interlayer dielectric layer;

[0008] Etch part of the second interlayer dielectric layer and part of the first interlayer dielectric layer to form a first type of trench on the side of the gate structure, and at the same time etch part of the first interlayer dielectric layer to form a second type of trench above the gate structure;

[0009] Etch the second interlayer dielectric layer to form a convex structure, a first wiring trench, and a second wiring trench, wherein one side of the convex structure is the first wiring trench, and the other side of the convex structure is the second wiring trench;

[0010] Etch the first interlayer dielectric layer and the second interlayer dielectric layer to deepen the first type of trenches and the second type of trenches until the first type of trenches are connected to the metal silicide of the semiconductor structure and the second type of trenches are connected to the gate oxide layer of the gate structure;

[0011] Fill a part of the second type of trenches to form a metal gate, and at the same time form to fill the first type of trenches and a part of the second type of trenches to form contact plugs; and

[0012] Fill the first wiring trench and the second wiring trench to form a metal layer.

[0013] In an embodiment of the present invention, the step of forming the first interlayer dielectric layer includes:

[0014] Form a protective layer on the semiconductor structure,

[0015] Form a first interlayer dielectric layer on the protective layer; and

[0016] Grind the first interlayer dielectric layer until the first interlayer dielectric layer is flush with the nitride layer of the gate structure, wherein the nitride layer covers the polysilicon layer of the gate structure.

[0017] In an embodiment of the present invention, after forming the second interlayer dielectric layer, form a stacked structure on the second interlayer dielectric layer, wherein the stacked structure includes a protective layer, an antireflection layer, and a first photoresist layer.

[0018] In an embodiment of the present invention, in the step of etching to form the first type of trenches and the second type of trenches, the orthographic projection of the etching window of the first type of trenches on the substrate overlaps with the functional area of the semiconductor structure, and the orthographic projection of the etching window of the second type of trenches on the substrate overlaps with the polysilicon layer of the gate structure.

[0019] In an embodiment of the present invention, the etching window width of the second type of trenches is greater than the etching layer window width of the first type of trenches.

[0020] In an embodiment of the present invention, the step of forming the first wiring trench and the second wiring trench includes:

[0021] Etch the second interlayer dielectric layer located between adjacent first type of trenches to form the first wiring trench; and

[0022] Simultaneously etch a part of the second interlayer dielectric layer located between the first type of trenches and the second type of trenches to form the second wiring trench, and form a convex structure between the first type of trenches and the second type of trenches.

[0023] In an embodiment of the present invention, in the step of forming the first type of trench and the second type of trench, the bottom of the first type of trench is formed in the middle of the first interlayer dielectric layer, and the bottom of the second type of trench is formed in the middle of the second interlayer dielectric layer.

[0024] In an embodiment of the present invention, after forming the first type of trench and the second type of trench, a photoresist pattern is formed in the first type of trench and the second type of trench, and on the second interlayer dielectric layer between the first type of trench and the second type of trench.

[0025] In an embodiment of the present invention, in the step of forming the metal layer, after filling the first wiring trench and the second wiring trench, the metal layer is polished until the surface of the metal layer is flush with the surface of the convex structure.

[0026] The present invention provides a semiconductor device, comprising:

[0027] A semiconductor structure, the semiconductor structure includes a substrate and a gate structure, and the gate structure is disposed on the substrate;

[0028] A first interlayer dielectric layer, disposed on the semiconductor structure;

[0029] A second interlayer dielectric layer, disposed on the first interlayer dielectric layer, wherein the second interlayer dielectric layer includes a convex structure, one side of the convex structure is a first wiring trench, and the other side of the convex structure is a second wiring trench;

[0030] A plurality of first type of trenches, passing through the first interlayer dielectric layer and the second interlayer dielectric layer, and connecting to the metal silicide of the semiconductor structure, and the first type of trenches communicate with the first wiring trench;

[0031] A second type of trench, passing through the first interlayer dielectric layer, and connecting to the gate oxide layer of the gate structure, and the second type of trench communicates with the second wiring trench;

[0032] A metal gate, filled in the second type of trench and covering the gate oxide layer;

[0033] Contact plugs, filled in the first type of trench and the second type of trench, and connected to the metal gate or the metal silicide; and

[0034] A metal layer, filled in the first wiring trench and the second wiring trench, and connected to the contact plugs.

[0035] As described above, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, and its unexpected technical effects are as follows: in the forming processes of the gate and the contact hole, not only metal residues are avoided, but also non-preset depressions caused by over-etching can be avoided. Therefore, the forming yield of the metal gate is high, and defects brought by the polishing process and the loading effect to the gate forming and the contact hole forming can also be reduced, thereby improving the yield of the forming processes of the gate and the contact hole, and thus improving the reliability of the semiconductor device. Moreover, the method for manufacturing a semiconductor device and the semiconductor device provided by the present invention have a low complexity of the manufacturing process and a high manufacturing efficiency.

[0036] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-mentioned advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 Schematic diagram of a semiconductor structure in an embodiment of the present invention.

[0039] Figure 2 Schematic diagram of a structure for forming an etch stop layer in an embodiment of the present invention.

[0040] Figure 3 Schematic diagram of a structure for depositing and forming a first interlayer dielectric layer in an embodiment of the present invention.

[0041] Figure 4 Schematic diagram of a structure after grinding and processing the first interlayer dielectric layer in an embodiment of the present invention.

[0042] Figure 5 Schematic diagram of a structure for forming a stacked structure in an embodiment of the present invention.

[0043] Figure 6 Schematic diagram of a structure for forming a photolithography trench in an embodiment of the present invention.

[0044] Figure 7 Schematic diagram of a structure for forming a first type of trench and a second type of trench in an embodiment of the present invention.

[0045] Figure 8 Schematic diagram of a structure for forming a second photoresist layer in an embodiment of the present invention.

[0046] Figure 9 Schematic diagram of a structure for forming a second photoresist pattern in an embodiment of the present invention.

[0047] Figure 10 It is a schematic structural diagram of forming a convex structure in an embodiment of the present invention.

[0048] Figure 11 It is a schematic structural diagram of a device after removing the second photoresist pattern in an embodiment of the present invention.

[0049] Figure 12 It is a schematic structural diagram of the first type of trench and the second type of trench after deepening in an embodiment of the present invention.

[0050] Figure 13 It is a schematic structural diagram of the second type of trench after deepening in an embodiment of the present invention.

[0051] Figure 14 It is a schematic structural diagram of a metal layer, a metal gate, and a contact plug in an embodiment of the present invention.

[0052] Figure 15 It is a schematic structural diagram of a metal layer, a metal gate, and a contact plug after grinding treatment in an embodiment of the present invention.

[0053] In the figure: 100, semiconductor structure; 110, substrate; 111, deep well region; 112, first well region; 113, second well region; 114, first doping region; 115, second doping region; 116, metal silicide; 120, gate structure; 121, gate oxide layer; 122, polysilicon layer; 123, sidewall structure; 1231, nitride layer; 200, protective layer; 300, first interlayer dielectric layer; 400, second interlayer dielectric layer; 410, protective layer; 420, first anti-reflection layer; 430, second anti-reflection layer; 440, convex structure; 500, first photoresist layer; 510, lithography trench; 520, first type of trench; 530, second type of trench; 600, second photoresist layer; 610, second photoresist pattern; 620, first wiring trench; 630, second wiring trench; 700, metal layer; 710, contact plug. Detailed implementation manners

[0054] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0055] The semiconductor device provided by the present invention includes a metal gate. And the semiconductor device provided by the present invention can be one or several of semiconductor devices such as a Field Effect Transistor (FET), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Complementary Metal Oxide Semiconductor (CMOS), an Insulated Gate Bipolar Transistor (IGBT), a Fast Recovery Diode (FRD), a High Efficiency Diode (HED), a zener diode, a high-frequency diode, a Light-Emitting Diode (LED), a Gate Turn off Thyristor (GTO), a Light Triggered Thyristor (LTT), a thyristor, a Charge Coupled Device (CCD image sensor), a Digital Signal Processor (DSP), a Photo Relay, or a Micro Processor. In this embodiment, the semiconductor device is a CMOS semiconductor device.

[0056] Please refer to Figure 1As shown, in the method for manufacturing a semiconductor device provided by the present invention, first, a semiconductor structure 100 is provided. The semiconductor structure 100 includes a substrate 110. Among them, the substrate 110 is, for example, a silicon substrate forming the semiconductor structure 100. The substrate 110 may include a substrate and a silicon layer disposed above the substrate. The substrate is, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc. Phosphorus ions or arsenic ions can be implanted into the silicon layer of the substrate 110 to form a deep well region 111 and a plurality of well regions and doped regions. Among them, the plurality of well regions, such as a first well region 112 and a second well region 113, are both located above the deep well region 111. In this embodiment, the doped ions in the first well region 112 and the second well region 113 are different. Specifically, the first well region 112 may be a P well, and the second well region 113 may be an N well. Continuing to inject various ions into the well regions to form the source region and the drain region of the semiconductor structure 100. And ions can be injected into the well regions, and the concentration of the injected ions can be adjusted to form a heavily doped region or a lightly doped region, etc. The present invention does not make specific limitations in this regard. In this embodiment, for example, a first doped region 114 is formed in the first well region 112. A second doped region 115 is formed in the second well region 113. It should be noted that the present invention does not limit the type and structure of the doped regions. For example, the first doped region 114 is a doped structure with a rectangular cross-section, and the second doped region 115 is a sigma doping. Then, a metal silicide 116 is formed on the tops of the first doped region 114 and the second doped region 115 through a metal silicide process.

[0057] Please refer to Figure 1 As shown, in an embodiment of the present invention, the semiconductor structure 100 includes a gate structure 120. The gate structure 120 is disposed on the substrate 110, and the gate structure 120 is disposed between the source region and the drain region of the semiconductor structure 100. Among them, the gate structure 120 includes a gate oxide layer 121, a polysilicon layer 122, and a sidewall structure 123. In this embodiment, the gate oxide layer 121 is disposed on the substrate 110. It should be noted that the multi-layer structure of the gate oxide layer 121 is not shown in the drawings. In this embodiment, the gate oxide layer 121 may be a stacked structure of an oxide and a high-K dielectric layer. For example, the gate oxide layer 121 includes a hafnium dioxide layer and a titanium nitride layer. Among them, the polysilicon layer 122 is disposed on the gate oxide layer 121. The sidewall structure 123 covers the outside of the polysilicon layer 122 and the gate oxide layer 121. In this embodiment, the sidewall structure 123 includes at least one silicon nitride layer and at least one silicon oxide layer. Among them, the silicon nitride layer covers the outside of the polysilicon layer 122 and the gate oxide layer 121, and the silicon oxide layer is disposed on the silicon nitride layer. The silicon nitride layer may be, for example, Figure 1 the nitride layer 1231 as shown.

[0058] Please refer to Figure 1 andFigure 2 As shown, in an embodiment of the present invention, a protective layer 200 is formed on a semiconductor structure 100. In this embodiment, silicon nitride is deposited on a substrate 110, on a gate structure 120, and on a metal silicide 116 by means of chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) to form a protective layer 200 in the shape of a thin film, so as to protect the semiconductor structure 100 from being damaged during subsequent manufacturing processes. The protective layer 200 covers the semiconductor structure 100.

[0059] Please refer to Figure 2 and Figure 3 As shown, in an embodiment of the present invention, a first interlayer dielectric layer 300 is formed on the protective layer 200. In this embodiment, silicon oxide is deposited on the protective layer 200 by means of chemical vapor deposition or plasma enhanced chemical vapor deposition to form the first interlayer dielectric layer 300. The thickness of the first interlayer dielectric layer 300 is greater than the height of the gate structure 120. Specifically, the first interlayer dielectric layer 300 covers the gate structure 120. It should be noted that, as Figure 3 shown, when the first interlayer dielectric layer 300 is formed, the surface of the first interlayer dielectric layer 300 is uneven. Specifically, the area where the first interlayer dielectric layer 300 covers the gate structure 120 is higher than the area where it covers the substrate 110, and the area where the first interlayer dielectric layer 300 covers the gate structure 120 is higher than the area where it covers the metal silicide 116.

[0060] Please refer to Figure 3 and Figure 4As shown, in an embodiment of the present invention, the surface of the first interlayer dielectric layer 300 is polished to expose the sidewall structure 123 covering the polysilicon layer 122, and the surface of the first interlayer dielectric layer 300 is made flush with the surface of the nitride layer 1231. In this embodiment, the nitride layer 1231 is a layer of silicon nitride in the sidewall structure 123 that directly covers the polysilicon layer 122. And the nitride layer 1231 is the innermost layer of the sidewall structure 123. In this embodiment, the first interlayer dielectric layer 300 and a part of the sidewall structure 123 are processed by Chemical Mechanical Polishing (CMP). Specifically, taking the nitride layer 1231 covering the top of the polysilicon layer 122 as the polishing stop layer, a part of the first interlayer dielectric layer 300 and a part of the sidewall structure 123 are ground and removed. The part of the sidewall structure 123 removed is the part of the sidewall structure 123 above the nitride layer 1231 covering the top of the polysilicon layer 122. At this time, the surfaces of the first interlayer dielectric layer 300 and the nitride layer 1231 are flush.

[0061] Please refer to Figures 4 to 6 As shown, in an embodiment of the present invention, after grinding the first interlayer dielectric layer 300, a stacked structure is formed on the first interlayer dielectric layer 300. In this embodiment, Boro phospho silicate Glass (BPSG) is deposited on the first interlayer dielectric layer 300 by chemical vapor deposition or plasma enhanced chemical vapor deposition, etc., so as to form the second interlayer dielectric layer 400. Then a protective layer 410 is formed on the second interlayer dielectric layer 400. The protective layer 410 is an APF film, and the material is amorphous carbon. Then a plurality of lithography assist layers are formed on the protective layer 410. In this embodiment, the lithography assist layers include a first anti-reflection layer 420 and a second anti-reflection layer 430. The anti-reflection layer is an ARC film (Anti-Reflection Coating, ARC). Then a photoresist is spin-coated on the second anti-reflection layer 430 to form a first photoresist layer 500. The first photoresist layer 500 is patterned by exposure and etching, etc. to form a plurality of lithography trenches 510, and the first photoresist layer 500 is converted into a first photoresist pattern. In this embodiment, the orthographic projection of a part of the lithography trenches 510 on the gate structure 120 is located on the polysilicon layer 122, and the orthographic projection of another part of the lithography trenches 510 on the substrate 110 is located on the metal silicide 116. And the groove width of the lithography trenches 510 located on the polysilicon layer 122 is greater than the groove width of the lithography trenches 510 located on the metal silicide 116. It should be noted that the present invention does not limit the bottom of the lithography trenches 510. The bottom of the lithography trenches 510 in this embodiment can be the first anti-reflection layer 420.

[0062] Please refer to Figure 6 and Figure 7As shown, in an embodiment of the present invention, using the first photoresist pattern as a mask, part of the first anti-reflection layer 420, part of the protective layer 410, part of the second interlayer dielectric layer 400, and part of the first interlayer dielectric layer 300 are removed by dry etching to form a first type of trench 520 and a second type of trench 530. In this embodiment, under the same etching environment and the same etching object, since the groove width of the photolithography trench 510 located on the metal silicide 116 is smaller, the etching depth is larger, and it will directly etch into the first interlayer dielectric layer 300, thereby forming the first type of trench 520. While the groove width of the photolithography trench 510 located on the polysilicon layer 122 is larger, so the etching depth is smaller, and it only etches into the second interlayer dielectric layer 400, thereby forming the second type of trench 530. The groove width of the second type of trench 530 is greater than that of the first type of trench 520. In this embodiment, when forming the first type of trench 520, the etching stops at any position of the first interlayer dielectric layer 300. For example, the etching can stop when reaching the middle of the first interlayer dielectric layer 300 to form the first type of trench 520 and the second type of trench 530. After forming the first type of trench 520 and the second type of trench 530, the first photoresist pattern, the first anti-reflection layer 420, the second anti-reflection layer 430, and the protective layer 410 are washed away to expose the second interlayer dielectric layer 400.

[0063] Please refer to Figures 7 to 9 As shown, in an embodiment of the present invention, the first type of trench 520 and the second type of trench 530 are filled with photoresist to form a second photoresist layer 600. In this embodiment, after the photoresist fills the first type of trench 520 and the second type of trench 530, the photoresist continues to accumulate and a film-like structure is formed on the second interlayer dielectric layer 400, such as Figure 8 As shown, thereby forming the second photoresist layer 600. Then, the second photoresist layer 600 is processed by exposure and development, etc., thereby forming a second photoresist pattern 610. When patterning the second photoresist layer 600, part of the photoresist located in the first type of trench 520 and the second type of trench 530 is retained, and part of the photoresist located on the second interlayer dielectric layer 400 is retained. In this embodiment, the second photoresist pattern 610 is located on the second interlayer dielectric layer 400, in the first type of trench 520, or in the second type of trench 530.

[0064] Please refer to Figures 9 to 11As shown, in an embodiment of the present invention, using the second photoresist pattern 610 as a mask layer, a portion of the second interlayer dielectric layer 400 is removed to form a first wiring trench 620 and a second wiring trench 630, and a convex structure 440 is formed. In this embodiment, the second photoresist pattern 610 remaining in the first type of trench 520 and the second type of trench 530 can protect these portions of the first type of trench 520 and the second type of trench 530 from being etched. On the second interlayer dielectric layer 400, the area not covered by the second photoresist pattern 610 is etched until reaching the top surface of the second photoresist pattern 610 located in the first type of trench 520 and the second type of trench 530, thereby forming the first wiring trench 620 and the second wiring trench 630. The bottom of the first wiring trench 620 is connected to the top surface of the second photoresist pattern 610 located in the first type of trench 520 and the second type of trench 530. In this embodiment, while forming the first wiring trench 620, a plurality of stepped convex structures 440 are formed on the top of the second interlayer dielectric layer 400. In this embodiment, the orthographic projection of the first wiring trench 620 on the substrate 110 connects the source electrode of the first device and the drain electrode of the second device. The first device and the second device are adjacent. The orthographic projection of the second wiring trench 630 on the gate structure 120 overlaps with the polysilicon layer 122. In this embodiment, the orthographic projection of the second wiring trench 630 on the gate structure 120 covers the polysilicon layer 122. Then, the second photoresist pattern 610 is removed to expose the first type of trench 520 and the second type of trench 530. In this embodiment, the first wiring trench 620 communicates with the first type of trench 520 of different devices. The second wiring trench 630 communicates with the second type of trench 530.

[0065] Please refer to Figure 11 and Figure 12 As shown, in an embodiment of the present invention, the first type of trench 520 is deepened so that the first type of trench 520 extends to the top surface of the metal silicide 116. The second type of trench 530 is deepened so that the second type of trench 530 extends to the top surface of the polysilicon layer 122. In this embodiment, using the top surface of the metal silicide 116 as an etch stop layer, the first interlayer dielectric layer 300 is etched to deepen the first type of trench 520. At the same time, using the top surface of the polysilicon layer 122 as an etch stop layer, the second interlayer dielectric layer 400 is etched to deepen the second type of trench 530. It should be noted that in this etching step, using the signal of exposing the surface of the metal silicide 116 as the etch stop can cause the polysilicon layer 122 to be etched a little more.

[0066] Please refer to Figure 12 and Figure 13As shown, in an embodiment of the present invention, the polysilicon layer 122 is etched away to continue deepening the second type of trench 530 until the polysilicon layer 122 is completely removed. In this embodiment, the polysilicon layer 122 is removed by wet etching. In another embodiment of the present invention, in the step of deepening the first type of trench 520, after the surface of the metal silicide 116 is exposed, the polysilicon layer 122 can be continuously etched until the polysilicon layer 122 is removed. Since the materials of the metal silicide 116 and the polysilicon layer 122 are completely different, the surface of the metal silicide 116 can still remain undamaged in the step of removing the polysilicon layer 122.

[0067] Please refer to Figure 1 , Figures 13 to 15 As shown, in an embodiment of the present invention, the first type of trench 520 and the second type of trench 530 are filled to form a metal interconnect structure and a metal gate 800. And the surface of the metal interconnect structure is polished so that the top surface of the metal interconnect structure is flush with the top surface of the convex structure 440. In this embodiment, the first type of trench 520, the second type of trench 530, the first wiring trench 620, and the second wiring trench 630 are filled with a metal material, such as copper-aluminum alloy and tungsten, by chemical vapor deposition or sputtering, etc., so as to form a metal gate 800 in the second type of trench 530, a contact plug 710 in the first type of trench 520 and the first wiring trench 620, and a metal layer 700 in the second wiring trench 630. The metal gate 800 is disposed on the gate oxide layer 121. Among them, after the first wiring trench 620 and the second wiring trench 630 are filled, the metal material is continuously accumulated to increase the thickness of the metal layer 700. At this time, the metal layer 700 is electrically connected to the metal gate 800. In this embodiment, the metal layer 700 is polished by chemical mechanical polishing to reduce the thickness of the metal layer 700 until the surface of the metal layer 700 is flush with the top surface of the convex structure 440. At this time, the metal layer 700 is electrically connected to the source electrode of one device and the drain electrode of another device, and the metal gate 800 is separately led out. In this embodiment, to ensure that the convex structure 440 can play a good partitioning role, a part of the convex structure 440 can be removed during polishing, so that the surface of the convex structure 440 is flush with the surface of the metal layer 700, and the semiconductor device structure of the present invention is formed. For easy distinction, Figure 15 the structure of the metal gate 800 is separately shown in

[0068] The present invention provides a method for manufacturing a semiconductor device and a semiconductor device. By etching a part of the second interlayer dielectric layer and a part of the first interlayer dielectric layer, a first type of trench is formed on the side of the gate structure, and at the same time, a part of the first interlayer dielectric layer is etched to form a second type of trench above the gate structure. The second interlayer dielectric layer is etched to form a convex structure, a first wiring trench, and a second wiring trench, wherein one side of the convex structure is the first wiring trench, and the other side of the convex structure is the second wiring trench. The first interlayer dielectric layer and the second interlayer dielectric layer are etched to deepen the first type of trench and the second type of trench until the first type of trench is connected to the metal silicide of the semiconductor structure and the second type of trench is connected to the gate oxide layer of the gate structure. Part of the second type of trench is filled to form a metal gate, and at the same time, the first type of trench and part of the second type of trench are filled to form a contact plug. And the first wiring trench and the second wiring trench are filled to form a metal layer. The unexpected technical effect of the present invention is that in the forming process of the gate and the contact hole, not only metal residue is avoided, but also non-preset depressions caused by over-etching can be avoided. Therefore, the forming yield of the metal gate is high, and the defects brought by the polishing process and the load effect to the gate forming and the contact hole forming can be reduced, thereby improving the yield of the gate forming and the contact hole forming process, and thus improving the reliability of the semiconductor device. Moreover, the method for manufacturing a semiconductor device and the semiconductor device provided by the present invention have a low process complexity and a high manufacturing efficiency.

[0069] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art in the relevant technical field can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: A semiconductor structure is provided, the semiconductor structure comprising a substrate and a gate structure, wherein the gate structure is disposed on the substrate; forming a first interlayer dielectric layer on the semiconductor structure, and forming a second interlayer dielectric layer on the first interlayer dielectric layer; Etching a portion of the second interlayer dielectric layer and a portion of the first interlayer dielectric layer to form a first type of trench on the side of the gate structure, and etching a portion of the first interlayer dielectric layer to form a second type of trench on the gate structure; Etching the second interlayer dielectric layer to form a convex structure, a first wiring groove and a second wiring groove, wherein one side of the convex structure is the first wiring groove, and the other side of the convex structure is the second wiring groove; Etching the first interlayer dielectric layer and the second interlayer dielectric layer to deepen the first type of trench and the second type of trench until the first type of trench is connected to the metal silicide of the semiconductor structure and the second type of trench is connected to the gate oxide layer of the gate structure; Filling a portion of the second type of trench to form a metal gate, and simultaneously filling the first type of trench and a portion of the second type of trench to form a contact plug; as well as The first wiring trench and the second wiring trench are filled to form a metal layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The step of forming the first interlayer dielectric layer comprises: forming a protective layer on the semiconductor structure, forming a first interlayer dielectric layer on the protective layer; and The first interlayer dielectric layer is ground until the first interlayer dielectric layer is flush with the nitride layer of the gate structure, wherein the nitride layer covers the polysilicon layer of the gate structure.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that: After forming the second interlayer dielectric layer, a stacked structure is formed on the second interlayer dielectric layer, wherein the stacked structure includes a protective layer, an anti-reflection layer and a first photoresist layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the step of etching to form the first type of grooves and the second type of grooves, the orthographic projection of the etching window of the first type of grooves on the substrate overlaps with the functional area of ​​the semiconductor structure, and the orthographic projection of the etching window of the second type of grooves on the substrate overlaps with the polysilicon layer of the gate structure.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The width of the etching window for forming the second type of trench is greater than the width of the etching layer window for forming the first type of trench.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The step of forming the first wiring trench and the second wiring trench comprises: etching the second interlayer dielectric layer between adjacent first-type trenches to form the first wiring trenches; and At the same time, a portion of the second interlayer dielectric layer located between the first type of trench and the second type of trench is etched to form the second wiring trench, and a convex structure is formed between the first type of trench and the second type of trench.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the step of forming the first type trench and the second type trench, the bottom of the first type trench is formed in the middle of the first interlayer dielectric layer, and the bottom of the second type trench is formed in the middle of the second interlayer dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: After forming the first type of grooves and the second type of grooves, a photoresist pattern is formed in the first type of grooves and the second type of grooves, and on the second interlayer dielectric layer between the first type of grooves and the second type of grooves.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the step of forming the metal layer, after the first wiring groove and the second wiring groove are filled, the metal layer is ground until the metal layer is flush with the surface of the protrusion structure.

10. A semiconductor device, based on the method for manufacturing a semiconductor device according to claim 1, characterized in that: The semiconductor device comprises: A semiconductor structure, comprising a substrate and a gate structure, wherein the gate structure is disposed on the substrate; A first interlayer dielectric layer is disposed on the semiconductor structure; A second interlayer dielectric layer is disposed on the first interlayer dielectric layer, wherein the second interlayer dielectric layer includes a convex structure, one side of the convex structure is a first wiring groove, and the other side of the convex structure is a second wiring groove; A plurality of first-type trenches, passing through the first interlayer dielectric layer and the second interlayer dielectric layer, connected to the metal silicide of the semiconductor structure, wherein the first-type trenches are connected to the first wiring trenches; A second type of trench, passing through the first interlayer dielectric layer and connected to the gate oxide layer of the gate structure, wherein the second type of trench is connected to the second wiring trench; a metal gate, filling the second type of trench and covering the gate oxide layer; a contact plug filled in the first type trench and the second type trench and connected to the metal gate or the metal silicide; and A metal layer is filled in the first wiring trench and the second wiring trench and is connected to the contact plug.

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