Multi-interdigital bipolar transistor structure based on thermal coupling optimization

Abstract

The invention discloses a multi-interdigital bipolar transistor structure based on thermal coupling optimization. The multi-interdigital bipolar transistor structure comprises a silicon-based substrate and an epitaxial layer, n interdigital structures are sequentially arranged in the bipolar transistor device region of the epitaxial layer along the length direction of the bipolar transistor device region; each interdigital structure comprises a base region, an emitter region and a deep collector contact region, the base region is arranged in the top region of the epitaxial layer, and the emitter region is arranged in the top region of the base region; the deep collector contact region is arranged on one side of the base region and vertically extends downwards from the top of the epitaxial layer to the bottom of the epitaxial layer; and the lengths of the emitter regions in the interdigital structures are sequentially reduced along the direction from the edge to the middle of the bipolar transistor device region. According to the multi-interdigital bipolar transistor, the length of the emitter region of the edge interdigital structure in the multi-interdigital bipolar transistor is increased, and the length of the emitter region of the middle interdigital structure in the multi-interdigital bipolar transistor is reduced, so that the junction temperature difference between the edge interdigital structure and the middle interdigital structure in the multi-interdigital bipolar transistor can be reduced, and the performance stability of a device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a multi-finger bipolar transistor structure based on thermal coupling optimization. Background Art

[0002] Multi-finger bipolar transistors are commonly used in power amplifiers, and their device structure is usually composed of multiple emitter fingers (interdigital structures) with the same width and length arranged at equal intervals. However, the high current operating conditions of the power amplifier will cause electro-thermal coupling heating inside the device, thereby causing the junction temperature to rise. The total temperature of each interdigital structure comes from the self-heating effect caused by its own power dissipation and the thermal coupling effect with the adjacent interdigital structure. Since all the interdigital structures inside the same device are thermally coupled through the silicon substrate, the thermal coupling of the interdigital structure located in the middle of the multi-finger bipolar transistor is much greater than that of the interdigital structure at the edge of the device, resulting in a higher junction temperature in the middle of the device. Non-uniform temperature distribution will cause problems such as degradation of the device's electrical characteristics and thermal runaway, ultimately affecting the device's safe operating area and reliability. Therefore, how to improve the thermal coupling effect of the multi-finger bipolar transistor so that the interdigital structures inside the device have a uniform temperature distribution, thereby improving the performance stability of the device, is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a multi-finger bipolar transistor structure based on thermal coupling optimization.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A multi-finger bipolar transistor structure based on thermal coupling optimization comprises a silicon-based substrate and an epitaxial layer arranged on the silicon-based substrate; N finger structures are sequentially arranged in the bipolar transistor device region of the epitaxial layer along its length direction, where N is an integer greater than or equal to 3; each of the finger structures comprises a base region, an emitter region and a deep collector contact region, the base region is arranged in the top region of the epitaxial layer, and the emitter region is arranged in the top region of the base region; the deep collector contact region is arranged on one side of the base region, and the deep collector contact region extends vertically downward from the top of the epitaxial layer to the bottom of the epitaxial layer; along the direction from the edge to the middle of the bipolar transistor device region, the length of the emitter region in the finger structure decreases sequentially.

[0006] Furthermore, the interdigitated structure also includes a base contact arranged on the base region outside the emitter region, an emitter contact arranged on the emitter region, and a collector contact arranged on the deep collector contact region, wherein the base contact is connected to the base region outside the emitter region; the emitter contact is connected to the emitter region; and the collector contact is connected to the deep collector contact region.

[0007] Furthermore, the multi-finger bipolar transistor further includes a buried layer, which is disposed in a bottom region of the epitaxial layer and extends from the bottom region of the epitaxial layer to an upper region of the silicon-based substrate.

[0008] Furthermore, the epitaxial layer is provided with a circle of isolation grooves between the bipolar transistor device regions, the isolation grooves penetrate the epitaxial layer and extend into the silicon-based substrate, and isolation oxide is provided in the isolation grooves.

[0009] Furthermore, when N is an even number, the lengths of the emission regions of the N / 2th and (N / 2+1)th finger structures are the shortest and equal; when N is an odd number, the length of the emission region of the (N+1) / 2th finger structure is the shortest.

[0010] Furthermore, the widths of the emission regions of the interdigital structures are all equal.

[0011] Further, the spacing between the centers of the emission regions of two adjacent interdigitated structures is defined as the spacing between two adjacent interdigitated structures; N is an integer greater than or equal to 4; and along the direction from the edge to the middle of the bipolar transistor device region, the spacing between two adjacent interdigitated structures increases successively.

[0012] Furthermore, when N is an even number, the distance between the N / 2th interdigital structure and the (N / 2+1)th interdigital structure is the largest; when N is an odd number, the distance between the (N-1) / 2th interdigital structure and the (N+1) / 2th interdigital structure is the largest and equal to the distance between the (N+1) / 2th interdigital structure and the (N+3) / 2th interdigital structure.

[0013] Furthermore, the calculation formula for the junction temperature change of the interdigital structure is as follows:

[0014]

[0015] Where i represents the index of the interdigitated structure; ΔT i Indicates the junction temperature change of the i-th interdigital structure; ΔT ii Indicates the junction temperature rise of the i-th interdigit structure due to the self-heating effect; ΔT ij represents the junction temperature increase of the i-th interdigital structure due to the thermal coupling effect of the j-th interdigital structure; P d,i represents the electric power dissipation of the i-th interdigital structure; Rth,ii represents the thermal resistance of the i-th interdigital structure; P d,j represents the electrical power dissipation of the j-th interdigital structure; R th,jj represents the thermal resistance of the jth interdigital structure, c ij is the static thermal coupling coefficient, which represents the thermal coupling coefficient of the i-th interdigital structure caused by the heat generated by the j-th interdigital structure.

[0016] Furthermore, the length of the emission region in each finger structure and the spacing between adjacent finger structures are adjusted according to the calculation formula of the junction temperature change of the finger structure, so that the total temperature of the finger structure and the difference between the total temperature of each finger structure are within a preset range.

[0017] In the present invention, the emission region length of the edge finger structure in the multi-finger bipolar transistor is increased and the spacing between adjacent finger structures at the edge is reduced, so that the self-heating effect and thermal coupling effect of the edge finger structure are increased, and the emission region length of the middle finger structure is reduced and the spacing between the middle finger structures is increased, so that the self-heating effect and thermal coupling effect of the middle finger structure are reduced, thereby reducing the junction temperature difference between the edge finger structure and the middle finger structure in the multi-finger bipolar transistor, so that the multi-finger bipolar transistor presents a more uniform temperature distribution and a lower overall junction temperature, thereby improving the performance stability of the device, and having obvious advantages in circuit applications with large current working requirements such as power amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A top view of an embodiment of a multi-finger bipolar transistor structure based on thermal coupling optimization of the present invention.

[0020] Figure 2 for Figure 1 Schematic diagram of the A-A' cross section.

[0021] Figure 3 It is a schematic structural diagram of the emission region of each interdigitated structure when the number of interdigitated structures is an even number.

[0022] Figure 4 It is a schematic structural diagram of the emission region of each interdigitated structure when the number of interdigitated structures is an odd number.

[0023] Figure 5 FIG. 4 is a junction temperature distribution diagram of a multi-finger bipolar transistor in the prior art.

[0024] Figure 6It is a temperature comparison diagram of the multi-finger bipolar transistor in the prior art and the multi-finger bipolar transistor in this embodiment.

[0025] The accompanying drawings in the specification are numeraled as follows:

[0026] Silicon-based substrate-100; epitaxial layer-200; collector region-210; base region-310; base contact-311; emitter region-320; emitter contact-321; deep collector contact region-330; collector contact-331; buried layer-400; isolation trench-500; isolation oxide-510; interlayer dielectric layer-600. DETAILED DESCRIPTION

[0027] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0028] See also Figure 1 and Figure 2 A preferred embodiment of the multi-finger bipolar transistor structure based on thermal coupling optimization of the present invention includes a silicon-based substrate 100, on which an epitaxial layer 200 is arranged; the epitaxial layer 200 is generally divided into a plurality of device regions, each of which is used to form a device. The device regions generally include bipolar transistor device regions for forming multi-finger bipolar transistor devices and other device regions for forming other devices. For example, the other device regions may be resistor device regions for forming resistor devices, capacitor device regions for forming capacitor devices, etc. The bipolar transistor device region of the epitaxial layer 200 has a length direction (i.e., Figure 1 In the x-axis direction, N interdigital structures are arranged in sequence, where N is an integer greater than or equal to 3.

[0029] Each of the interdigitated structures includes a base region 310, an emitter region 320 and a deep collector contact region 330. The base region 310 is arranged in the epitaxial layer 200 and is located at the top of the epitaxial layer 200 (i.e., the base region 310 is arranged in the top region of the epitaxial layer 200). The emitter region 320 is arranged in the base region 310 and is located at the top of the base region 310 (i.e., the emitter region 320 is arranged in the top region of the base region 310). The deep collector contact region 330 is arranged on one side of the base region 310, and the deep collector contact region 330 extends vertically downward from the top of the epitaxial layer 200 to the bottom of the epitaxial layer 200. Of course, the interdigitated structure also includes a collector region 210. The region in the epitaxial layer 200 of each bipolar transistor device region where the base region 310, the emitter region 320 and the deep collector contact region 330 are not arranged forms the collector region 210 of the bipolar transistor device region.

[0030] Of course, the interdigitated structure may also include a base contact 311, an emitter contact 321 and a collector contact 331 disposed on the epitaxial layer 200. On the epitaxial layer 200, the base contact 311, the emitter contact 321 and the collector contact 331 are independent of each other. The base contact 311 is disposed on the base region 310 outside the emitter region 320 and is connected to the base region 310 outside the emitter region 320; the emitter contact 321 is disposed above the emitter region 320 and is connected to the emitter region 320; the collector contact 331 is disposed above the deep collector contact region 330 and is connected to the deep collector contact region 330. Generally, an interlayer dielectric layer 600 is also provided on the epitaxial layer 200, and the base contact 311, the emitter contact 321 and the collector contact 331 are all provided on the interlayer dielectric layer 600, and can form contact with the base region 310, the emitter region 320 or the deep collector contact region 330 by forming contact holes in the interlayer dielectric layer 600. Of course, the base contact 311, the emitter contact 321 and the collector contact 331 can also form contact with the base region 310, the emitter region 320 or the deep collector contact region 330 by other means.

[0031] The multi-finger bipolar transistor generally further includes a buried layer 400, which is disposed in the bottom region of the epitaxial layer 200 and extends from the bottom region of the epitaxial layer 200 to the upper region of the silicon-based substrate 100. The doping type of the buried layer 400 is the same as that of the epitaxial layer 200. When the current of the transistor flows from the emitter contact 321 to the collector contact 331, the current direction is from the emitter contact 321 through the emitter region 320, the base region 310, the epitaxial layer 200 between the base region 310 and the buried layer 400 (i.e., the collector region 210), the buried layer 400, the deep collector contact region 330 to the collector contact 331. It should be noted that although in Figure 2 There is a gap between the deep collector contact region 330 and the buried layer 400 , but after diffusion, the deep collector contact region 330 and the buried layer 400 are actually connected through the diffusion region.

[0032] In order to isolate the bipolar transistor device area, a circle of isolation grooves 500 are generally provided on the epitaxial layer 200 at the periphery of each bipolar transistor device area. The isolation grooves 500 penetrate the epitaxial layer 200 and extend into the silicon-based substrate 100. An isolation oxide 510 is provided in the isolation grooves 500 to form an isolation area, and electrical isolation of the bipolar transistor device area on the wafer is achieved through the isolation area.

[0033] In view of the problem that the thermal coupling of the interdigital structure in the middle of the existing multi-finger bipolar transistor is much greater than that of the interdigital structure at the edge of the device, this embodiment changes the setting mode in which the size of the emitter region 320 in the interdigital structure of the prior art is the same and the intervals between adjacent interdigital structures are also the same. In this embodiment, along the direction from the edge of the bipolar transistor device region to the middle, the length L of the emitter region 320 in the interdigital structure is E The width W of the emission region 320 of each interdigital structure is reduced in sequence, thereby reducing the difference in thermal coupling of each interdigital structure. E It should be noted that, since each interdigital structure is a whole, when the size of the emitter region 320 in the interdigital structure changes, the sizes of the base region 310, the collector region 210 and the deep collector contact region 330 in the interdigital structure will also change accordingly.

[0034] See also Figure 3 , when N is an even number, the N / 2th interdigital structure and the (N / 2+1)th interdigital structure are both located in the middle of the bipolar transistor device region ( Figure 3 1, 2, 3, ..., N / 2+1, (N / 2+1), ..., (N-2), (N-1), N above the middle emitting region 320 are the serial numbers of the interdigitated structures. Therefore, the length L of the emitting region 320 of the N / 2th interdigitated structure is N / 2 and the length L of the emission region 320 of the (N / 2+1)th interdigital structure N / 2+1 are the shortest and equal, that is: L1>L2>L3>……>L N / 2-1 >L N / 2 ; L N / 2 =L N / 2+1 ; correspondingly, L N / 2-1 =L N / 2+2 ; L N / 2-2 =L N / 2+3 ; ... ; L2 = L N-1 ; L1=L N Wherein, L1 represents the length of the emission region 320 of the first interdigital structure, L2 represents the length of the emission region 320 of the second interdigital structure, L3 represents the length of the emission region 320 of the third interdigital structure, and so on. N-1 represents the length of the emission region 320 of the (N-1)th interdigital structure, L N represents the length of the emission region 320 of the Nth interdigitated structure.

[0035] See also Figure 4 , when N is an odd number, the (N+1) / 2th interdigital structure is located in the middle of the bipolar transistor device region ( Figure 41, 2, 3, ..., (N-1) / 2, (N+1) / 2, (N+3) / 2, ..., (N-2), (N-1), N above the middle emitting region 320 are the serial numbers of the interdigitated structures. Therefore, the length L of the emitting region 320 of the (N+1) / 2th interdigitated structure is (N+1) / 2 The shortest, that is: L1>L2>L3>……>L (N-1) / 2 >L (N+1) / 2 ; L (N-1) / 2 =L (N+3) / 2 ; L (N-3) / 2 =L (N+5) / 2 ; ... ; L2 = L N-1 ; L1=L N .

[0036] The spacing between the centers of the emission regions 320 of two adjacent interdigital structures is defined as the spacing between the two adjacent interdigital structures; in order to further reduce the difference in thermal coupling of the interdigital structures, when N is an integer greater than or equal to 4, the spacing S between the two adjacent interdigital structures can also be set along the direction from the edge to the middle of the bipolar transistor device region. E Of course, when the spacing between the emitter regions 320 of adjacent interdigital structures changes, the spacing between the emitter regions 320 of the interdigital structures and the base region 310 and the deep collector contact region 330 will also change accordingly, that is, the internal structure of each interdigital structure changes in an integrated form.

[0037] Please continue reading Figure 3 When N is an even number, the N / 2th interdigital structure and the (N / 2+1)th interdigital structure are both located in the middle of the bipolar transistor device region. At this time, there are (N-1) spacing values ​​between adjacent interdigital structures, and the spacing S between the N / 2th interdigital structure and the (N / 2+1)th interdigital structure is N / 2 Maximum, that is: S1<S2<S3<……<S N / 2-1 <S N / 2 ; S N / 2-1 =S N / 2+1 ; S N / 2-2 =S N / 2+2 ; S N / 2-3 =S N / 2+3 ; ... ; S2 = S N-2 ; S1 = S N-1 . Wherein, S1 represents the distance between the first interdigital structure and the second interdigital structure, S2 represents the distance between the second interdigital structure and the third interdigital structure, S3 represents the distance between the third interdigital structure and the fourth interdigital structure, and so on. N-1 represents the distance between the (N-1)th interdigital structure and the Nth interdigital structure.

[0038] Please continue reading Figure 4 , when N is an odd number, the (N+1) / 2th interdigital structure is located in the middle of the bipolar transistor device region. At this time, there are (N-1) spacing values ​​between adjacent interdigital structures, and the spacing S between the (N-1) / 2th interdigital structure and the (N+1) / 2th interdigital structure is (N-1) / 2 The spacing S between the (N+1) / 2nd interdigital structure and the (N+3) / 2nd interdigital structure (N+1) / 2 Maximum and equal, that is: S1<S2<S3<……<S (N-3) / 2 <S (N-1) / 2 ; S (N-1) / 2 =S (N+1) / 2 ; correspondingly, S (N-3) / 2 =S (N+3) / 2 ; S (N-5) / 2 =S (N+5) / 2 ; ... ; S2 = S N-2 ; S1 = S N-1 .

[0039] The calculation formula for the junction temperature change of the interdigital structure is as follows:

[0040]

[0041] Where i represents the index of the interdigitated structure; ΔT i Indicates the junction temperature change of the i-th interdigital structure; ΔT ii Indicates the junction temperature rise of the i-th interdigit structure due to the self-heating effect; ΔT ij It indicates that the junction temperature of the i-th interdigital structure increases due to the thermal coupling of the j-th interdigital structure. d Represents the electrical power dissipation of the interdigital structure; P d,i represents the electric power dissipation of the i-th interdigital structure; P d,j represents the electrical power dissipation of the j-th interdigital structure; R th Represents the thermal resistance of the interdigital structure; R th,ii represents the thermal resistance of the i-th interdigital structure; R th,jj represents the thermal resistance of the jth interdigital structure, c ij is the static thermal coupling coefficient, which represents the thermal coupling coefficient of the i-th interdigital structure caused by the heat generated by the j-th interdigital structure.

[0042] See also Figure 5 , due to P d , R th 、c ij The length L of the emitting area 320 of the interdigital structure E Related, and c ij The spacing S between the interdigital structures E Related, that is, L E The larger the Pd , R th 、c ij The larger the S E The larger the c ij Therefore, when the multi-finger bipolar transistor is composed of N interdigital structures with the same length and width of the emitter region 320 arranged at equal intervals, the interdigital structure located in the middle has a much higher junction temperature than the interdigital structures at the edge due to the strong thermal coupling effect with the surrounding interdigital structures, which leads to uneven temperature distribution inside the multi-finger bipolar transistor and increased total temperature.

[0043] Therefore, by reducing the length of the emission region 320 of the middle interdigital structure and increasing the spacing between the adjacent interdigital structures in the middle (i.e., the spacing between the emission regions 320 of the adjacent interdigital structures), the thermal coupling effect and the junction temperature of the middle interdigital structure can be effectively reduced, and by increasing the length of the emission region 320 of the edge interdigital structure and reducing the spacing between the adjacent interdigital structures at the edge, the thermal coupling effect and the junction temperature of the edge interdigital structure can be appropriately increased. In this embodiment, the length of the emission region 320 in each interdigital structure and the spacing between each adjacent interdigital structure are adjusted according to the calculation formula for the junction temperature change of the interdigital structure, so that the total temperature of the interdigital structure and the difference between the total temperatures of each interdigital structure are within a preset range, so that the multi-finger bipolar transistor has a relatively uniform temperature distribution and a lower total temperature, thereby improving the performance stability of the device.

[0044] See also Figure 6 The total temperature of the multi-finger bipolar transistor (i.e., the optimized device) after optimizing the length of the emitter region 320 and the spacing between adjacent finger structures in this embodiment is compared with that of a conventional multi-finger bipolar transistor (i.e., the unoptimized device) with the same layout area and number of finger structures, the same length of the emitter region 320 and the same spacing between adjacent finger structures. It is found that the overall temperature of the optimized device and the temperature difference between each finger structure are significantly smaller than those of the unoptimized device, indicating that the multi-finger bipolar transistor structure based on thermal coupling optimization proposed in this embodiment has a good effect.

[0045] In this embodiment, by increasing the length of the emission region 320 of the edge finger structure in the multi-finger bipolar transistor and reducing the spacing between the adjacent finger structures at the edge, the self-heating effect and thermal coupling effect of the edge finger structure are increased, and by reducing the length of the emission region 320 of the middle finger structure and increasing the spacing between the middle finger structures, the self-heating effect and thermal coupling effect of the middle finger structure are reduced, thereby reducing the junction temperature difference between the edge finger structure and the middle finger structure in the multi-finger bipolar transistor, so that the multi-finger bipolar transistor presents a more uniform temperature distribution and a lower overall junction temperature, thereby improving the performance stability of the device. In addition, the multi-finger bipolar transistor device structure based on thermal coupling optimization in this embodiment is compatible with the existing bipolar transistor manufacturing process, does not increase the complexity of the manufacturing process and the manufacturing cost, and the optimized multi-finger bipolar transistor has obvious advantages in circuit applications with large current working requirements such as power amplifiers.

[0046] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A multi-finger bipolar transistor structure based on thermal coupling optimization, characterized in that: It comprises a silicon-based substrate and an epitaxial layer arranged on the silicon-based substrate; N interdigital structures are sequentially arranged in the bipolar transistor device region of the epitaxial layer along its length direction, where N is an integer greater than or equal to 3; each of the interdigital structures comprises a base region, an emitter region and a deep collector contact region, the base region is arranged in the top region of the epitaxial layer, and the emitter region is arranged in the top region of the base region; the deep collector contact region is arranged on one side of the base region, and the deep collector contact region extends vertically downward from the top of the epitaxial layer to the bottom of the epitaxial layer; Along the direction from the edge to the middle of the bipolar transistor device region, the length of the emission region in the interdigital structure decreases successively.

2. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 1, characterized in that: The interdigitated structure also includes a base contact arranged on the base region outside the emitter region, an emitter contact arranged on the emitter region, and a collector contact arranged on the deep collector contact region, wherein the base contact is connected to the base region outside the emitter region; the emitter contact is connected to the emitter region; and the collector contact is connected to the deep collector contact region.

3. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 2, characterized in that: The multi-finger bipolar transistor further includes a buried layer, which is disposed in a bottom region of the epitaxial layer and extends from the bottom region of the epitaxial layer to an upper region of the silicon-based substrate.

4. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 3, characterized in that: The epitaxial layer is provided with a circle of isolation grooves between each bipolar transistor device region. The isolation grooves penetrate the epitaxial layer and extend into the silicon-based substrate. Isolation oxide is provided in the isolation grooves.

5. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 1, characterized in that: When N is an even number, the length of the emission area of ​​the N / 2th interdigital structure and the (N / 2+1)th interdigital structure is the shortest and equal; when N is an odd number, the length of the emission area of ​​the (N+1) / 2th interdigital structure is the shortest.

6. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 1, characterized in that: The widths of the emission regions of the interdigital structures are all equal.

7. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 1, characterized in that: The distance between the centers of the emission regions of two adjacent interdigital structures is defined as the distance between the two adjacent interdigital structures; N is an integer greater than or equal to 4; along the direction from the edge to the middle of the bipolar transistor device area, the distance between the two adjacent interdigital structures increases successively.

8. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 7, characterized in that: When N is an even number, the distance between the N / 2th interdigital structure and the (N / 2+1)th interdigital structure is the largest; when N is an odd number, the distance between the (N-1) / 2th interdigital structure and the (N+1) / 2th interdigital structure is the largest and equal to the distance between the (N+1) / 2th interdigital structure and the (N+3) / 2th interdigital structure.

9. The multi-finger bipolar transistor structure based on thermal coupling optimization according to any one of claims 1 to 8, characterized in that: The calculation formula for the junction temperature change of the interdigital structure is as follows: Where i represents the index of the interdigitated structure; ΔT i Indicates the junction temperature change of the i-th interdigital structure; ΔT ii Indicates the junction temperature rise of the i-th interdigit structure due to the self-heating effect; ΔT ij represents the junction temperature increase of the i-th interdigital structure due to the thermal coupling effect of the j-th interdigital structure; P d,i represents the electric power dissipation of the i-th interdigital structure; R th,ii represents the thermal resistance of the i-th interdigital structure; P d,j represents the electrical power dissipation of the j-th interdigital structure; R th,jj represents the thermal resistance of the jth interdigital structure, c ij is the static thermal coupling coefficient, which represents the thermal coupling coefficient of the i-th interdigital structure caused by the heat generated by the j-th interdigital structure.

10. The multi-finger bipolar transistor structure based on thermal coupling optimization according to claim 9, characterized in that: The length of the emission region in each interdigital structure and the spacing between adjacent interdigital structures are adjusted according to the calculation formula of the junction temperature change of the interdigital structure, so that the total temperature of the interdigital structure and the difference between the total temperature of each interdigital structure are within a preset range.

Images