Silicon wafer and preparation method and application thereof

Abstract

The invention discloses a silicon wafer and a preparation method and application thereof, and relates to the technical field of solar cells, and the silicon wafer comprises a silicon wafer substrate and a single-walled carbon nanotube film arranged on at least one surface of the silicon wafer substrate. The silicon wafer is applied to the battery, the photoelectric conversion efficiency of the battery is improved, the service life of the battery is prolonged, and meanwhile power attenuation is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a silicon wafer and a preparation method and application thereof. Background Art

[0002] Solar cells are a technology that uses the heterojunction interface of different semiconductor materials to form a PN junction to achieve photoelectric conversion. Usually, solar cells are composed of two or more different semiconductor materials, which form a structure with a discontinuous energy band structure at the junction. This heterojunction allows photons to be absorbed when light shines on the surface of the cell, electron-hole pairs are generated and separated, and current is generated.

[0003] Solar cells have many advantages, such as high efficiency, fast response, adaptability to a variety of spectral ranges, high stability, etc. Therefore, they can achieve efficient photoelectric conversion under different lighting conditions.

[0004] However, solar cell technologies such as heterojunction cells also have some challenges, such as complex preparation processes, high costs, unstable performance at low temperatures, etc. Therefore, continuous efforts are needed to improve heterojunction cell technology to improve its performance and reduce costs to promote its widespread application.

[0005] By the end of 2022, silicon costs accounted for 71% of HJT cells, which is the largest cost item of HJT cells. Silicon costs can be directly reduced by thinning silicon wafers. However, thinning the silicon wafers of solar cells represented by heterojunction cells will also cause a series of problems. For example, the thinned silicon wafers of solar cells will have a reduced strength due to the reduced thickness, which makes them prone to cracking or deformation; the surface becomes more fragile and easily damaged, which increases the difficulty of processing and easily causes damage and waste; the heat dissipation capacity decreases, affecting the performance and life of the battery.

[0006] In view of this, the present invention is proposed. Summary of the invention

[0007] The purpose of the present invention is to provide a silicon wafer and a preparation method and application thereof, so as to improve the strength of the silicon wafer and reduce the adverse effects on solar cells.

[0008] The present invention is achieved in that: In a first aspect, the present invention provides a silicon wafer, comprising a silicon wafer substrate and a single-walled carbon nanotube film disposed on at least one surface of the silicon wafer substrate.

[0009] In an optional embodiment, the thickness of the silicon wafer substrate is 80 μm to 120 μm.

[0010] In an optional embodiment, the single-walled carbon nanotube film has a thickness of 1 μm to 10 μm.

[0011] In an optional embodiment, the silicon wafer is an N-type single crystal silicon wafer.

[0012] In an optional embodiment, the single-walled carbon nanotube film is disposed on two oppositely disposed surfaces of the silicon wafer substrate.

[0013] In a second aspect, the present invention provides a method for preparing the silicon wafer described in the aforementioned embodiment, comprising: introducing a carbon-containing gas source into a hot wire chemical vapor deposition device on which the silicon wafer substrate is placed to deposit single-walled carbon nanotubes to form the single-walled carbon nanotube film.

[0014] In an optional embodiment, the temperature of single-walled carbon nanotube deposition is 600-800°C and the vacuum degree is 5×10 -3 pa~5×10 -5 pa.

[0015] In an optional embodiment, the roughness of the surface of the silicon wafer substrate is 0.5 nm to 3 nm.

[0016] In an optional embodiment, the diameter of the single-walled carbon nanotube is 1 nm-3 nm.

[0017] In a fifth aspect, the present invention provides a solar cell, characterized in that it comprises the silicon wafer described in any one of the aforementioned embodiments.

[0018] In an optional embodiment, the solar cell is a heterojunction cell, which includes an amorphous silicon layer, a microcrystalline silicon layer and an ITO layer sequentially arranged on the front and back sides of the silicon wafer containing the single-walled carbon nanotube film.

[0019] The present invention has the following beneficial effects: The silicon wafer in the present application is used in batteries, which is beneficial to improving the photoelectric conversion efficiency of the battery, extending the service life of the battery, and reducing power attenuation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 Schematic diagram of the structure of the heterojunction battery prepared in Example 1.

[0022] Illustration: 100 - silicon wafer; 110 - silicon wafer substrate; 120 - single-walled carbon nanotube film; 200 - amorphous silicon layer; 300 - microcrystalline silicon layer; 400 - ITO layer. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0024] The present invention provides a silicon wafer 100 , comprising a silicon wafer substrate 110 and a single-walled carbon nanotube film 120 disposed on at least one surface of the silicon wafer substrate 110 .

[0025] First, the SWCNTs film layer in the present application has high strength characteristics, and its elastic modulus is between 1000Gpa and 1200Gpa, which is higher than that of steel. The elastic modulus of the silicon wafer 100 is between 130Gpa and 188Gpa. Therefore, using the SWCNTs film layer as a protective layer for the silicon wafer substrate 110 can improve the mechanical strength of the silicon wafer 100, balance the brittleness of the silicon wafer 100, and be more helpful in preparing battery components.

[0026] Secondly, SWCNTs also have a photovoltaic effect, and its bandgap width is 0.5eV~2eV, while the bandgap width of the silicon wafer 100 is 1eV~1.2eV. The two can cooperate with each other, and the light that cannot be absorbed by the silicon wafer substrate 110 can be reabsorbed when passing through the SWCNTs film, which is beneficial to improving the battery conversion efficiency.

[0027] Thirdly, SWCNTs have excellent thermal conductivity and can conduct heat even more efficiently than copper. The thermal conductivity of the silicon wafer 100 is 100-150 W / mk, and the thermal conductivity of SWCNTs is 3000-6000 W / mk, which helps to reduce the impact of high temperature on the silicon wafer 100 and the battery using the silicon wafer 100.

[0028] Therefore, the silicon wafer 100 in the present application is used in a battery, which is beneficial to improving the photoelectric conversion efficiency of the battery, extending the service life of the battery, and reducing power attenuation.

[0029] In an optional embodiment, the thickness of the silicon wafer substrate 110 is 80 μm to 120 μm, specifically, it can be 80 μm, 90 μm, 100 μm, 110 μm, 120 μm or any value between 80 μm and 120 μm.

[0030] Thinning the silicon wafer 100 is beneficial to reducing production costs. In the prior art, the thickness of the thinned silicon wafer 100 can usually reach 80μm, but the yield rate is reduced during the battery processing, and the photoelectric conversion efficiency, service life and power attenuation of the battery prepared therefrom will all deteriorate. In the embodiment of the present application, the single-walled carbon nanotube film 120 is arranged on the surface of the silicon wafer substrate 110 to increase the strength of the silicon wafer 100, so that the silicon wafer substrate 110 can be arranged thinner, which is more conducive to cost reduction. At the same time, the yield rate during the battery processing and the photoelectric conversion efficiency, service life and power attenuation of the battery prepared therefrom can all have better performance.

[0031] In an optional embodiment, the thickness of the single-walled carbon nanotube film 120 is 1 μm to 10 μm, specifically 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or any value between 1 μm and 10 μm.

[0032] If the thickness of the single-walled carbon nanotube film 120 is too small, the effect on the strength improvement of the silicon wafer 100 and the performance of the battery prepared from the silicon wafer 100 will not be obvious; however, if the thickness of the single-walled carbon nanotube film 120 is too large, the bonding force between the single-walled carbon nanotube film 120 and the film layer deposited on the surface of the silicon wafer 100 in the subsequent steps will be reduced, causing the film layer to easily fall off, thereby reducing the service life of the battery.

[0033] In an optional embodiment, the silicon wafer 100 is an N-type single crystal silicon wafer 100 , and the single-walled carbon nanotube is usually N-type and is more suitable for the N-type single crystal silicon wafer 100 .

[0034] In an optional embodiment, the single-walled carbon nanotube film 120 is disposed on two oppositely disposed surfaces of the silicon wafer substrate 110 .

[0035] Single-walled carbon nanotube films 120 are disposed on both sides of the silicon wafer substrate 110 . The two layers of single-walled carbon nanotube films 120 can protect the silicon wafer substrate 110 in the middle, making the silicon wafer 100 less susceptible to damage and deformation.

[0036] It should be noted that when the single-walled carbon nanotube film 120 is set on only one surface of the silicon wafer substrate 110, the strength of the silicon wafer 100 can also be improved and the deformation of the silicon wafer 100 can be reduced. However, in order to improve the photoelectric conversion efficiency while improving the strength of the silicon wafer 100, the single-walled carbon nanotube film 120 is preferably set on the front side of the single-sided battery.

[0037] In a second aspect, the present invention provides a method for preparing the silicon wafer 100 described in the aforementioned embodiment, comprising: introducing a carbon-containing gas source into a hot wire chemical vapor deposition device where the silicon wafer substrate 110 is placed to deposit single-walled carbon nanotubes to form the single-walled carbon nanotube film 120.

[0038] The single-walled carbon nanotubes are deposited on the silicon wafer substrate 110 , and the preparation process is simple, which is conducive to industrial application.

[0039] The carbon source used can be natural gas, acetylene, ethylene and other carbon source gases.

[0040] In an optional embodiment, the temperature of single-walled carbon nanotube deposition is 600-800°C and the vacuum degree is 5×10 -3 pa~5×10 -5 pa.

[0041] The temperature of the single-walled carbon nanotube deposition is 600-800° C., specifically, 600° C., 650° C., 700° C., 750° C., 800° C. or any value between 600-800° C. The temperature increase is beneficial to improving the catalytic decomposition efficiency of the carbon source, increasing the growth rate of the single-walled carbon nanotubes, and optimizing the growth morphology of the single-walled carbon nanotubes, but too high a temperature will affect the silicon wafer 100 substrate.

[0042] The vacuum degree is 5×10 -3 pa~5×10 -5 pa, specifically 5×10 -3 pa, 1×10 -3 pa, 5×10 -4 pa, 1×10 -4 pa, 5×10 -5 pa or 5×10 -3 pa~5×10 -5 The pressure will affect the concentration and diffusion rate of the carbon source, and further affect the uniformity of the single-walled carbon nanotube film formation.

[0043] Reasonable setting of temperature and vacuum degree is beneficial to optimizing the growth rate, morphology and structure of SWCNTs, improving the quality and performance of the film, and thus making the prepared silicon wafer 100 perform better in solar cells.

[0044] In an optional embodiment, the roughness of the surface of the silicon wafer substrate 110 is 0.5nm~3nm, specifically 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm or any value between 0.5nm~3nm, and the appropriate roughness is conducive to improving the bonding strength between the silicon wafer substrate 110 and the single-walled carbon nanotubes, thereby helping to improve the life of the battery using the silicon wafer 100. In some embodiments, the roughness of the surface of the silicon wafer substrate 110 can be adjusted to a desired range by adjusting the texturing step.

[0045] In an optional embodiment, the diameter of the single-walled carbon nanotube is 1 nm-3 nm, specifically, it can be 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm or any value between 1 nm and 3 nm.

[0046] On the one hand, the smaller diameter of the single-walled carbon nanotube is beneficial to improving the density of the single-walled carbon nanotube film 120. On the other hand, this size, combined with the surface roughness of the silicon wafer substrate 110, is beneficial to improving the bonding strength between the silicon wafer substrate 110 and the single-walled carbon nanotube, which in turn helps to increase the life of the battery using the silicon wafer 100.

[0047] In a fifth aspect, the present invention provides a solar cell, characterized in that it comprises the silicon wafer 100 described in any one of the aforementioned embodiments.

[0048] It should be noted that the purpose of developing the silicon wafer 100 of the present application is to solve the problem of reduced strength of the silicon wafer 100 after thinning in heterojunction cells, but in fact, the silicon wafer 100 in the present application can be applied to common solar cells on the market, such as heterojunction solar cells, backplane solar cells, etc.

[0049] In an optional embodiment, the solar cell is a heterojunction cell, which includes an amorphous silicon layer 200, a microcrystalline silicon layer 300 and an ITO layer 400 sequentially arranged on the front and back sides of the silicon wafer 100 containing the single-walled carbon nanotube film 120.

[0050] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0051] Example 1 This embodiment provides a method for preparing a heterojunction battery, comprising: Step (1), selecting an N-type single crystal silicon wafer 100 for thinning and texturing to obtain a silicon wafer substrate 110 with a thickness of 80 μm and a surface roughness of 2 nm; Step (2), passing acetylene-containing gas source into a hot wire chemical vapor deposition device in which the silicon wafer substrate 110 is placed to deposit single-walled carbon nanotubes, the deposition temperature is 700°C, the vacuum degree is 5×10 -4 pa, forming the single-walled carbon nanotube film 120 with a thickness of 5 μm and an average diameter of 2 μm on the front side of the N-type single-crystal silicon wafer 100, and then forming the single-walled carbon nanotube film 120 with a thickness of 5 μm and an average diameter of 2 μm on the back side of the N-type single-crystal silicon wafer 100, to obtain the silicon wafer 100; Step (3), sequentially preparing an amorphous silicon layer 200, a microcrystalline silicon layer 300 and an ITO layer 400 on the front and back sides of the silicon wafer 100 to obtain a heterojunction battery having a structure as shown in FIG. Figure 1 shown.

[0052] Example 2 The only difference between this embodiment and the first embodiment is that the single-walled carbon nanotube film 120 is not deposited on the back side of the N-type single crystal silicon wafer 100 .

[0053] Example 3 The only difference between this embodiment and the first embodiment is that the thickness of the single-walled carbon nanotube film 120 on the front and back surfaces of the N-type single crystal silicon wafer 100 is 10 μm.

[0054] Example 4 The only difference between this embodiment and the first embodiment is that the thickness of the single-walled carbon nanotube film 120 on the front and back surfaces of the N-type single crystal silicon wafer 100 is 1 μm.

[0055] Example 5 The only difference between this embodiment and Embodiment 1 is that the thickness of the silicon wafer substrate 110 is 120 μm.

[0056] Comparative Example 1 The difference between this comparative example and Example 1 is that step (2) is omitted, and an amorphous silicon layer 200, a microcrystalline silicon layer 300 and an ITO layer 400 are directly prepared in sequence on the front and back surfaces of the silicon wafer substrate 110 to obtain a heterojunction battery.

[0057] The mechanical strength and heterojunction cells of the silicon wafers prepared in the above-mentioned embodiments and comparative examples were tested, and the results are shown in Table 1.

[0058] Table 1

[0059] Note: When the silicon wafer is tested in Example 2, the single-walled carbon nanotube film is located below the silicon wafer substrate.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A silicon wafer, characterized in that: The invention comprises a silicon wafer substrate and a single-walled carbon nanotube film arranged on at least one surface of the silicon wafer substrate, wherein the thickness of the silicon wafer substrate is 80 μm to 120 μm.

2. The silicon wafer according to claim 1, characterized in that: The thickness of the single-walled carbon nanotube film is 1 μm to 10 μm.

3. The silicon wafer according to claim 1, characterized in that: The silicon wafer is an N-type single crystal silicon wafer.

4. The silicon wafer according to claim 1, characterized in that: The single-walled carbon nanotube film is disposed on two oppositely disposed surfaces of the silicon wafer substrate.

5. A method for preparing a silicon wafer according to any one of claims 1 to 4, characterized in that: include: A carbon-containing gas source is introduced into a hot wire chemical vapor deposition device on which the silicon wafer substrate is placed to deposit single-walled carbon nanotubes, thereby forming the single-walled carbon nanotube film.

6. The method for preparing a silicon wafer according to claim 5, characterized in that: The temperature of single-walled carbon nanotube deposition is 600-800°C and the vacuum degree is 5×10 -3 pa~5×10 -5 pa.

7. The method for preparing a silicon wafer according to claim 5, characterized in that: The roughness of the silicon wafer substrate surface is 0.5nm~3nm.

8. The method for preparing a silicon wafer according to claim 5, characterized in that: The diameter of the single-walled carbon nanotube is 1nm-3nm.

9. A solar cell, characterized in that: A silicon wafer comprising the silicon wafer described in any one of claims 1 to 4.

10. The solar cell according to claim 9, characterized in that: The solar cell is a heterojunction cell, which comprises an amorphous silicon layer, a microcrystalline silicon layer and an ITO layer which are sequentially arranged on both sides of the front and back of the silicon slice containing the single-walled carbon nanotube film.

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