Battery and photovoltaic module

Abstract

The embodiment of the invention provides a battery and a photovoltaic module. The battery comprises a substrate, the substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction, and the first surface is provided with a plurality of light trapping holes; the first grid lines and the second grid lines are alternately arranged on the substrate, the first grid lines and at least one light trapping hole have an overlapping part in the thickness direction, and the second grid lines and the light trapping holes are not overlapped in the thickness direction. In the embodiment of the invention, in the process of collecting the carriers by the first grid line and the second grid line, the collection distance of the carriers is relatively short and relatively consistent, a local electric field formed by local carrier accumulation is avoided, and the battery efficiency is improved. Moreover, the phenomenon of stress concentration of the battery can be prevented, and the fragment rate of the battery is reduced.

Description

Technical Field

[0001] The present application belongs to the field of photovoltaic manufacturing technology, and specifically relates to a battery and a photovoltaic module. Background Art

[0002] With the development of science and technology, solar energy as a new type of clean photovoltaic energy has developed rapidly in recent years, and its application scenarios have continued to diversify. In addition to centralized power stations and distributed power stations, building curtain walls, vehicle-mounted photovoltaics, and aerospace have all become areas of photovoltaic application exploration.

[0003] In the existing technology, in order to obtain a high photoelectric conversion efficiency in various installation scenarios, the surface of photovoltaic cells is usually provided with a velvet structure and large-sized light-trapping holes, wherein the velvet structure can reduce the reflection of vertically incident light, and the light-trapping holes can reduce the reflection of large-angle incident light. However, when both the velvet structure and the light-trapping holes are provided on the surface of the cell, it is easy to cause the defect of uneven cell thickness, resulting in the problem of inconsistent carrier collection distance, and it is easy to generate a local electric field formed by local carrier accumulation, which greatly reduces the efficiency of the cell. Summary of the invention

[0004] The present application aims to provide a battery and a photovoltaic module to solve the problem of low efficiency of existing batteries.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, the present application discloses a battery, comprising: a substrate, the substrate comprising a first surface and a second surface arranged in opposition to each other along a thickness direction, the first surface being provided with a plurality of light trapping holes; a first gate line and a second gate line, the first gate line and the second gate line being alternately arranged on the substrate, the first gate line having an overlapping portion with at least one of the light trapping holes along the thickness direction, and the second gate line having no overlapping portion with the light trapping holes along the thickness direction.

[0007] In an embodiment of the present application, a plurality of spaced light-trapping holes are provided on the first surface of the substrate of the battery, the first gate line and the second gate line are alternately provided on the substrate, and the first gate line has an overlapping portion with at least one of the light-trapping holes along the thickness direction, and the second gate line has no overlap with the light-trapping holes along the thickness direction. The first gate line is used to collect one type of carrier, such as holes, and the second gate line is used to collect another type of carrier, such as electrons. The first gate line and the second gate line have opposite polarities and collect different carriers. Therefore, when the first gate lines are all provided in the light-trapping hole area, the second gate lines are all provided in the non-light-trapping hole area, and the first gate lines and the second gate lines are alternately provided, for the first gate lines, the distances for hole collection are equal and uniform, and for the second gate lines, the distances for electron collection are equal and uniform, which can avoid the accumulation of carriers due to uneven carrier collection, thereby reducing the recombination of carriers and improving battery efficiency. In addition, the first gate lines and the second gate lines are alternately arranged and evenly distributed, which can also prevent the gate lines from being arranged only in the light-trapping hole area or the non-light-trapping hole area, causing stress concentration in the battery, reduce the fragmentation rate of the battery, and improve the reliability of the battery.

[0008] Optionally, the first gate line and the second gate line are both collector gate lines, the collector gate line is used to collect carriers transmitted in the substrate, and the bus gate line is used to collect current of the collector gate line. Therefore, the first gate line and the second gate line are both set as collector gate lines, so that the first gate line and the second gate line can directly collect carriers transmitted in the substrate to generate current, thereby improving the current collection efficiency.

[0009] Optionally, the battery further includes a first semiconductor layer and a second semiconductor layer; wherein the first semiconductor layer is arranged between the first gate line and the substrate, the second semiconductor layer is arranged between the second gate line and the substrate, and the conductivity type of the second semiconductor layer is opposite to the conductivity type of the substrate, that is, taking the substrate as an N-type substrate as an example, the second semiconductor layer is a P-type semiconductor layer, and the second gate line is arranged on the side of the second semiconductor layer away from the substrate, and is a P-type electrode for collecting holes. Since the carriers transmitted in the N-type substrate are mainly electrons and the minority carriers are holes, the second gate line, i.e., the P-type electrode, is used to collect the minority carriers of the N-type substrate. In addition, since most of the substrate in the light-trapping hole area is removed, the substrate in the non-light-trapping hole area is thicker, and more minority carriers are generated. Therefore, when the P-type semiconductor layer is arranged in the non-light-trapping hole area, it can be ensured that most of the minority carriers in the non-light-trapping hole area can be transmitted to the P-type semiconductor layer in the vertical direction and finally collected by the second gate line. Compared with the P-type semiconductor layer being arranged in the light-trapping hole area, the transmission path of most of the minority carriers can be shortened, the recombination of the minority carriers can be reduced, and accordingly, the power loss can be reduced.

[0010] Optionally, the area between adjacent light-trapping holes on the substrate is a non-light-trapping hole area, and the projection of the non-light-trapping hole area along the thickness direction is a first projection; wherein, when the width of the second semiconductor layer is greater than the width of the non-light-trapping hole area, the first projection is located within the projection of the second semiconductor layer along the thickness direction, so that the second semiconductor layer corresponds to the non-light-trapping hole area, so that the second semiconductor layer can collect carriers transmitted in the non-light-trapping hole area and shorten the carrier transmission path of the non-light-trapping hole area; when the width of the second semiconductor layer is less than the width of the non-light-trapping hole area, the projection of the second semiconductor layer along the thickness direction is located within the first projection, so that the area corresponding to the second semiconductor layer and the non-light-trapping hole area is as large as possible, so that the second semiconductor layer can collect carriers transmitted in the non-light-trapping hole area to the greatest extent and shorten the carrier transmission path of the non-light-trapping hole area.

[0011] In a second aspect, the present application further discloses a photovoltaic module, which comprises any one of the batteries described above.

[0012] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0014] Figure 1 is a schematic structural diagram of a battery described in an embodiment of the present application;

[0015] Figure 2 is a schematic diagram of the structure of another battery described in an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of the distribution of a grid line in a battery according to an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of another type of grid line distribution in a battery according to an embodiment of the present application;

[0018] Figure 5 is a schematic structural diagram of another battery described in an embodiment of the present application;

[0019] Figure 6 is a structural schematic diagram of another battery described in an embodiment of the present application;

[0020] Reference numerals: 1 - substrate, 11 - first surface, 12 - second surface, 2 - light trapping hole, 3 - first gate line, 4 - second gate line, 5 - first semiconductor layer, 6 - second semiconductor layer, 7 - intrinsic amorphous silicon layer, 8 - transparent conductive film layer, 9 - anti-reflection layer. DETAILED DESCRIPTION

[0021] Embodiments of the present invention will be described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The term "first" or "second" in the specification and claims of the present application may include one or more of the features explicitly or implicitly. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0023] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] The embodiment of the present application provides a battery, which may be a double-sided battery or a back-contact battery with a silicon substrate. The embodiment of the present application does not specifically limit the type of the battery.

[0026] Reference Figure 1 , showing a schematic diagram of the structure of a battery according to an embodiment of the present application, referring to Figure 2 , shows a schematic diagram of the structure of another battery described in an embodiment of the present application. Figure 1 , Figure 2 As shown, the battery may specifically include: a substrate 1, the substrate 1 may include a first surface 11 and a second surface 12 arranged in opposite directions along the thickness direction, the first surface 11 is provided with a plurality of light trapping holes 2; first gate lines 3 and second gate lines 4, the first gate lines 3 and the second gate lines 4 are alternately arranged on the substrate 1, the first gate lines 3 have an overlapping portion with at least one light trapping hole 2 along the thickness direction, and the second gate lines 4 have no overlapping portion with the light trapping hole 2 along the thickness direction.

[0027] In the embodiment of the present application, a plurality of light-trapping holes 2 are arranged at intervals on the first surface 11 of the substrate 1 of the battery, the first grid lines 3 and the second grid lines 4 are alternately arranged on the substrate 1, and the first grid lines 3 and at least one light-trapping hole 2 have overlapping parts along the thickness direction, and the projection of the second grid lines 4 does not overlap with the light-trapping hole 2 along the thickness direction. In this way, when the first grid lines 3 and the second grid lines 4 are collecting carriers, the collection distance of the carriers is short and more consistent, avoiding the local electric field formed by the accumulation of local carriers, thereby improving the battery efficiency. Moreover, it is also possible to prevent the stress concentration phenomenon in the battery and reduce the fragmentation rate of the battery.

[0028] In a specific application, the substrate 1 may be a silicon substrate, the first surface 11 may be the light-receiving surface of the substrate 1, and the second surface 12 may be the backlight surface of the substrate 1. The light-trapping hole 2 arranged on the first surface 11 may be a concave hole structure. Compared with the existing velvet structure, when the incident light enters the light-trapping hole 2, the light will be reflected multiple times in the light-trapping hole 2, and the absorption effect of the incident light is better. The velvet is a raised pyramid microstructure. When the incident light is irradiated on the velvet, the incident light is easily reflected out under the reflection effect of the pyramid, and the absorption of the incident light is poor.

[0029] Optionally, the depth of the light trap hole 2 is 10-100 microns, so that the setting of the light trap hole 2 will not affect the mechanical strength of the battery, and at the same time, can achieve a good front absorption effect. The maximum aperture of the light trap hole 2 is 10-500 microns, preferably 20-300 microns, so that the incident light can fully enter the light trap hole 2, and at the same time, it does not affect the mechanical strength of the battery. The shape of the light trap hole 2 may include but is not limited to at least one of a cylinder and a truncated cone.

[0030] For example, the depth of the light trap hole 2 along the thickness direction may be 10 microns, 20 microns, 60 microns, 75 microns or 100 microns, etc. The maximum aperture of the light trap hole 2 may be 10 microns, 50 microns, 200 microns, 350 microns or 500 microns, etc. The depth and maximum aperture of the light trap hole 2 may not be limited in the embodiment of the present application.

[0031] It should be noted that, in the embodiment of the present application, only the case where the hole wall of the light trap hole 2 is substantially parallel to the thickness direction is shown, that is, the case where the shape of the light trap hole 2 is cylindrical. In practical applications, the hole wall of the light trap hole 2 can also be set at a certain angle to the thickness direction, that is, the shape of the light trap hole 2 can also be a truncated cone or a cone, etc., and the embodiment of the present application does not specifically limit the shape of the light trap hole 2.

[0032] In the embodiment of the present application, the area outside the light-trapping hole 2 on the substrate 1 can be a non-light-trapping hole area. Since the first gate line 3 overlaps with at least one light-trapping hole 2 along the thickness direction, the second gate line 4 does not overlap with the light-trapping hole 2 along the thickness direction, that is, the second gate line 4 overlaps with the non-light-trapping hole area along the thickness direction. By setting the gate lines of the same polarity on the same type of substrate 1 area, for example, the first gate line 3 is correspondingly set in the light-trapping hole 2 area, and the second gate line 4 is correspondingly set in the non-light-trapping hole area, the probability of the carriers collected by each first gate line 3 or second gate line 4 can be made substantially equal, so that for a single first gate line 3 or second gate line 4, the current collection is more uniform. Specifically, the first gate line is used to collect one type of carrier, such as holes, and the second gate line is used to collect another type of carrier, such as electrons. The first gate line and the second gate line have opposite polarities and collect different carriers. Therefore, when the first gate lines are all set in the light-trapping hole area, the second gate lines are all set in the non-light-trapping hole area, and the first gate lines and the second gate lines are alternately set, for the first gate lines, the distance for hole collection is equal and uniform, and for the second gate lines, the distance for electron collection is equal and uniform, which can avoid the accumulation of carriers caused by uneven carrier collection, thereby reducing carrier recombination and improving battery efficiency.

[0033] Moreover, generally speaking, after a light-trapping hole 2 with a relatively deep depth is provided on the substrate 1, the strength of the substrate 1 will be affected to a certain extent, especially in the area of ​​the light-trapping hole 2, where the strength reduction is more obvious, and fracture due to stress concentration is more likely to occur. In the embodiment of the present application, by providing the first gate line 3 at the position corresponding to the light-trapping hole 2, the first gate line 3 can play a role in supporting the area of ​​the light-trapping hole 2, enhance the strength of the position, and avoid fracture at the position, so as to achieve the purpose of reducing the fragmentation rate. In addition, the first gate line and the second gate line are alternately provided and evenly distributed, which can also prevent the gate line from being provided only in the light-trapping hole area or the non-light-trapping hole area, causing stress concentration in the battery, thereby improving the reliability of the battery.

[0034] In the embodiments of the present application, Figure 3 As shown, the first gate line 3 and the second gate line 4 are both collector gate lines, so that the first gate line 3 and the second gate line 4 directly collect carriers transmitted in the substrate 1 to generate current, thereby improving the current collection efficiency.

[0035] It should be noted that, in practical applications, the first gate line 3 and the second gate line 4 may also be bus gate lines, so as to collect the current on the collector gate line through the bus gate line. Optionally, the first gate line 3 and the second gate line 4 may also be at least one of a collector gate line and a bus gate line, such as Figure 4 As shown, the first gate line 3 may be a collector gate line or a bus gate line, and the second gate line 4 may be a collector gate line or a bus gate line. The specific types of the first gate line 3 and the second gate line 4 may not be limited in the embodiment of the present application.

[0036] In some optional embodiments of the present application, such as Figure 3 , Figure 4 As shown, the multiple light trap holes 2 may include multiple columns, and each column of light trap holes 2 may include multiple light trap holes 2 distributed along the extension direction of the first grid line 3, so that the area distribution of the light trap holes on the first surface is relatively uniform, which is conducive to fully absorbing the incident light and improving the conversion efficiency; wherein, at least one first grid line 3 has an overlapping portion with each light trap hole 2 in a column of light trap holes along the thickness direction, so that the first grid line 3 can collect carriers in the corresponding area of ​​the column of light trap holes 2. Moreover, since the probability of the carriers on the column of light trap holes 2 reaching the first grid line 3 is basically equal, the current collection of the first grid line 3 can be more uniform. Specifically, the first grid line 3 and the light trap hole 2 have an overlapping portion, which may specifically include: the first grid line 3 completely overlaps the light trap hole 2, or the first grid line 3 partially overlaps the light trap hole 2 and partially is outside the light trap hole 2. wherein, when the first grid line 3 and the light trap hole 2 completely overlap, the center of the first grid line 3 completely corresponds to the center of the light trap hole 2.

[0037] It should be noted that, in a specific application, one column of light-trapping holes 2 may correspond to one or more first grid lines 3, which is not specifically limited in the present embodiment. Similarly, one or more second grid lines 4 may correspond to the non-light-trapping hole region between two adjacent columns of light-trapping holes 2, which is also not specifically limited in the present embodiment.

[0038] Optional, such as Figure 3 As shown, a grid line is set corresponding to a column of light-trapping holes 2, and a grid line is set corresponding to a non-light-trapping hole area, so that the grid lines of two polarities are evenly and alternately distributed, which is more conducive to the uniform collection of carriers;

[0039] In some optional embodiments of the present application, the center of the first grid line 3 may correspond to the center of the light-trapping hole 2. Similarly, the center of the second grid line 4 may correspond to the center of the non-light-trapping hole 2. A grid line corresponding to each column of light-trapping holes and non-light-trapping holes is located at the center, so that the grid lines are evenly distributed, which can better prevent stress concentration and further reduce the fragmentation rate.

[0040] Of course, in specific applications, such as Figure 3 As shown, the center of the first grid line 3 may not necessarily correspond to the center of the light-trapping hole 2, and the center of the second grid line 4 may not necessarily correspond to the center of the non-light-trapping hole 2, which is not specifically limited in the embodiment of the present application.

[0041] In practical applications, in order to further improve the uniformity of the gate line current collection, it is preferred that the spacing between two adjacent columns of light trap holes is equal, and in each column of light trap holes 2, the spacing between two adjacent light trap holes 2 is equal. That is, the light trap holes on the first surface have equal horizontal and vertical distances, and the light trap holes are arranged in an array on the first surface, such as Figure 4 shown.

[0042] like Figure 5 and Figure 6 As shown, the battery may further include a first semiconductor layer 5 and a second semiconductor layer 6; wherein the first semiconductor layer 5 is disposed between the first gate line 3 and the substrate 1, the second semiconductor layer 6 is disposed between the second gate line 4 and the substrate 1, and the conductivity type of the second semiconductor layer 6 is opposite to that of the substrate 1. The first semiconductor layer 5 and the second semiconductor layer 6 may both be used to collect carriers to improve the collection efficiency of carriers. The first semiconductor layer and the second semiconductor layer have opposite doping types. The first semiconductor layer 5 and the second semiconductor layer 6 may be at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon or microcrystalline silicon layers, and / or the first semiconductor layer and the second semiconductor layer may be diffusion layers.

[0043] In a specific application, the carriers transmitted in the substrate 1 may include electrons and holes. Wherein, in the case where the substrate 1 is a P-type substrate, the carriers transmitted in the substrate 1 are mainly holes, positively charged, and the minority carriers are electrons. Wherein, in the case where the substrate 1 is an N-type substrate, the carriers transmitted in the substrate 1 are mainly electrons, negatively charged, and the minority carriers are holes. The first semiconductor layer 5 may be one of a P-type semiconductor layer (mainly doped with the element boron) and an N-type semiconductor layer (mainly doped with the element phosphorus), and the second semiconductor layer 6 may be the other of the P-type semiconductor layer and the N-type semiconductor layer, and the doping types of the first semiconductor layer and the second semiconductor layer are opposite. Wherein, the P-type semiconductor layer can be used to collect holes transmitted by the silicon substrate 1, and the N-type semiconductor layer can be used to collect electrons transmitted by the silicon substrate 1. The thickness of the P-type semiconductor layer is about 50nm, and the thickness of the N-type semiconductor layer is about 40nm.

[0044] For solar cells, minority carrier lifetime is one of the important parameters for measuring the performance of solar cells. Ensuring the shortest possible transmission distance of minority carriers can reduce the recombination of minority carriers and facilitate the collection of carriers. In the embodiment of the present application, since a light-trapping hole 2 is provided on the substrate 1, most of the substrate in the light-trapping hole area is removed, and the substrate in the non-light-trapping hole area is thicker, and more minority carriers are generated. Therefore, the transmission of most minority carriers in the substrate 1 is reflected in the non-light-trapping hole area. Since the second semiconductor layer 6 and the substrate 1 have opposite polarities (for example, the substrate 1 is an N-type substrate, the second semiconductor layer 6 is a P-type semiconductor layer, or the substrate 1 is a P-type substrate, and the second semiconductor layer 6 is an N-type semiconductor layer), that is, when the substrate is an N-type substrate, the second semiconductor layer is a P-type semiconductor layer, and the second gate line is provided on the side of the second semiconductor layer away from the substrate, which is a P-type electrode for collecting holes. Since the carriers transmitted in the N-type substrate are mainly electrons and the minority carriers are holes, the second gate line, i.e., the P-type electrode, is used to collect the minority carriers of the N-type substrate. Therefore, when the P-type semiconductor layer is disposed in the non-light-trapping hole region, it can be ensured that a large number of minority carriers in the non-light-trapping hole region can be transmitted to the P-type semiconductor layer along the vertical direction and finally collected by the second gate line, that is, Figure 1 and Figure 2 If the P-type semiconductor layer is set in the light-trapping hole region, a large number of minority carriers in the non-light-trapping hole region will be transmitted in the direction shown by the solid arrow. Figure 1 and Figure 2 Transmission in the direction indicated by the dotted arrow has a longer transmission distance and is more likely to cause recombination. Therefore, compared with the P-type semiconductor layer set in the light-trapping hole area, the transmission path of most minority carriers can be shortened, the recombination of minority carriers can be reduced, and correspondingly, the power loss is reduced. Specifically, the polarity of the first gate line 3 and the second gate line 4 is opposite, that is, the first gate line 3 is a positive gate line, and the second gate line 4 is a negative gate line, or the first gate line 3 is a negative gate line and the second gate line 4 is a positive gate line. Among them, the positive gate line can be used to collect carriers collected by the P-type semiconductor layer, and the negative gate line can be used to collect carriers collected by the P-type semiconductor layer. That is, in the case where the substrate 1 is an N-type substrate 1, the second semiconductor layer 6 is a P-type semiconductor layer, the second gate line 4 is a positive gate line, the first semiconductor layer 5 is an N-type semiconductor layer, and the first gate line 3 is a negative gate line. Similarly, when the substrate 1 is a P-type substrate, the second semiconductor layer 6 is an N-type semiconductor layer, the second gate line 4 is a negative gate line, the first semiconductor layer 5 is a P-type semiconductor layer, and the first gate line 3 is an anode gate line.

[0045] like Figure 5As shown, the cell may also be provided with an intrinsic amorphous silicon layer 7 on both the front and back sides of the substrate 1. The intrinsic amorphous silicon layer 7 may be formed on the surface of the light trapping hole 2, the first surface 11 and the second surface 12 by chemical vapor deposition. The thickness of the intrinsic amorphous silicon layer 7 may be about 5 nm. The first semiconductor layer 5 and the second semiconductor layer 6 may be formed on the intrinsic amorphous silicon layer 7, respectively.

[0046] like Figure 5 and Figure 6 As shown, the battery may further include a transparent conductive film layer 8 or an anti-reflection layer 9, and the transparent conductive film layer 8 and the anti-reflection layer 9 are respectively formed on the first semiconductor layer 5 and the second semiconductor layer 6. The thickness of the transparent conductive film layer 8 is about 80nm, and the target material used for the transparent conductive film layer 8 includes but is not limited to ITO, AZO, and IWO. The thickness of the anti-reflection layer 9 may be about 100nm.

[0047] In some optional embodiments of the present application, the area between adjacent light-trapping holes 2 on the substrate 1 is a non-light-trapping hole area, the projection of the non-light-trapping hole area along the thickness direction is a first projection, and the second semiconductor layer 6 is disposed between the second gate line 4 and the substrate 1, and the second semiconductor layer corresponds to the non-light-trapping hole area; wherein, when the width of the second semiconductor layer 6 is greater than the width of the non-light-trapping hole area, the first projection is located within the projection of the second semiconductor layer 6 along the thickness direction, that is, the second semiconductor layer 6 can cover all non-light-trapping hole areas, so that the second semiconductor layer 6 can collect carriers transmitted in the non-light-trapping hole area and shorten the carrier transmission path of the non-light-trapping hole area. Alternatively, when the width of the second semiconductor layer 6 is less than the width of the non-light-trapping hole area, the projection of the second semiconductor layer 6 along the thickness direction is located within the first projection, so that the area corresponding to the second semiconductor layer 6 and the non-light-trapping hole area is as large as possible, so that the second semiconductor layer 6 can collect carriers transmitted in the non-light-trapping hole area to the greatest extent and shorten the carrier transmission path of the non-light-trapping hole area.

[0048] In some other optional embodiments of the present application, the projection of the light-trapping hole 2 region along the thickness direction is a second projection, the first semiconductor layer 5 is disposed between the first gate line 3 and the substrate 1, and the first semiconductor layer corresponds to the light-trapping hole; wherein, when the width of the first semiconductor layer 5 is greater than the width of the light-trapping hole 2, the second projection is located within the projection of the first semiconductor layer 5 along the thickness direction, that is, the first semiconductor layer 5 can correspond to cover all light-trapping hole 2 regions, so that the first semiconductor layer 5 can collect carriers transmitted in the light-trapping hole 2 region and shorten the carrier transmission path in the light-trapping hole 2 region. Alternatively, when the width of the first semiconductor layer 5 is less than the width of the light-trapping hole 2, the projection of the first semiconductor layer 5 along the thickness direction is located within the second projection, so that the area corresponding to the first semiconductor layer 5 and the light-trapping hole 2 region is as large as possible, so that the first semiconductor layer 5 can collect carriers transmitted in the light-trapping hole 2 region to the greatest extent and shorten the carrier transmission path in the light-trapping hole 2 region.

[0049] Optionally, the sum of the projection areas of the plurality of second semiconductor layers 6 along the thickness direction is greater than the sum of the projection areas of the plurality of first semiconductor layers 5 along the thickness direction. Since the second semiconductor layer 6 is disposed between the non-light-trapping area and the second gate line 4, and undertakes the main task of collecting carriers, improving the carrier collection ability of the second semiconductor layer 6 is beneficial to improving the overall current collection efficiency of the battery. In practical applications, since the carrier collection ability of the second semiconductor layer 6 is related to the projection area of ​​the second semiconductor layer 6 along the thickness direction, the larger the projection area, the stronger the carrier collection ability. Therefore, by controlling the sum of the projection areas of the plurality of second semiconductor layers 6 along the thickness direction to be greater than the sum of the projection areas of the plurality of first semiconductor layers 5 along the thickness direction, the overall current collection efficiency of the battery can be improved.

[0050] Optionally, the second semiconductor layer 6 is disposed between the second gate line 4 and the substrate 1, and the second semiconductor layer 6 is a diffusion layer, and the diffusion depth of the second semiconductor layer 6 is less than the depth of the light trapping hole 2. Since the carrier mobility of the second semiconductor layer 6 is relatively low, reducing the thickness of the second semiconductor layer 6 is beneficial to the transmission of the carriers in the battery, thereby improving the transmission efficiency of the carriers.

[0051] In some optional embodiments of the present application, the battery can be Figure 1The back contact cell shown, that is, the first grid line 3 and the second grid line 4 are both arranged on the second surface 12. Since the back contact cell arranges the first grid line 3, the second grid line 4 and the PN junction on the back of the cell, there is no electrode blocking the front, which is more conducive to the absorption of multi-angle light by the light trap, thereby improving the conversion efficiency. Moreover, since there is no metal grid line on the front, the appearance of the back contact cell is neater and more beautiful, and is particularly suitable for distributed photovoltaic scenes with high requirements for aesthetics.

[0052] In some other optional embodiments of the present application, the battery can be Figure 2 The bifacial cell shown, that is, the first grid line 3 is arranged on the second surface 12, and the second grid line 4 is arranged on the first surface 11. The bifacial cell has the characteristic of low photo-induced attenuation, which means that during long-term use, its power generation efficiency will not drop significantly like some traditional cells. And the bifacial cell performs better than traditional single-sided cells in low-light environments, and can provide more stable power output under insufficient light conditions. More importantly, both the front and back sides of the bifacial cell can receive light energy and convert it into electrical energy, thereby improving the overall power generation efficiency. Compared with traditional single-sided power generation cells, bifacial cells have a greater output power and reduce the cost per kilowatt-hour. In addition, setting the second grid line in the non-light-trapping area of ​​the first surface can make full use of the light-trapping area and further enhance the silicon substrate's absorption of multi-angle light. It should be noted that in specific applications, the battery in the embodiment of the present application can be arranged according to actual needs. Figure 1 The back contact battery shown can also be configured as Figure 2 The double-sided battery shown in the embodiment of the present application does not specifically limit the type of the battery.

[0053] In an optional embodiment of the present application, based on the fact that the crystalline silicon material responds to and absorbs light within the spectrum, the present application correlates the depth of the light-trapping hole with the thickness of the silicon substrate and the light absorption coefficient of the silicon substrate to enhance the reflection of the silicon substrate 1 to inclined incident light and increase the optical path, thereby enhancing the absorption of inclined incident light and improving the response to the spectrum.

[0054] like Figure 1 As shown, the thickness of the silicon substrate 1 is h1, the depth of the light trapping hole 2 is h2, and the difference between the thickness h1 of the silicon substrate 1 and the depth h2 of the light trapping hole 2 is △h=h1-h2≥1 / A(λ=300nm), where A is the light absorption coefficient of the silicon substrate at wavelength λ, in units of cm -1 , corresponding to different wavelengths of light, the silicon substrate 1 has different light absorption coefficients. A(λ=300nm) is the light absorption coefficient of the silicon substrate at wavelength λ=300nm. In addition, the depth h2 of the light trapping hole 2 is less than the thickness h1 of the silicon substrate 1. It can be seen that the depth h2 of the light trapping hole 2 satisfies: h2≤h1-1 / A(λ=300nm).

[0055] The thickness h1 of the silicon substrate 1 is the distance between the first surface 11 and the second surface 12 ; the depth h2 of the light trapping hole 2 is the distance between the highest point and the lowest point of the light trapping hole 2 along the thickness direction of the silicon substrate 1 .

[0056] The absorption coefficient of the silicon substrate 1 can be obtained by testing and fitting the silicon substrate 1 using an ellipsometer or a UV absorption meter. In the present application, a relationship is established between the difference between the thickness of the silicon substrate 1 and the depth of the light trapping hole 2 and the light absorption coefficient of the corresponding wavelength of the silicon substrate 1. The established relationship can be used to design the size of the light trapping hole 2 according to different incident light conditions, ensuring that the light trapping hole 2 is in the range of the best response efficiency for the incident light, thereby increasing the utilization rate of light.

[0057] Furthermore, the absorption coefficients of crystalline silicon of different types and different doping concentrations are also different. Generally, the wavelength response range of crystalline silicon cells with better response is about 600nm-850nm. In some embodiments, when 0.5×h1<1 / A(λ=x)

[0058] When 1 / A(λ=x)<0.5×h1, the difference △h between the thickness h1 of the silicon substrate 1 and the depth h2 of the light trap hole 2 satisfies: 1 / A(λ=x)≤△h≤0.5×h1. That is, the difference △h between h1 and h2 is greater than or equal to 1 / A(λ=x), and less than or equal to half of the thickness h1 of the silicon substrate 1. Wherein A(λ=x) is the light absorption coefficient of the silicon substrate 1 at wavelength x, for example, the light absorption coefficient at x=900nm, x=1000nm, x=1100nm, x=1200nm or x=1300nm, and the wavelength x can be the values ​​exemplified above, but is not limited to the above values. Therefore, the depth h2 of the light trap hole 2 satisfies: 0.5×h1≤h2≤h1-1 / A(λ=x). That is, the depth h2 of the light trap hole 2 is greater than or equal to half of the thickness h1 of the silicon substrate 1, and less than or equal to the thickness h1 of the silicon substrate minus 1 / A(λ=x). Therefore, when the depth of the light trapping hole 2 is greater than or equal to half of the thickness of the substrate 1 , the light trapping hole 2 is more conducive to the absorption of incident light.

[0059] ​By reasonably setting the range of the difference △h between h1 and h2, the light trapping hole 2 can better play the role of light trapping, thereby improving the absorption of light by the silicon substrate 1 and avoiding the existence of the light trapping hole 2 affecting the mechanical strength of the silicon substrate 1. According to the test fitting data, for crystalline silicon material, for light with a wavelength of λ = 900 nanometers, 1 / A = 2 × 10-3 cm = 20 μm. Then the difference △h between the thickness h1 of the silicon substrate 1 and the depth h2 of the light trapping hole 2 is ≥ 20 μm. For a silicon substrate with a specific thickness h1, the depth h2 of the light trapping hole 2 can be determined, h2 ≤ h1-20 μm.

[0060] In summary, the battery described in the embodiments of the present application may at least include the following advantages:

[0061] In an embodiment of the present application, a plurality of spaced light-trapping holes are provided on the first surface of the substrate of the battery, the first gate line and the second gate line are alternately provided on the substrate, and the first gate line has an overlapping portion with at least one of the light-trapping holes along the thickness direction, and the second gate line has no overlap with the light-trapping holes along the thickness direction. The first gate line is used to collect one type of carrier, such as holes, and the second gate line is used to collect another type of carrier, such as electrons. The first gate line and the second gate line have opposite polarities and collect different carriers. Therefore, when the first gate lines are all provided in the light-trapping hole area, the second gate lines are all provided in the non-light-trapping hole area, and the first gate lines and the second gate lines are alternately provided, for the first gate lines, the distances for hole collection are equal and uniform, and for the second gate lines, the distances for electron collection are equal and uniform, which can avoid the accumulation of carriers due to uneven carrier collection, thereby reducing the recombination of carriers and improving battery efficiency. In addition, the first gate lines and the second gate lines are alternately arranged and evenly distributed, which can also prevent the gate lines from being arranged only in the light-trapping hole area or the non-light-trapping hole area, causing stress concentration in the battery, reduce the fragmentation rate of the battery, and improve the reliability of the battery.

[0062] The embodiment of the present application further provides a photovoltaic assembly, which may specifically include the battery described in any of the above embodiments.

[0063] It should be noted that in the embodiments of the present application, the structure of the battery is the same as the structure of the battery described in any of the above embodiments, and its beneficial effects are also similar, which will not be described in detail here.

[0064] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0065] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A battery, characterized in that: The battery comprises: A substrate (1), the substrate (1) comprising a first surface (11) and a second surface (12) arranged opposite to each other in a thickness direction, the first surface (11) being provided with a plurality of light trapping holes (2); A first gate line (3) and a second gate line (4), wherein the first gate line (3) and the second gate line (4) are alternately arranged on the substrate (1), The first grid lines (3) and at least one of the light trap holes (2) have overlapping portions along the thickness direction, and the second grid lines (4) and the light trap holes (2) have no overlapping portions along the thickness direction.

2. The battery according to claim 1, characterized in that The first gate line (3) and the second gate line (4) are both current collecting gate lines.

3. The battery according to claim 1, characterized in that The plurality of light trap holes (2) include a plurality of columns of light trap holes, and each column of light trap holes (2) includes a plurality of light trap holes (2) distributed along the extension direction of the first grid line (3); wherein: At least one of the first grid lines (3) and each of the light trap holes (2) in a row of the light trap holes (2) have an overlapping portion along the thickness direction.

4. The battery according to claim 1, characterized in that The battery further comprises a first semiconductor layer (5) and a second semiconductor layer (6); wherein, The first semiconductor layer (5) is arranged between the first gate line (3) and the substrate (1), the second semiconductor layer (6) is arranged between the second gate line (4) and the substrate (1), and the conductivity type of the second semiconductor layer (6) is opposite to the conductivity type of the substrate (1).

5. The battery according to claim 1 or 4, characterized in that: The first gate line (3) and the second gate line (4) are both located on the second surface (12).

6. The battery according to claim 5, characterized in that The area between the adjacent light-trapping holes (2) on the substrate (1) is a non-light-trapping hole area, and the projection of the non-light-trapping hole area along the thickness direction is a first projection. The second semiconductor layer (6) is arranged between the second gate line (4) and the substrate (1), and the second semiconductor layer corresponds to the non-light-trapping hole area; wherein: When the width of the second semiconductor layer (6) is greater than the width of the non-light-trapping hole region, the first projection is located within the projection of the second semiconductor layer (6) along the thickness direction; When the width of the second semiconductor layer (6) is smaller than the width of the non-light-trapping hole region, the projection of the second semiconductor layer (6) along the thickness direction is located within the first projection.

7. The battery according to claim 5, characterized in that The projection of the light trap hole along the thickness direction is a second projection, the first semiconductor layer (5) is arranged between the first gate line (3) and the substrate (1), and the first semiconductor layer corresponds to the light trap hole; wherein, when the width of the first semiconductor layer (5) is greater than the width of the light trap hole (2), the second projection is located within the projection of the first semiconductor layer (5) along the thickness direction; When the width of the first semiconductor layer (5) is smaller than the width of the light trapping hole (2), the projection of the first semiconductor layer (5) along the thickness direction is located within the second projection.

8. The battery according to claim 5, characterized in that The battery further comprises a first semiconductor layer (5) and a second semiconductor layer (6), wherein the first semiconductor layer (5) is arranged between the first gate line (3) and the substrate (1), and the second semiconductor layer (6) is arranged between the second gate line (4) and the substrate (1); wherein: The sum of the areas of the plurality of second semiconductor layers (6) is greater than the sum of the areas of the plurality of first semiconductor layers (5).

9. The battery according to claim 1 or 4, characterized in that: The second gate line (4) is arranged on the first surface (11), and the first gate line (3) is arranged on the second surface (12).

10. The battery according to claim 9, characterized in that The second semiconductor layer (6) is arranged between the second gate line (4) and the substrate (1), the second semiconductor layer is a diffusion layer, and the diffusion depth of the second semiconductor layer (6) is smaller than the depth of the light trap hole (2).

11. The battery according to claim 1, characterized in that The thickness of the substrate (1) is h1, the depth of the light trapping hole (2) is h2, wherein the difference △h between h1 and h2 satisfies h1>△h≥1 / A, wherein A is the light absorption coefficient of the substrate at a wavelength λ=300nm, in units of cm －1 .

12. The battery according to claim 1, characterized in that The depth of the light trap hole is greater than or equal to half of the thickness of the substrate.

13. The battery according to claim 1, characterized in that The depth of the light trapping hole (2) is 10-100 microns; And / or, the maximum aperture of the light trapping hole (2) is 10-500 micrometers; And / or, the shape of the light trapping hole (2) includes at least one of a cylinder, a truncated cone, and a square column.

14. A photovoltaic module, characterized in that: The photovoltaic module comprises: the battery according to any one of claims 1 to 13.

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