Display panel and display device

Abstract

The invention discloses a display panel and a display device. In the display panel, a first pixel circuit comprises a first driving transistor and a first double-gate transistor, and the first double-gate transistor is connected with a grid electrode of the first driving transistor; the second pixel circuit comprises a second driving transistor and a second double-gate transistor, and the second double-gate transistor is connected with the grid electrode of the second driving transistor; a first transistor and a second transistor of the first double-gate transistor are connected to a first node, and the first node is connected with one end of a first capacitor; a third transistor and a fourth transistor of the second double-gate transistor are connected to a second node, and the second node is connected with one end of a second capacitor; the overlapping area of the two polar plates of the first capacitor is different from the overlapping area of the two polar plates of the second capacitor. According to the embodiment of the invention, the color cast problem of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] The display panel includes a plurality of pixel circuits arranged in a matrix. The pixel circuits are provided with driving transistors and other switching transistors. Based on the mutual cooperation of the plurality of transistors, the pixel circuits transmit driving current to the light-emitting elements to drive the light-emitting elements to emit light.

[0004] However, due to the influence of the gate node leakage current of the driving transistor, the brightness of the light-emitting element deviates. If the leakage currents in sub-pixels of different colors are inconsistent, the display panel may have a color deviation problem. Summary of the invention

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the color cast problem of the display panel.

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising: sub-pixels, the sub-pixels comprising a first sub-pixel and a second sub-pixel, the first sub-pixel comprising a first pixel circuit and a first light-emitting element connected to each other, the second sub-pixel comprising a second pixel circuit and a second light-emitting element connected to each other, and the light-emitting colors of the first light-emitting element and the second light-emitting element are different; the first pixel circuit comprises a first driving transistor and a first dual-gate transistor, and the first dual-gate transistor is connected to the gate of the first driving transistor; the second pixel circuit comprises a second driving transistor and a second dual-gate transistor, and the second dual-gate transistor is connected to the gate of the second driving transistor; the first dual-gate transistor comprises a first transistor and a second transistor, and the first transistor and the second transistor are connected to a first node, and the first node is connected to one end of a first capacitor; the second dual-gate transistor comprises a third transistor and a fourth transistor, and the third transistor and the fourth transistor are connected to a second node, and the second node is connected to one end of a second capacitor; in a direction perpendicular to the plane where the display panel is located, the overlapping area of ​​the two plates of the first capacitor is different from the overlapping area of ​​the two plates of the second capacitor.

[0007] In a second aspect, an embodiment of the present application further provides a display device, comprising a display panel as described in the embodiment of the first aspect.

[0008] According to the display panel and the display device provided by the embodiments of the present application, the overlapping area of ​​the two plates of the first capacitor is different from the overlapping area of ​​the two plates of the second capacitor, so that the potential control ability of the first capacitor over the first node is different from the potential control ability of the second capacitor over the second node, so that the potential difference between the first node and the second node can flexibly match the potential difference between the gate of the first driving transistor and the gate of the second driving transistor, thereby creating a feasible condition for the potential difference between the gate of the first driving transistor and the first node and the potential difference between the gate of the second driving transistor and the second node to tend to be consistent, which can help solve the color deviation problem.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0011] Figure 1 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present application is shown;

[0012] Figure 2 A schematic diagram showing a topological structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0013] Figure 3 Show Figure 2 A corresponding timing diagram;

[0014] Figure 4 A schematic diagram showing a layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0015] Figure 5 Show Figure 4 An enlarged schematic diagram of the local structure in the middle Q1 region;

[0016] Figure 6 Another schematic diagram showing a layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0017] Figure 7 Show Figure 6 An enlarged schematic diagram of the local structure in the middle Q2 region;

[0018] Figure 8 A schematic diagram showing another layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0019] Fig. 9 Show Figure 8 An enlarged schematic diagram of the local structure in the middle Q31 region;

[0020] Fig.10 Show Figure 8 An enlarged schematic diagram of the local structure in the middle Q32 region;

[0021] Fig.11 A schematic diagram showing another layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0022] Fig.12 Show Fig.11 An enlarged schematic diagram of the local structure in the middle Q41 region;

[0023] Fig.13 Show Fig.11 An enlarged schematic diagram of the local structure in the middle Q42 region;

[0024] Fig.14 A schematic diagram showing another layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0025] Fig.15 Another schematic diagram of a topological structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0026] Fig.16 A schematic diagram showing another layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0027] Fig.17 Show Fig.16 An enlarged schematic diagram of the local structure in the middle Q5 region;

[0028] Fig.18 A schematic diagram showing another layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0029] Fig.19 Show Fig.18 An enlarged schematic diagram of the local structure in the middle Q6 region;

[0030] Fig. 20 A schematic diagram showing another topological structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0031] Fig.21 A schematic diagram showing another topological structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0032] Fig. 22 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0034] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0035] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0036] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0037] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0038] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0039] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0040] With the development of display technology, the functions of display panels are becoming more and more diverse. For example, display panels support low-frequency display. However, in low-frequency display mode, the display panel is prone to color deviation. Especially when the temperature rises or the ambient light increases, the color deviation problem will be more serious. For example, the display panel has the problem that the white screen is not white.

[0041] The display panel usually includes sub-pixels of multiple luminous colors. The sub-pixels of various luminous colors include pixel circuits and light-emitting elements. The pixel circuit includes a driving transistor. A data voltage is written into the gate of the driving transistor. The driving transistor generates a certain driving current according to the written data voltage to drive the light-emitting element to emit light.

[0042] Through research, the inventors found that the reasons for color deviation include: sub-pixels of different luminous colors have different luminous characteristics. When displaying a white screen, the driving currents required for sub-pixels of different luminous colors are different, and the data voltages written into the gates of the driving transistors in the sub-pixels of different luminous colors are different, resulting in different leakage levels of the gates of the driving transistors in the sub-pixels of different luminous colors, thus causing color deviation problems.

[0043] In order to solve the above problems, the embodiments of the present application provide a display panel and a display device. The embodiments of the display panel and the display device will be described below in conjunction with the accompanying drawings.

[0044] Please refer to Figure 1 and Figure 2The display panel 100 includes sub-pixels, and the sub-pixels include a first sub-pixel 1 and a second sub-pixel 2. The first sub-pixel 1 includes a first pixel circuit 10 and a first light-emitting element D1 connected to each other, and the second sub-pixel 2 includes a second pixel circuit 20 and a second light-emitting element D2 connected to each other. The light-emitting colors of the first light-emitting element D1 and the second light-emitting element D2 are different.

[0045] The first pixel circuit 10 includes a first driving transistor M3 and a first double-gate transistor 11. The first double-gate transistor 11 is connected to the gate of the first driving transistor M3. Figure 2 In the example, the gates of the first dual-gate transistor 11 and the first driving transistor M3 are connected to the node N11.

[0046] The first dual-gate transistor 111 includes a first transistor 111 and a second transistor 112 . The first transistor 111 and the second transistor 112 are connected to a first node N01 . The first node N01 is connected to one end of the first capacitor C1 .

[0047] The second pixel circuit 20 includes a second driving transistor T3 and a second dual-gate transistor 22. The second dual-gate transistor 22 is connected to the gate of the second driving transistor T3. Figure 2 In the example, the gates of the second dual-gate transistor 22 and the second driving transistor T3 are connected to N12.

[0048] The second dual-gate transistor 22 includes a third transistor 223 and a fourth transistor 224 . The third transistor 223 and the fourth transistor 224 are connected to a second node N02 . The second node N02 is connected to one end of the second capacitor C2 .

[0049] In a direction perpendicular to the plane where the display panel is located, the overlapping area of ​​the two plates of the first capacitor C1 is different from the overlapping area of ​​the two plates of the second capacitor C2. The overlapping area of ​​the two plates of the capacitor determines the capacitance of the capacitor. The capacitance of the first capacitor C1 is different from the capacitance of the second capacitor C2. Exemplarily, the lower plate of the first capacitor C1 and the lower plate of the second capacitor C2 are in the same film layer, and the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 are in the same film layer.

[0050] Exemplarily, the circuit topology of the first pixel circuit and the second pixel circuit is the same. The first dual-gate transistor and the second dual-gate transistor can be understood as transistors with equivalent connection positions in the two pixel circuits. For example, the pixel circuit includes a reset transistor and a threshold compensation transistor connected to the driving transistor, the reset transistor is used to reset the gate of the driving transistor, and the threshold compensation transistor is used to perform threshold compensation on the driving transistor. The first dual-gate transistor and the second dual-gate transistor may include the reset transistor in the first pixel circuit and the second pixel circuit, and / or the first dual-gate transistor and the second dual-gate transistor may include the threshold compensation transistor in the first pixel circuit and the second pixel circuit.

[0051] For example, Figure 3 As shown, the operation process of the pixel circuit may include a first stage t1, a second stage t2 and a light-emitting stage t3, wherein the first stage t1 and the second stage t2 are non-light-emitting stages. In the first stage t1, the reset signal on the reset signal line Vref is written into the gates of the first drive transistor M3 and the second drive transistor T3. In the second stage t2, the data signal on the data signal line data is written into the gates of the first drive transistor M3 and the second drive transistor T3, respectively, and the threshold voltages of the first drive transistor M3 and the second drive transistor T3 are compensated, respectively. In the light-emitting stage t3, the first light-emitting element D1 and the second light-emitting element D2 emit light.

[0052] It should be noted that Figure 2 The circuit topology of the first pixel circuit and the second pixel circuit shown in FIG. Figure 3 The timings shown are just some examples and are not intended to limit the present application.

[0053] For the first pixel circuit, the gate of the first driving transistor M3 and the first dual-gate transistor 11 are connected to the node N11, the first transistor and the second transistor of the first dual-gate transistor 11 are connected to the first node N01, and the potential of the first node N01 is pulled up by the coupling of the scanning signal line S1(i) or the scanning signal line S2(i), so that there is a leakage current between the node N11 and the first node N01.

[0054] For the second pixel circuit, the gate of the second driving transistor T3 and the second dual-gate transistor 22 are connected to the node N12, the third transistor and the fourth transistor of the second dual-gate transistor 22 are connected to the second node N02, and the potential of the second node N02 is also pulled up by the coupling of the scanning signal line S1(i) or the scanning signal line S2(i), so that there is a leakage current between the node N12 and the second node N02.

[0055] Sub-pixels of different luminous colors have different luminous characteristics. When displaying a white screen, sub-pixels of different luminous colors require different driving currents, and the data voltages written into the gates of driving transistors in sub-pixels of different luminous colors are different. In other words, the potentials of node N11 and node N12 are different. If the potentials of the first node N01 and the second node N02 remain the same, the leakage currents of node N11 and node N12 will be different. For example, the leakage current speed of one of node N11 and node N12 will be faster, resulting in color deviation of the displayed white screen.

[0056] According to the display panel provided in the embodiment of the present application, the first sub-pixel and the second sub-pixel with different luminous colors are differentiated. Specifically, the overlapping area of ​​the two plates of the first capacitor and the overlapping area of ​​the two plates of the second capacitor are different, so that the potential control ability of the first capacitor over the first node is different from the potential control ability of the second capacitor over the second node, so that the potential difference between the first node and the second node can flexibly match the potential difference between the gate of the first driving transistor and the gate of the second driving transistor, creating a feasible condition for the potential difference between the gate of the first driving transistor and the first node and the potential difference between the gate of the second driving transistor and the second node to be consistent, which can help solve the color deviation problem.

[0057] Exemplarily, the other end of the first capacitor C1 is connected to the fixed voltage signal line, and the other end of the second capacitor C2 is also connected to the fixed voltage signal line. For example, the other end of the first capacitor C1 and the other end of the second capacitor C2 are connected to the first power line PVDD, and the first power line PVDD is used to provide a fixed voltage source to the pixel circuit. The other end of the first capacitor C1 and the other end of the second capacitor C2 are connected to the reset signal line Vref, and the reset signal line Vref is used to provide a reset signal to the pixel circuit. In this example, the first capacitor C1 is used to maintain the potential stability of the first node, and the second capacitor C2 is used to maintain the potential stability of the second node.

[0058] As an example, Figure 2 As shown, the first electrode of the first driving transistor M3 and the first electrode of the second driving transistor T3 are connected to the first power line PVDD, the first dual-gate transistor 11 includes a first threshold compensation transistor M5, and the first threshold compensation transistor M5 is connected between the gate of the first driving transistor M3 and the second electrode of the first driving transistor, and the second dual-gate transistor 22 includes a second threshold compensation transistor T5, and the second threshold compensation transistor T5 is connected between the gate of the second driving transistor T3 and its second electrode.

[0059] The first capacitor C1 includes a first sub-capacitor C11, and the first sub-capacitor C11 is connected to the connection node (node ​​N61) of the two transistors in the first threshold compensation transistor M5. The second capacitor C2 includes a second sub-capacitor C22, and the second sub-capacitor C22 is connected to the connection node (node ​​N62) of the two transistors in the second threshold compensation transistor T5. The overlapping area of ​​the two plates of the first sub-capacitor C11 is different from the overlapping area of ​​the two plates of the second sub-capacitor C22.

[0060] As another example, the first dual-gate transistor 11 includes a first reset transistor M4, which is connected between the gate of the first driving transistor M3 and the reset signal line Vref, and the second dual-gate transistor 22 includes a second reset transistor T4, which is connected between the gate of the second driving transistor T3 and the reset signal line Vref.

[0061] The first capacitor C1 includes a third sub-capacitor C13, and the third sub-capacitor C13 is connected to the connection node (node ​​N51) of the two transistors in the first reset transistor M4. The second capacitor C2 includes a fourth sub-capacitor C24, and the fourth sub-capacitor C24 is connected to the connection node (node ​​N52) of the two transistors in the second reset transistor T4. The overlapping area of ​​the two plates of the third sub-capacitor C13 is different from the overlapping area of ​​the two plates of the fourth sub-capacitor C24.

[0062] Exemplarily, the overlapping area of ​​the two plates of the first sub-capacitor C11 is different from the overlapping area of ​​the two plates of the second sub-capacitor C22, and / or the overlapping area of ​​the two plates of the third sub-capacitor C13 is different from the overlapping area of ​​the two plates of the fourth sub-capacitor C24.

[0063] Exemplarily, the display panel includes red sub-pixels, green sub-pixels and blue sub-pixels, the light-emitting element of the red sub-pixel emits red light, the light-emitting element of the green sub-pixel emits green light, and the light-emitting element of the blue sub-pixel emits blue light.

[0064] In some embodiments, the first light emitting element emits blue light, the second light emitting element emits red light or green light, and the overlapping area of ​​the two plates of the first capacitor is greater than the overlapping area of ​​the two plates of the second capacitor.

[0065] The inventors have found that when displaying a white image, the blue sub-pixel requires the largest driving current. For a P-type driving transistor, the gate potential of the driving transistor in the blue sub-pixel is the lowest, usually 0.1V to 0.6V lower than the gate potential of the driving transistor in the red sub-pixel or the green sub-pixel. The lower the gate potential of the driving transistor, the faster the leakage current of the driving transistor, resulting in a decrease in the luminous brightness of the blue sub-pixel, which leads to color shift, such as a reddish phenomenon.

[0066] Both the first node and the second node will be pulled up due to the coupling of the scanning signal lines S1(i) and S2(i). In this embodiment, when both the first capacitor and the second capacitor are used to maintain potential stability, since the overlapping area of ​​the two plates of the first capacitor in the blue sub-pixel is larger, the first capacitor has a stronger ability to maintain the potential of the first node, so that the potential of the first node in the blue sub-pixel after being coupled and pulled up is lower than the potential of the second node in the red / green sub-pixel after being coupled and pulled up, so that the difference between the first node in the blue sub-pixel and the gate potential of the first driving transistor is close to the difference between the second node and the gate potential of the second driving transistor in the red / green sub-pixel, so that the gate leakage current of the first driving transistor in the blue sub-pixel and the gate leakage current of the second driving transistor in the red / green sub-pixel tend to be consistent, thereby improving the red cast phenomenon.

[0067] In the following examples, the driving current required by the blue sub-pixel is the largest when a white image is displayed, that is, the first light-emitting element emits blue light and the second light-emitting element emits red light or green light, to illustrate the size relationship between the parameters of the first sub-pixel and the second sub-pixel.

[0068] Exemplarily, the overlapping area of ​​the two plates of the first sub-capacitor C11 is greater than the overlapping area of ​​the two plates of the second sub-capacitor C22, and / or the overlapping area of ​​the two plates of the third sub-capacitor C13 is greater than the overlapping area of ​​the two plates of the fourth sub-capacitor C24.

[0069] Exemplarily, the first sub-capacitor C11, the second sub-capacitor C22, the third sub-capacitor C13, and the fourth sub-capacitor C24 are all used to maintain potential stability.

[0070] In the first sub-capacitor C11 and the second sub-capacitor C22, since the overlapping area of ​​the two plates of the first sub-capacitor C11 is larger, the first sub-capacitor C11 has a stronger ability to maintain the potential of the node N61, and the potential of the node N61 after being coupled and pulled up by the scanning signal line S2(i) is lower than the potential of the node N62 after being coupled and pulled up by the scanning signal line S2(i), and the potential of the node N11 is lower than the potential of the node N12, and finally the potential difference between the node N61 and the node N11 can be made close to the potential difference between the node N62 and the node N12, thereby balancing the leakage current between the driving transistor and the threshold compensation transistor in the first sub-pixel and the second sub-pixel.

[0071] In the third sub-capacitor C13 and the fourth sub-capacitor C24, since the overlapping area of ​​the two plates of the third sub-capacitor C13 is larger, the third sub-capacitor C13 has a stronger ability to maintain the potential of the node N51. The potential of the node N51 after being coupled and pulled up by the scanning signal line S1(i) is lower than the potential of the node N52 after being coupled and pulled up by the scanning signal line S1(i), and the potential of the node N11 is lower than the potential of the node N12. Finally, the potential difference between the node N51 and the node N11 can be close to the potential difference between the node N52 and the node N12, thereby balancing the leakage current between the driving transistor and the reset transistor in the first sub-pixel and the second sub-pixel.

[0072] In some embodiments, Figure 2 As shown, the first transistor 111 is connected between the gate of the first driving transistor M3 and the second transistor 112, and the third transistor 223 is connected between the gate of the second driving transistor T3 and the fourth transistor 224. The channel area of ​​the first transistor 111 is smaller than the channel area of ​​the third transistor 223.

[0073] The transistor includes an active layer and a gate. The active layer includes a channel and a source region and a drain region. In a direction perpendicular to the plane where the display panel is located, the channel overlaps with the gate of the transistor, and the source region and the drain region do not overlap with the gate of the transistor. The channel area of ​​the transistor is the product of the length of the channel of the transistor and the width of the channel. In other words, the channel area can be considered as the positive projection area of ​​the channel on the plane where the display panel is located.

[0074] The gate of the first transistor 111 and the gate of the third transistor 223 are connected to the scanning signal line S1(i) or the scanning signal line S2(i). The channel area of ​​the first transistor 111 is smaller, so that the degree of coupling of the first transistor to the scanning signal line is smaller, so that the potential of the first node N01 after being pulled up by the scanning signal line is lower than the potential of the second node N02 after being pulled up by the scanning signal line, and the potential of the node N11 is lower than the potential of the node N12, so that the difference between the first node and the gate potential of the first driving transistor in the first sub-pixel is close to the difference between the second node and the gate potential of the second driving transistor in the second sub-pixel, so that the gate leakage current of the first driving transistor in the blue sub-pixel and the gate leakage current of the second driving transistor in the red / green sub-pixel tend to be consistent.

[0075] For example, Figure 2 As shown, the first transistor 111 includes a transistor M4_1 and a transistor M5_1, the second transistor 112 includes a transistor M4_2 and a transistor M5_2, the third transistor 223 includes a transistor T4_1 and a transistor T5_1, and the fourth transistor 224 includes a transistor T4_2 and a transistor T5_2.

[0076] The channel area of ​​the transistor M4_1 is smaller than the channel area of ​​the transistor T4_1 , and / or the channel area of ​​the transistor M5_1 is smaller than the channel area of ​​the transistor T5_1 .

[0077] In some embodiments, Figure 2 As shown, the first transistor 111 is connected between the gate of the first driving transistor M3 and the second transistor 112, and the third transistor 223 is connected between the gate of the second driving transistor T3 and the fourth transistor 224. The channel length of the second transistor 112 is less than the channel length of the fourth transistor 224.

[0078] For example, the other ends of the second transistor 112 and the fourth transistor 224 are connected to the reset signal line Vref, and the reset signal line Vref leaks to the node N51 through the second transistor 112, and the reset signal line Vref leaks to the node N52 through the fourth transistor 224. The channel length of the second transistor 112 is smaller, and the leakage path between the reset signal line Vref and the node N51 is shorter, so that the leakage speed between the reset signal line Vref and the node N51 is faster, so that the potential of the node N51 is lower than the potential of the node N52, and the potential of the node N11 is lower than the potential of the node N12, so that the potential difference between the node N51 and the node N11 and the potential difference between the node N52 and the node N12 are relatively close, thereby reducing the leakage current of the gates of the first sub-pixel and the second sub-pixel.

[0079] Exemplarily, the channel length of the transistor M4_2 is smaller than the channel length of the transistor T4_2 , and / or the channel length of the transistor M5_2 is smaller than the channel length of the transistor T5_2 .

[0080] In some embodiments, Figure 2 As shown, the first transistor 111 is connected between the gate of the first driving transistor M3 and the second transistor 112, and the third transistor 223 is connected between the gate of the second driving transistor T3 and the fourth transistor 224. The channel area of ​​the first transistor 111 is smaller than that of the second transistor 112.

[0081] Exemplarily, a channel area of ​​the transistor M4_1 is smaller than a channel area of ​​the transistor M4_2 , and / or a channel area of ​​the transistor M5_1 is smaller than a channel area of ​​the transistor M5_2 .

[0082] Taking transistor M4_1 and transistor M4_2 as examples, the channel area of ​​transistor M4_1 is relatively small, the smaller the coupling between transistor M4_1 and the scanning signal line S1(i), the smaller the turn-off current of transistor M4_1, and in the process of the scanning signal line S1(i) switching from a low level to a high level, a current flows from node N51 to node N11, thereby making the potential of node N51 lower, so that the potential difference between node N51 and node N11 and the potential difference between node N52 and node N12 are relatively close, thereby reducing the leakage current of the gates of the first sub-pixel and the second sub-pixel.

[0083] Similarly, the channel area of ​​transistor M5_1 is smaller, the coupling between transistor M5_1 and the scanning signal line S2(i) is smaller, and the turn-off current of transistor M5_1 is smaller. In the process of the scanning signal line S2(i) switching from a low level to a high level, a current flows from node N61 to node N11, thereby making the potential of node N61 lower, so that the potential difference between node N61 and node N11 and the potential difference between node N62 and node N12 are closer, thereby reducing the leakage current of the gate of the first sub-pixel and the second sub-pixel.

[0084] In some embodiments, please refer to Figure 2 , Figure 4 and Figure 5 The first transistor 111 and the second transistor 112 are connected through the first connection structure 31a, the third transistor 223 and the fourth transistor 224 are connected through the second connection structure 32b, and the display panel further includes a first conductive portion 41a and a second conductive portion 42b, and the first conductive portion 41a and the second conductive portion 42b receive a fixed voltage signal. For example, the fixed voltage signal includes a signal transmitted by the first power line PVDD or a signal transmitted by the reset signal line Vref.

[0085] The first connection structure 31a and the first conductive portion 41a at least partially overlap in the thickness direction of the display panel to form a first capacitor C1, and the second connection structure 32b and the second conductive portion 42b at least partially overlap in the thickness direction of the display panel to form a second capacitor C2.

[0086] Exemplarily, the first connection structure 31a, the active layer of the first transistor 111, and the active layer of the second transistor 112 are located in the same film layer, and the material of the first connection structure 31a includes a semiconductor material. The second connection structure 32b, the active layer of the third transistor 223, and the active layer of the fourth transistor 224 are located in the same film layer, and the material of the second connection structure 32b includes a semiconductor material.

[0087] Exemplarily, the first connection structure 31 a and the second connection structure 32 b are located in the same film layer, and the first conductive portion 41 a and the second conductive portion 42 b are located in another film layer.

[0088] Exemplarily, the differentiated design of the first connection structure 31a and the second connection structure 32b, and / or the differentiated design of the first conductive portion 41a and the second conductive portion 42b can make the overlapping area of ​​the two plates of the first capacitor C1 different from the overlapping area of ​​the two plates of the second capacitor C2.

[0089] As an example, please refer to Figure 4 and Figure 5 The first connection structure 31a includes a first sub-portion 311, and the first sub-portion 311 overlaps with the first conductive portion 41a in the thickness direction of the display panel. It can be understood that the first sub-portion 311 is a portion of the first connection structure 31a that overlaps with the first conductive portion 41a, and the portion of the first connection structure 31a other than the first sub-portion 311 does not overlap with the first conductive portion 41a in the thickness direction of the display panel.

[0090] The second connection structure 32b includes a second sub-portion 322, and the second sub-portion 322 overlaps with the second conductive portion 42b in the thickness direction of the display panel. It can be understood that the second sub-portion 322 is a portion of the second connection structure 32b that overlaps with the second conductive portion 42b, and the portion of the second conductive portion 42b other than the second sub-portion 322 does not overlap with the second conductive portion 42b in the thickness direction of the display panel.

[0091] The area of ​​the first sub-portion 311 is greater than the area of ​​the second sub-portion 322 .

[0092] In this embodiment, by differentially designing the first connection structure 31 a and the second connection structure 32 b , the overlapping area of ​​the two plates of the first capacitor C1 is different from the overlapping area of ​​the two plates of the second capacitor C2 .

[0093] As another example, refer to Figure 6 and Figure 7 The first conductive portion 41a includes a third sub-portion ref1, and the third sub-portion ref1 overlaps with the first connection structure 31a in the thickness direction of the display panel. It can be understood that the third sub-portion ref1 is a portion of the first conductive portion 41a that overlaps with the first connection structure 31a, and the portion of the first conductive portion 41a other than the third sub-portion ref1 does not overlap with the first connection structure 31a in the thickness direction of the display panel.

[0094] The second conductive portion 42b includes a fourth sub-portion ref2, and the fourth sub-portion ref2 overlaps with the second connection structure 32b in the thickness direction of the display panel. It can be understood that the fourth sub-portion ref2 is a portion of the second conductive portion 42b that overlaps with the second connection structure 32b, and the portion of the second conductive portion 42b other than the fourth sub-portion ref2 does not overlap with the second connection structure 32b in the thickness direction of the display panel.

[0095] The area of ​​the third sub-portion ref1 is greater than the area of ​​the fourth sub-portion ref2.

[0096] In this embodiment, by differentially designing the first conductive portion 41 a and the second conductive portion 42 b , the overlapping area of ​​the two plates of the first capacitor C1 is different from the overlapping area of ​​the two plates of the second capacitor C2 .

[0097] In some embodiments, please refer to Figure 2 , Figure 4 and Figure 5 , the first electrode of the first driving transistor M3 and the first electrode of the second driving transistor T3 are connected to the first power line PVDD, the first dual-gate transistor 11 includes a first threshold compensation transistor M5, the first threshold compensation transistor M5 is connected between the gate of the first driving transistor M3 and the second electrode of the first driving transistor, the second dual-gate transistor 22 includes a second threshold compensation transistor T5, the second threshold compensation transistor T5 is connected between the gate of the second driving transistor T3 and the second electrode. The first capacitor C1 includes a first sub-capacitor C11, and the second capacitor C2 includes a second sub-capacitor C22. The first connecting portion 31a includes a first wiring structure 31, the second connecting portion 32b includes a second wiring structure 32, the first conductive portion 41a includes a first shielding structure 41, and the second conductive portion 42b includes a second shielding structure 42. The first transistor 111 (i.e., transistor M5_1) and the second transistor 112 (i.e., transistor M5_2) in the first threshold compensation transistor M5 are connected through the first wiring structure 31, and the first shielding structure 41 and the first wiring structure 31 at least partially overlap in the thickness direction of the display panel to form a first sub-capacitor C11. The third transistor 223 (i.e., transistor T5_1) and the fourth transistor 224 (i.e., transistor T5_2) in the second threshold compensation transistor T5 are connected through the second wiring structure 32, and the second shielding structure 42 and the second wiring structure 32 at least partially overlap in the thickness direction of the display panel to form a second sub-capacitor C22. In addition, the first shielding structure 41 and the second shielding structure 42 are connected to the first power line PVDD.

[0098] In the layout structure of this article, the structure filled with the same pattern represents the structure located in the same film layer, and the structure filled with different patterns represents the structure located in different film layers. Exemplarily, the display panel includes a semiconductor layer B and a first metal layer M11, a capacitor metal layer MC and a second metal layer M12 which are sequentially arranged away from the semiconductor layer B. An insulating layer is included between the semiconductor layer and the metal layer and between different metal layers. The semiconductor layer B includes an active layer of each transistor, the first metal layer M11 includes scanning signal lines S1(i), S2(i) and the gate of the transistor, the capacitor metal layer MC includes the upper plate of the storage capacitor, the reset signal line Vref, and the second metal layer M12 includes a first power line PVDD and a data signal line data. It is understandable that the material of the semiconductor layer includes semiconductors, and the material of the metal layer includes metals. For example, the material of the semiconductor layer B includes polysilicon (poly).

[0099] Exemplarily, the first wiring structure 31 and the second wiring structure 32 are located in the semiconductor layer 01. The first shielding structure 41 and the second shielding structure 42 are located in the capacitor metal layer MC.

[0100] The overlapping portion of the first shielding structure 41 and the first wiring structure 31 can be used as two plates of the first sub-capacitor C11 , and the overlapping portion of the second shielding structure 42 and the second wiring structure 32 can be used as two plates of the second sub-capacitor C22 .

[0101] Exemplarily, the first shielding structure 41 and the second shielding structure 42 can shield light to reduce the influence of light on transistor characteristics.

[0102] Exemplarily, the first power line PVDD is used to transmit a fixed voltage, and the first shielding structure 41 and the second shielding structure 42 are connected to the first power line PVDD, so that the first sub-capacitor C11 can be used to stabilize the potential of the node N61, and the second sub-capacitor C22 can be used to stabilize the potential of the node N62.

[0103] In some embodiments, please refer to Figure 4 and Figure 5 The first wiring structure 31 includes a first sub-portion 311, and the first sub-portion 311 overlaps with the first shielding structure 41 in the thickness direction of the display panel. The second wiring structure 32 includes a second sub-portion 322, and the second sub-portion 322 overlaps with the second shielding structure 42 in the thickness direction of the display panel; the area of ​​the first sub-portion 311 is larger than the area of ​​the second sub-portion 322.

[0104] It should be noted that in order to clearly illustrate the first sub-capacitor and the second sub-capacitor, Figure 5 The structure of the second metal layer M2 is hidden.

[0105] As an example, the first routing structure 31 includes a first corner portion, a portion extending along the first direction X, and a portion extending along the second direction Y, and the portions extending in two directions in the first routing structure 31 are connected at the first corner portion of the first routing structure. The first sub-portion 311 is the first corner portion of the first routing structure 31. The second routing structure 32 includes a second corner portion, a portion extending along the first direction X, and a portion extending along the second direction Y, and the portions extending in two directions in the second routing structure 32 are connected at the second corner portion of the second routing structure. The second sub-portion 322 is the second corner portion of the second routing structure 32.

[0106] Exemplarily, the line width of the first sub-section 311 is greater than the line width of the second sub-section 322. For example, the line width of the first sub-section 311 in the first direction X is greater than the line width of the second sub-section 322 in the first direction X, and / or the line width of the first sub-section 311 in the second direction Y is greater than the line width of the second sub-section 322 in the second direction Y.

[0107] In this embodiment, the first sub-portion 311 serves as the lower plate of the first sub-capacitor C11, and the second sub-portion 322 serves as the lower plate of the second sub-capacitor C22, and the area of ​​the first sub-portion 311 is larger than the area of ​​the second sub-portion 322, so that the overlapping area of ​​the two plates of the first sub-capacitor C11 is larger than the overlapping area of ​​the two plates of the second sub-capacitor C22.

[0108] In some embodiments, Figure 4 As shown, the first shielding structure 41 and the second shielding structure 42 have the same shape and area when projected on the plane where the display panel is located.

[0109] In this embodiment, the first shielding structure 41 and the second shielding structure 42 have the same shape and area, so that it is only necessary to differentiate the design so that the area of ​​the first sub-portion 311 is larger than the area of ​​the second sub-portion 322. In this way, the purpose of making the overlapping area of ​​the two plates of the first sub-capacitor C11 larger than the overlapping area of ​​the two plates of the second sub-capacitor C22 can be achieved with relatively few structural changes.

[0110] In some embodiments, please refer to Figure 2 , Figure 6 and Figure 7, the first dual-gate transistor 11 includes a first reset transistor M4, which is connected between the gate of the first driving transistor M3 and the reset signal line Vref, and the second dual-gate transistor 22 includes a second reset transistor T4, which is connected between the gate of the second driving transistor T3 and the reset signal line Vref. The first capacitor C1 includes a third sub-capacitor C13, and the second capacitor C2 includes a fourth sub-capacitor C24. The first connection structure 31a includes a third wiring structure 33, the second connection structure 32b includes a fourth wiring structure 34, and the reset signal line Vref includes a main body ref0, a third sub-portion ref1 and a fourth sub-portion ref2. The first transistor 111 (i.e., transistor M4_1) and the second transistor 112 (i.e., transistor M4_2) in the first reset transistor M4 are connected through the third wiring structure 33; the third sub-portion ref1 and the third wiring structure 33 at least partially overlap in the thickness direction of the display panel to form a third sub-capacitor C13. The third transistor 223 (ie, transistor T4_1) and the fourth transistor (ie, transistor T4_2) in the second reset transistor T4 are connected via a fourth wiring structure 34; the fourth sub-portion ref2 at least partially overlaps with the fourth wiring structure 34 in the thickness direction of the display panel to form a fourth sub-capacitor C24.

[0111] Exemplarily, the third wiring structure 33 and the fourth wiring structure 34 are located in the semiconductor layer 01 .

[0112] The main portion ref0 , the third sub-portion ref1 and the fourth sub-portion ref2 of the reset signal line Vref are all located in the capacitor metal layer MC.

[0113] The overlapped portion of the third sub-portion ref1 and the third wiring structure 33 can be respectively used as two plates of the third sub-capacitor C13 , and the overlapped portion of the fourth sub-portion ref2 and the fourth wiring structure 34 can be respectively used as two plates of the fourth sub-capacitor C24 .

[0114] Exemplarily, the reset signal line Vref can be used to transmit a fixed negative voltage, so that the third sub-capacitor C13 can be used to stabilize the potential of the node N51, and the fourth sub-capacitor C24 can be used to stabilize the potential of the node N52.

[0115] In some embodiments, please refer to Figure 6 and Figure 7 , the reset signal line Vref extends along the first direction X, and in the second direction Y, the line width of the third sub-portion ref1 is greater than the line width of the fourth sub-portion ref2.

[0116] It should be noted that, in order to clearly show the third sub-capacitor and the fourth sub-capacitor, Figure 7 The structure of the second metal layer M2 is hidden.

[0117] Exemplarily, in the first direction X, the line width of the third sub-portion ref1 is equal to the line width of the fourth sub-portion ref2.

[0118] In this example, the third sub-portion ref1 serves as the upper plate of the third sub-capacitor C13, and the fourth sub-portion ref2 serves as the upper plate of the fourth sub-capacitor C24, and the line width of the third sub-portion ref1 in the second direction Y is greater than the line width of the fourth sub-portion ref2 in the second direction Y, so that the overlapping area of ​​the two plates of the third sub-capacitor C13 is greater than the overlapping area of ​​the two plates of the fourth sub-capacitor C24.

[0119] In some embodiments, Figure 4 As shown, the shapes and areas of the orthographic projections of the third wiring structure 33 and the fourth wiring structure 34 on the plane where the display panel is located are the same.

[0120] In this embodiment, the third routing structure 33 and the fourth routing structure 34 have the same shape and area, so it is only necessary to differentiate the design so that the line width of the third sub-portion ref1 in the second direction Y is greater than the line width of the fourth sub-portion ref2 in the second direction Y. In this way, the purpose of making the overlapping area of ​​the two plates of the third sub-capacitor C13 greater than the overlapping area of ​​the two plates of the fourth sub-capacitor C24 can be achieved through relatively few structural changes.

[0121] In some embodiments, Figure 2 As shown, the first transistor 111 is connected between the gate of the first driving transistor M3 and the second transistor 112, and the third transistor 223 is connected between the gate of the second driving transistor T3 and the fourth transistor 224. The channel area of ​​the first transistor 111 is smaller than the channel area of ​​the third transistor 223. Figure 2 , Figure 8 , Fig. 9 and Fig.10 ,in, Fig. 9 and Fig.10 The structures of the capacitor metal layer MC and the second metal layer M2 are hidden, and the sizes of the channel of the first transistor 111 and the channel of the third transistor 223 in the semiconductor layer B can be designed differently, so that the channel area of ​​the first transistor 111 is smaller than the channel area of ​​the third transistor 223.

[0122] For example, please refer to Figure 8 and Fig. 9 The first transistor 111 includes a transistor M5_1, the third transistor 223 includes a transistor T5_1, the length of a channel b51 of the transistor M5_1 in the second direction Y is less than the length of a channel b52 of the transistor T5_1 in the second direction Y, and the width of the channel b51 of the transistor M5_1 in the first direction X is equal to the width of the channel b52 of the transistor T5_1 in the first direction X.

[0123] For example, please refer to Figure 8 and Fig.10 The first transistor 111 includes a transistor M4_1, the third transistor 223 includes a transistor T4_1, the length of a channel b41 of the transistor M4_1 in the second direction Y is equal to the length of a channel b42 of the transistor T4_1 in the second direction Y, and the width of the channel b41 of the transistor M4_1 in the first direction X is less than the width of the channel b42 of the transistor T4_1 in the first direction X.

[0124] In some embodiments, Figure 2 As shown, the first transistor 111 is connected between the gate of the first driving transistor M3 and the second transistor 112, and the third transistor 223 is connected between the gate of the second driving transistor T3 and the fourth transistor 224. The channel length of the second transistor 112 is less than the channel length of the fourth transistor 224. Figure 2 , Fig.11 , Fig.12 and Fig.13 ,in, Fig.12 and Fig.13 The structures of the capacitor metal layer MC and the second metal layer M2 are hidden, and the sizes of the channel of the second transistor 112 and the channel of the fourth transistor 224 in the semiconductor layer B can be designed differently, so that the channel length of the second transistor 112 and the channel length of the fourth transistor 224 are the same.

[0125] For example, please refer to Fig.11 and Fig.12 The second transistor 112 includes a transistor M5_2, the fourth transistor 224 includes a transistor T5_2, the length of the channel b53 of the transistor M5_2 in the second direction Y is less than the length of the channel b54 of the transistor T5_2 in the second direction Y, and the width of the channel b53 of the transistor M5_2 in the first direction X is equal to the width of the channel b54 of the transistor T5_2 in the first direction X.

[0126] For example, please refer to Fig.11 and Fig.13 The second transistor 112 includes a transistor M4_2, the fourth transistor 224 includes a transistor T4_2, the length of the channel b43 of the transistor M4_2 in the second direction Y is less than the length of the channel b44 of the transistor T4_4 in the second direction Y, and the width of the channel b43 of the transistor M4_2 in the first direction X is equal to the width of the channel b44 of the transistor T4_4 in the first direction X.

[0127] In some embodiments, Figure 2As shown, the first pixel circuit 10 includes a first storage capacitor Cst1, and the first storage capacitor Cst is connected between the gate of the first driving transistor M3 and the first power line PVDD; the second pixel circuit 20 includes a second storage capacitor Cst2, and the second storage capacitor Cst2 is connected between the gate of the second driving transistor T3 and the first power line PVDD; the overlapping area of ​​the two plates of the first storage capacitor Cst1 is greater than the overlapping area of ​​the two plates of the second storage capacitor Cst2.

[0128] Still assuming that the first sub-pixel is a blue sub-pixel and the second sub-pixel is a red sub-pixel or a green sub-pixel, in this embodiment, the first storage capacitor Cst1 can be used to maintain the stability of the gate potential of the first driving transistor M3, and the second storage capacitor Cst2 can be used to maintain the stability of the gate potential of the second driving transistor T3. The overlapping area of ​​the two plates of the first storage capacitor Cst1 is larger, so that the capacitance of the first storage capacitor Cst1 is larger, and thus the first storage capacitor Cst1 has a greater potential maintenance ability, thereby reducing the leakage current of the gate of the first driving transistor M3, so that the gate leakage current of the first driving transistor in the blue sub-pixel and the gate leakage current of the second driving transistor in the red / green sub-pixel tend to be consistent, thereby improving the red cast phenomenon.

[0129] As an example, please refer to Figure 2 and Fig.14 The first storage capacitor Cst1 includes a first plate c01 and a second plate c02, the second storage capacitor Cst2 includes a third plate c03 and a fourth plate c04, the first plate c01 and the third plate c03 are located on the first metal layer M1, the second plate c02 and the fourth plate c04 are located on the capacitor metal layer MC, the area of ​​the first plate c01 is greater than the area of ​​the third plate c03, the area of ​​the second plate c02 is greater than the area of ​​the fourth plate c04, so that the overlapping area of ​​the two plates of the first storage capacitor Cst1 is greater than the overlapping area of ​​the two plates of the second storage capacitor Cst2.

[0130] In some embodiments, Fig.15 As shown, the first pixel circuit 10 includes a first coupling capacitor C31, which is connected between the gate of the first driving transistor M3 and the scanning signal line S2 (i). The second pixel circuit 20 includes a second coupling capacitor C32, which is connected between the gate of the second driving transistor T3 and the scanning signal line S2 (i). The capacitance value of the first coupling capacitor C31 is greater than the capacitance value of the second coupling capacitor C32.

[0131] In this embodiment, the scanning signal line connected to the coupling capacitor may refer to a scanning signal line for controlling the writing of data signals. For example, the first pixel circuit 10 includes a transistor M2, a first electrode of the transistor M2 is connected to the data signal line, and a second electrode of the transistor M2 is connected to a first electrode of the first driving transistor M3. The transistor M2 is used to write a data signal to the gate of the first driving transistor M3. The second pixel circuit 20 includes a transistor T2, a first electrode of the transistor T2 is connected to the data signal line, and a second electrode of the transistor T2 is connected to a first electrode of the second driving transistor T3. The transistor T2 is used to write a data signal to the gate of the second driving transistor T3. The gates of the transistor M2 and the transistor T2 are both connected to the scanning signal line S2(i).

[0132] To better illustrate the effect of the differentiated design of coupling capacitors, please refer to Table 1. Table 1 illustrates two cases. Case 1 is a case where the first coupling capacitor C31 and the second coupling capacitor C32 are not set. Case 2 is a case where the capacitance value of the first coupling capacitor C31 is greater than the capacitance value of the second coupling capacitor C32.

[0133] In addition, nodes N1 and N6 in Table 1 respectively identify nodes N11 and N61 in the first sub-pixel, and nodes N12 and N62 in the second sub-pixel.

[0134] Table 1

[0135]

[0136] Please refer to Fig.15As shown in Table 1, for example, for case 1, the node N11 of the first sub-pixel needs to reach 1.5V in the light-emitting stage, and the node N12 of the second sub-pixel needs to reach 2V in the light-emitting stage. Since there is no coupling capacitor, the nodes N11 and N12 will not be coupled and pulled up by the scanning signal line S2(i). Ignoring the threshold voltage of the transistor, the data voltages written into the first sub-pixel and the second sub-pixel are 1.5V and 2V respectively. In the writing stage, ignoring the threshold voltage of the transistor, the voltages of the nodes N61 and N11 of the first sub-pixel are both 1.5V, and the voltages of the nodes N62 and N12 of the second sub-pixel are both 2V. For example, the high level (VGH) voltage on the scanning signal line S2(i) is 6V. After the signal of the scanning signal line S2(i) jumps from a low level to a high level, the difference between the high level of the scanning signal line S2(i) and the N6 in the writing stage is the N6 coupling jump voltage. The voltage of the node N61 of the first sub-pixel coupled jump is 4.5V, and the voltage of the node N62 of the second sub-pixel coupled jump is 4V. Taking the coupling ratio of the scanning signal line S2(i) to the node N6 as 80% of the total capacitance of the node N6 as an example, the voltage of N6 after being coupled by the scanning signal line S2(i) is the N6 coupling jump voltage multiplied by 80% plus the voltage of N6 in the writing stage. The voltage of the node N61 of the first sub-pixel after being coupled by the scanning signal line S2(i) is 5.1V (4.5*0.8+1.5=5.1), and the voltage of the node N62 of the second sub-pixel after being coupled by the scanning signal line S2(i) is 5.2V (4*0.8+2=5.2). The voltage difference between the node N61 and the node N11 of the first sub-pixel in the light-emitting stage is 3.6V (5.1-1.5=3.6), and the voltage difference between the node N62 and the node N12 of the second sub-pixel in the light-emitting stage is 3.2V (5.2-2=3.2). Finally, the difference between the voltage difference between the node N11 and the node N61 of the first sub-pixel and the voltage difference between the node N12 and the node N62 of the second sub-pixel is 0.4V.

[0137] For case 2, the node N11 of the first sub-pixel needs to reach 1.5V in the light-emitting stage, and the node N12 of the second sub-pixel needs to reach 2V in the light-emitting stage. Since the capacitance value of the first coupling capacitor C31 is greater than the capacitance value of the second coupling capacitor C32, both the node N11 and the node N12 will be coupled and pulled up by the scanning signal line S2(i), and the node N11 of the first sub-pixel will be pulled up more, so the data voltage written into the first sub-pixel can be smaller. For example, the data voltage written into the first sub-pixel is 0.5V, and the data voltage written into the second sub-pixel is 2V. In the writing stage, ignoring the threshold voltage of the transistor, the voltages of the nodes N61 and N11 of the first sub-pixel are both 0.5V, and the voltages of the nodes N62 and N12 of the second sub-pixel are both 1.5V. The voltage of the coupling jump of the node N61 of the first sub-pixel is 5.5V, and the voltage of the coupling jump of the node N62 of the second sub-pixel is 4.5V. Still taking the example that the coupling ratio of the scanning signal line S2(i) to the node N6 is 80% of the total capacitance of the node N6, the voltage of the node N61 of the first sub-pixel after being coupled by the scanning signal line S2(i) is 4.9V (5.5*0.8+0.5=4.9), and the voltage of the node N62 of the second sub-pixel after being coupled by the scanning signal line S2(i) is 5.1V (4.5*0.8+1.5=5.1). The voltage difference between the node N61 and the node N11 of the first sub-pixel in the light-emitting stage is 3.4V (4.9-1.5=3.4), and the voltage difference between the node N62 and the node N12 of the second sub-pixel in the light-emitting stage is 3.1V (5.1-2=3.1). Finally, the difference between the voltage difference between the node N11 and the node N61 of the first sub-pixel and the voltage difference between the node N12 and the node N62 of the second sub-pixel is 0.3V.

[0138] It can be seen that since the capacitance value of the first coupling capacitor C31 is greater than the capacitance value of the second coupling capacitor C32, the gate leakage current of the first driving transistor in the first sub-pixel and the gate leakage current of the second driving transistor in the second sub-pixel eventually become consistent, thereby improving the color cast phenomenon.

[0139] In some embodiments, please refer to Fig.15 , Fig.16 and Fig.17 The display panel includes a first connection portion 51 and a second connection portion 52. The first connection portion 51 is connected to the gate of the first driving transistor M3 and the first dual-gate transistor 11, and the second connection portion 52 is connected to the gate of the second driving transistor T3 and the second dual-gate transistor 22. The first connection portion 51 and the scanning signal line S2(i) at least partially overlap in the thickness direction of the display panel to form a first coupling capacitor C31, and the second connection portion 52 and the scanning signal line S2(i) at least partially overlap in the thickness direction of the display panel to form a second coupling capacitor C32.

[0140] Exemplarily, the first connection portion 51 and the second connection portion 52 are located in the second metal layer M2, one end of the first connection portion 51 is connected to the first dual-gate transistor 11 through a via, and the other end of the first connection portion 51 is connected to the gate of the first driving transistor M3 through a via. One end of the second connection portion 52 is connected to the second dual-gate transistor 12 through a via, and the other end of the second connection portion 52 is connected to the gate of the second driving transistor T3 through a via. The first connection portion 51 and the second connection portion 52 extend along the second direction Y.

[0141] The scan signal line S2 (i) is located in the first metal layer M1 and extends along the first direction X. Different line segments on the scan signal line S2 (i) overlap with the first connection portion 51 and the second connection portion 52 respectively.

[0142] The overlapped portion of the first connection portion 51 and the scanning signal line S2 can be respectively used as two plates of the first coupling capacitor C31 , and the overlapped portion of the second connection portion 52 and the scanning signal line S2 (i) can be respectively used as two plates of the second coupling capacitor C32 .

[0143] In some embodiments, Fig.17 As shown, Fig.17 The structure of the semiconductor layer B and the capacitor metal layer MC is hidden in the figure. The first connecting portion 51 includes a first connecting segment 511. The first connecting segment 511 and the scanning signal line S2(i) overlap in the thickness direction of the display panel. The second connecting portion 52 includes a second connecting segment 522. The second connecting segment 522 and the scanning signal line S2(i) overlap in the thickness direction of the display panel. The scanning signal line S2(i) extends along a first direction X, and the first connecting segment 511 and the second connecting segment 522 extend along a second direction Y. The first direction X and the second direction Y intersect.

[0144] Exemplarily, in the first direction X, the line width of the first connecting segment 511 is greater than the line width of the second connecting segment 522. In the second direction Y, the line width of the first connecting segment 511 is equal to the line width of the second connecting segment 522. In this example, the area of ​​the first connecting segment 511 is greater than the area of ​​the second connecting segment 522, so that the overlapping area of ​​the two plates of the first coupling capacitor C31 is greater than the overlapping area of ​​the two plates of the second coupling capacitor C32, and thus the capacitance value of the two plates of the first coupling capacitor C31 is greater than the capacitance value of the two plates of the second coupling capacitor C32.

[0145] For example, the second connection portion 52 may be designed to reduce the line width only in the portion overlapping with the scan signal line S2 ( i ).

[0146] In other embodiments, please refer to Fig.15 , Fig.18 and Fig.19 , Fig.19 The structure of the semiconductor layer B is hidden in the figure. The display panel further includes an auxiliary portion 53 connected to the first connecting portion 51. The auxiliary portion 53 and the scanning signal line S2(i) at least partially overlap in the thickness direction of the display panel.

[0147] The overlapping portion of the first connecting portion 51 and the scanning signal line S2(i) can be used as the two plates of the first coupling capacitor C31, and the overlapping portion of the auxiliary portion 53 and the scanning signal line S2(i) can also be used as the two plates of the first coupling capacitor C31. In this way, it is equivalent to increasing the overlapping area of ​​the two plates of the first coupling capacitor C31, so that the overlapping area of ​​the two plates of the first coupling capacitor C31 is larger than the overlapping area of ​​the two plates of the second coupling capacitor C32, and further makes the capacitance value of the first coupling capacitor C31 larger than the capacitance value of the second coupling capacitor C32.

[0148] In some embodiments, Fig.19 As shown, the auxiliary portion 53 and the first connecting portion 51 are located in different film layers. For example, the auxiliary portion 53 is located in the capacitor metal layer MC, and the first connecting portion 51 is located in the second metal layer M2.

[0149] In other embodiments, in order to make the gate leakage current of the first driving transistor in the blue sub-pixel and the gate leakage current of the second driving transistor in the red / green sub-pixel tend to be consistent, the reset voltages of the blue sub-pixel and the red / green sub-pixel may be designed differently. Fig. 20 As shown, the display panel includes a first reset signal line Vref1 and a second reset signal line Vref2, the first reset signal line Vref1 is used to transmit a first reset voltage, and the second reset signal line Vref2 is used to transmit a second reset voltage. At least one first double-gate transistor 11 is used to write the first reset voltage to the gate of the first driving transistor M3, and at least one second double-gate transistor 22 is used to write the second reset voltage to the gate of the second driving transistor T3; the first reset voltage is less than the second reset voltage.

[0150] Since the driving current required by the blue sub-pixel is the largest when displaying a white image, the gate potential of the driving transistor in the blue sub-pixel is the lowest for a P-type driving transistor. In this embodiment, the first reset voltage is relatively small, so that the leakage current between the first reset voltage and the node N51 makes the node N51 lower than the node N52, so that the difference between the node N51 and the gate potential of the first driving transistor in the blue sub-pixel is close to the difference between the node N52 and the gate potential of the second driving transistor in the red / green sub-pixel, so that the gate leakage current of the first driving transistor in the blue sub-pixel and the gate leakage current of the second driving transistor in the red / green sub-pixel tend to be consistent, thereby improving the reddish phenomenon.

[0151] In any of the above embodiments, the first light emitting element emits blue light, and the second light emitting element emits red light or green light. That is, the first sub-pixel is a blue sub-pixel, and the second sub-pixel is a red sub-pixel or a green sub-pixel. The above embodiments can be combined with each other if there is no contradiction.

[0152] Of course, when displaying a white image, if the driving current required by the red sub-pixel is greater than the driving current required by the green sub-pixel, for the P-type driving transistor, the gate potential of the driving transistor in the red sub-pixel is lower than the gate potential of the driving transistor in the green sub-pixel. In this case, the first sub-pixel can be a red sub-pixel and the second sub-pixel can be a green sub-pixel.

[0153] In some embodiments, Figure 1 As shown, the plurality of sub-pixels further include a third sub-pixel 3, which includes a third pixel circuit 30 and a third light-emitting element D3 connected to each other, and the first light-emitting element D1, the second light-emitting element D2 and the third light-emitting element D3 have different light-emitting colors.

[0154] like Fig.21 As shown, the third pixel circuit 30 includes a third driving transistor F3 and a third dual-gate transistor 63, the third dual-gate transistor 63 is connected to the gate of the third driving transistor F3, the third dual-gate transistor 63 includes a fifth transistor 635 and a sixth transistor 636, the fifth transistor 635 and the sixth transistor 636 are connected to a third node N03, and the third node N03 is connected to one end of the third capacitor C4.

[0155] As an example, the overlapping area of ​​the two plates of the third capacitor C4 is the same as the overlapping area of ​​the two plates of one of the first capacitor C1 and the second capacitor C2.

[0156] For example, the first subpixel is a blue subpixel, the second subpixel is a green subpixel, and the third subpixel is a red subpixel. The overlapping area of ​​the two plates of the third capacitor C4 is the same as the overlapping area of ​​the two plates of the second capacitor C2, and the overlapping area of ​​the two plates of the first capacitor C1 is the largest.

[0157] In this example, the layout structures of the sub-pixels of two luminous colors can be designed to be the same, which can reduce the difficulty of the process.

[0158] Exemplarily, the third capacitor C4 includes a fifth sub-capacitor C45 and a sixth sub-capacitor C46. Exemplarily, the other end of the fifth sub-capacitor C45 is connected to the first power line PVDD, and the other end of the sixth sub-capacitor C46 is connected to the reset signal line Vref.

[0159] The overlapping area of ​​the two plates of the fifth sub-capacitor C45 is equal to the overlapping area of ​​the two plates of the second sub-capacitor C22, and the overlapping area of ​​the two plates of the sixth sub-capacitor C46 is equal to the overlapping area of ​​the two plates of the fourth sub-capacitor C24.

[0160] It should be noted that, in various layouts in this document, the layout structures of the second pixel circuit and the third pixel circuit are shown to be the same, which is not intended to limit the present application.

[0161] As another example, as an example, the overlapping area of ​​the two plates of the third capacitor C4 is different from the overlapping area of ​​the two plates of any one of the first capacitor C1 and the second capacitor C2.

[0162] In this example, the layout structure of the sub-pixels of each luminous color can be designed differently according to the luminous characteristics of the sub-pixels of each luminous color, so as to balance the leakage current of the sub-pixels of each luminous color and better improve the display effect.

[0163] The present application also provides a display device, including the display panel provided by the present application. Fig. 22 , Fig. 22 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig. 22 The provided display device 1000 includes a display panel, and the display panel 100 includes the display panel provided by any of the above embodiments of the present application. Fig. 22 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0164] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: sub-pixels, the sub-pixels comprising a first sub-pixel and a second sub-pixel, the first sub-pixel comprising a first pixel circuit and a first light-emitting element connected to each other, the second sub-pixel comprising a second pixel circuit and a second light-emitting element connected to each other, and the first light-emitting element and the second light-emitting element emit different colors of light; The first pixel circuit includes a first driving transistor and a first dual-gate transistor, wherein the first dual-gate transistor is connected to a gate of the first driving transistor; The second pixel circuit includes a second driving transistor and a second dual-gate transistor, wherein the second dual-gate transistor is connected to a gate of the second driving transistor; The first dual-gate transistor includes a first transistor and a second transistor, the first transistor and the second transistor are connected to a first node, and the first node is connected to one end of a first capacitor; the second dual-gate transistor includes a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected to a second node, and the second node is connected to one end of a second capacitor; In a direction perpendicular to the plane where the display panel is located, an overlapping area of ​​two plates of the first capacitor is different from an overlapping area of ​​two plates of the second capacitor.

2. The display panel according to claim 1, characterized in that: The first light emitting element emits blue light, the second light emitting element emits red light or green light, and the overlapping area of ​​the two plates of the first capacitor is greater than the overlapping area of ​​the two plates of the second capacitor.

3. The display panel according to claim 1, characterized in that: The first transistor is connected between the gate of the first driving transistor and the second transistor, and the third transistor is connected between the gate of the second driving transistor and the fourth transistor; A channel area of ​​the first transistor is smaller than a channel area of ​​the third transistor.

4. The display panel according to claim 1, characterized in that: The first transistor is connected between the gate of the first driving transistor and the second transistor, and the third transistor is connected between the gate of the second driving transistor and the fourth transistor; A channel length of the second transistor is smaller than a channel length of the fourth transistor.

5. The display panel according to claim 1, characterized in that: The first transistor is connected between the gate of the first driving transistor and the second transistor, and the third transistor is connected between the gate of the second driving transistor and the fourth transistor; A channel area of ​​the first transistor is smaller than a channel area of ​​the second transistor.

6. The display panel according to claim 1, characterized in that: The first transistor and the second transistor are connected via a first connection structure, the third transistor and the fourth transistor are connected via a second connection structure, the display panel further comprises a first conductive portion and a second conductive portion, and the first conductive portion and the second conductive portion both receive a fixed voltage signal; The first connection structure and the first conductive portion at least partially overlap in the thickness direction of the display panel to form the first capacitor, and the second connection structure and the second conductive portion at least partially overlap in the thickness direction of the display panel to form the second capacitor.

7. The display panel according to claim 6, characterized in that: The first connection structure includes a first sub-portion, and the first sub-portion and the first conductive portion overlap in a thickness direction of the display panel; The second connection structure includes a second sub-portion, and the second sub-portion and the second conductive portion overlap in a thickness direction of the display panel; An area of ​​the first sub-portion is greater than an area of ​​the second sub-portion.

8. The display panel according to claim 6, characterized in that: The first conductive portion includes a third sub-portion, and the third sub-portion and the first connecting portion overlap in a thickness direction of the display panel; The second conductive portion includes a fourth sub-portion, and the fourth sub-portion and the second connecting portion overlap in a thickness direction of the display panel; The area of ​​the third sub-portion is greater than the area of ​​the fourth sub-portion.

9. The display panel according to claim 6, characterized in that: The first electrode of the first driving transistor and the first electrode of the second driving transistor are connected to a first power line, the first dual-gate transistor includes a first threshold compensation transistor, the first threshold compensation transistor is connected between the gate of the first driving transistor and the second electrode of the first driving transistor, and the second dual-gate transistor includes a second threshold compensation transistor, the second threshold compensation transistor is connected between the gate of the second driving transistor and its second electrode.

10. The display panel according to claim 9, characterized in that: The first capacitor includes a first sub-capacitor, the second capacitor includes a second sub-capacitor, the first connection structure includes a first wiring structure, the second connection structure includes a second wiring structure, and the first transistor and the second transistor in the first threshold compensation transistor are connected through the first wiring structure. The third transistor and the fourth transistor in the second threshold compensation transistor are connected via the second wiring structure; The first conductive portion includes a first shielding structure, the second conductive portion includes a second shielding structure, the first shielding structure and the second shielding structure are connected to a first power line, the first shielding structure and the first wiring structure at least partially overlap in the thickness direction of the display panel to form the first sub-capacitor, and the second shielding structure and the second wiring structure at least partially overlap in the thickness direction of the display panel to form the second sub-capacitor; The first sub-portion of the first wiring structure and the first shielding structure overlap in the thickness direction of the display panel, and the second sub-portion of the second wiring structure and the second shielding structure overlap in the thickness direction of the display panel; The area of ​​the first sub-portion is greater than that of the second sub-portion, and the orthographic projections of the first shielding structure and the second shielding structure on the plane where the display panel is located have the same shape and area.

11. The display panel according to claim 6, characterized in that: The first dual-gate transistor includes a first reset transistor connected between the gate of the first drive transistor and a reset signal line, and the second dual-gate transistor includes a second reset transistor connected between the gate of the second drive transistor and the reset signal line.

12. The display panel according to claim 11, characterized in that: The first capacitor includes a third sub-capacitor, the second capacitor includes a fourth sub-capacitor, the first connection structure includes a third wiring structure, the second connection structure includes a fourth wiring structure, and the first transistor and the second transistor in the first reset transistor are connected via the third wiring structure. The third transistor and the fourth transistor in the second reset transistor are connected via the fourth wiring structure; The reset signal line of the display panel comprises a main body portion, a third sub-portion and a fourth sub-portion connected to each other, the first conductive portion comprises the third sub-portion, and the second conductive portion comprises the fourth sub-portion; The third sub-portion and the third wiring structure at least partially overlap in the thickness direction of the display panel to form the third sub-capacitor, and the fourth sub-portion and the fourth wiring structure at least partially overlap in the thickness direction of the display panel to form the fourth sub-capacitor; The main body of the reset signal line extends along the first direction, and in the second direction, the line width of the third sub-portion is greater than the line width of the fourth sub-portion, and the third wiring structure and the fourth wiring structure have the same shape and area of ​​the orthographic projection on the plane where the display panel is located.

13. The display panel according to claim 1, characterized in that: The first pixel circuit includes a first storage capacitor connected between the gate of the first driving transistor and a first power line; The second pixel circuit comprises a second storage capacitor, and the second storage capacitor is connected between the gate of the second driving transistor and the first power line; An overlapping area of ​​two plates of the first storage capacitor is greater than an overlapping area of ​​two plates of the second storage capacitor.

14. The display panel according to claim 1, characterized in that: The first pixel circuit includes a first coupling capacitor, and the first coupling capacitor is connected between the gate of the first driving transistor and the scanning signal line; The second pixel circuit includes a second coupling capacitor, and the second coupling capacitor is connected between the gate of the second driving transistor and the scanning signal line; The capacitance value of the first coupling capacitor is greater than the capacitance value of the second coupling capacitor.

15. The display panel according to claim 14, characterized in that: The display panel includes a first connection portion and a second connection portion, the first connection portion is connected to the gate of the first driving transistor and the first double-gate transistor, and the second connection portion is connected to the gate of the second driving transistor and the second double-gate transistor; The first connection portion and the scanning signal line at least partially overlap in the thickness direction of the display panel to form the first coupling capacitor, and the second connection portion and the scanning signal line at least partially overlap in the thickness direction of the display panel to form the second coupling capacitor.

16. The display panel according to claim 15, characterized in that: The first connecting portion includes a first connecting segment, and the first connecting segment and the scanning signal line overlap in a thickness direction of the display panel; The second connecting portion includes a second connecting segment, and the second connecting segment and the scanning signal line overlap in a thickness direction of the display panel; The scanning signal line extends along a first direction, the first connecting section and the second connecting section extend along a second direction, and the first direction and the second direction intersect; In the first direction, a line width of the first connecting segment is greater than a line width of the second connecting segment.

17. The display panel according to claim 15, characterized in that: The display panel further includes an auxiliary portion connected to the first connection portion, and the auxiliary portion and the scan signal line at least partially overlap in a thickness direction of the display panel.

18. The display panel according to claim 17, characterized in that: The auxiliary portion and the first connecting portion are located in different film layers.

19. The display panel according to claim 1, characterized in that: The first dual-gate transistor is used to write a first reset voltage into the gate of the first driving transistor, and the second dual-gate transistor is used to write a second reset voltage into the gate of the second driving transistor; The first reset voltage is lower than the second reset voltage.

20. The display panel according to claim 1, characterized in that: The plurality of sub-pixels further include a third sub-pixel, the third sub-pixel including a third pixel circuit and a third light-emitting element connected to each other, and the first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors of light; The third pixel circuit includes a third driving transistor and a third dual-gate transistor, the third dual-gate transistor is connected to the gate of the third driving transistor, the third dual-gate transistor includes a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor are connected to a third node, and the third node is connected to one end of a third capacitor; The overlapping area of ​​the two plates of the third capacitor is the same as the overlapping area of ​​the two plates of one of the first capacitor and the second capacitor.

21. The display panel according to claim 1, characterized in that: The plurality of sub-pixels further include a third sub-pixel, the third sub-pixel including a third pixel circuit and a third light-emitting element connected to each other, and the first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors of light; The third pixel circuit includes a third driving transistor and a third dual-gate transistor, the third dual-gate transistor is connected to the gate of the third driving transistor, the third dual-gate transistor includes a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor are connected to a third node, and the third node is connected to one end of a third capacitor; The overlapping area of ​​the two plates of the third capacitor is different from the overlapping area of ​​the two plates of any one of the first capacitor and the second capacitor.

22. The display panel according to any one of claims 1 to 21, wherein the first light-emitting element emits blue light, and the second light-emitting element emits red light or green light.

23. A display device, characterized in that: Comprising a display panel according to any one of claims 1 to 22.

Images