Backside contact for signal routing

Abstract

A cell layout that may be implemented in a FinFET device or other FET device is disclosed. The cell layout utilizes an isolated gate structure to provide routing between the signal input of the active gate and the backside metal layer. The isolation gate structure includes a metal filler surrounded by a gate spacer. The metal filler is connected between a top side layer in the device and a back side layer in the device. The metal filler may be connected to the signal input of the active gate through a route in a top side metal layer or a metal line placed in a top side insulating layer. The isolation gate structure may be part of any standard cell placed at the cell boundary or inside the cell to provide access to backside signal routing. Additionally, a filler cell having an isolated gate structure may provide backside routing connections for adjacent functional cells.

Description

Background Art Technical Field

[0001] Embodiments described herein relate to signal routing in semiconductor devices. More particularly, embodiments described herein relate to signal routing through backside layers of integrated circuits.

[0002] Related technical description

[0003] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell approaches is toward reducing the size of standard cells while increasing the complexity (e.g., circuit density and number of components) within the standard cells. However, as standard cell designs become smaller, providing access (e.g., connections) to components within the standard cells becomes more difficult.

[0004] Additionally, as the size of a standard cell decreases, the performance of the standard cell may become more affected by characteristics within the cell. For example, resistance within a standard cell (such as in a metal trace or in the interface between a diffusion region and a metal trace in the cell) may reduce the performance of the cell, with the impact on performance becoming more problematic as the cell becomes smaller. Thus, reducing trace resistance within a standard cell may improve the performance of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The features and advantages of the methods and apparatus of the embodiments described in the present disclosure will be more fully understood by reference to the following detailed description of presently preferred but merely exemplary embodiments according to the embodiments described in the present disclosure when taken in conjunction with the accompanying drawings, in which:

[0006] Figure 1 Depicted are representations of embodiments of a standard cell with backside layer power connections according to some embodiments.

[0007] Figure 2 Depicted along the Figure 1 A cross-sectional representation of a standard cell is shown along section line 2-2.

[0008] Figure 3 Depicted are representations of embodiments of a cell with routing between an active gate and a backside metal layer through an isolation gate structure, according to some embodiments.

[0009] Figure 4 Depicted along the Figure 3 A cross-sectional representation of the cell is shown along section line 4-4.

[0010] Figure 5Depicted are representations of embodiments of a cell with alternative routing between active gate and isolation gate structures according to some embodiments.

[0011] Figure 6 Depicted along the Figure 5 A cross-sectional representation of the cell is shown along section line 6-6.

[0012] Figure 7 Depicted is a cross-sectional representation of a cell with a gate contact connected to a signal input and source / drain to an active gate, according to some embodiments.

[0013] Figure 8 Depicted are representations of embodiments of an integrated circuit layout having an isolation gate with signal routing in both topside and backside layers, according to some embodiments.

[0014] Fig. 9 Depicted is a representation of topside signal tracks in an integrated circuit layout with topside-only signal routing, according to some embodiments.

[0015] Fig.10 Depicted are representations of topside signal tracks and backside signal tracks in an integrated circuit layout with topside and backside signal routing, according to some embodiments.

[0016] Fig.11 Depicted is a cross-sectional representation of an integrated circuit device having two types of routing connections between a signal input of an active gate and a metal fill in an isolation gate, according to some embodiments.

[0017] Fig.12 Depicted is a top view representation of an integrated circuit layout with functional cells and filler cells according to some embodiments.

[0018] Fig.13 Depicted is a cross-sectional representation of a filler cell having an isolation gate structure for providing a backside via, according to some embodiments.

[0019] Fig.14 is a block diagram of one embodiment of an example system.

[0020] Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments of the present invention are shown in the drawings by way of example and described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the scope of the claims to the specific forms disclosed. On the contrary, the application is intended to cover all modifications, equivalents and alternatives that fall within the essence and scope of the disclosure of the application defined by the appended claims. DETAILED DESCRIPTION

[0021] The present disclosure relates to the use of a backside metal layer to provide control signal connections to transistors in an integrated circuit cell, such as a standard cell. As used herein, the term "standard cell" refers to a set of transistor structures, passive structures, and interconnect structures formed on a substrate to provide a logic function or a memory function for a variety of specific implementation standards. An integrated circuit cell may also include a custom circuit design unit designed separately for a specific implementation. The embodiments of the circuit design unit described herein may be implemented in various specific implementations of a logic integrated circuit or a memory integrated circuit.

[0022] Many current designs of cells provide for connections and routing of power or signals to transistors or other structures in the area above the transistors. For example, connections and routing for power or signals may be provided in a topside layer of the device (e.g., a layer above an active layer of a transistor in the device when viewed in a typical cross-sectional view). As used herein, the term "topside" refers to an area of ​​a device that is vertically above an active layer of the device (e.g., above a transistor area of ​​the device). For example, the topside may refer to a component (such as a contact or layer) that is located above a transistor area in a vertical dimension, as depicted in the figure and described herein. In some instances, the term "frontside" may be used interchangeably with the term "topside".

[0023] Some recent developments for designing standard cells move the connections and routing for power connections to the metal layer below the transistor. For example, connections and routing for power can be provided in the backside layer of the device (e.g., the layer below the active layer of the transistor in the device when viewed in a typical cross-sectional view). As used herein, the term "backside" refers to an area of ​​the device that is vertically located below the active layer of the device (e.g., below the transistor area of ​​the device). For example, the backside may refer to a component (such as a contact or layer) that is located below the transistor area in the vertical dimension, as depicted in the figure and described herein. It should be noted that, as used herein, the backside elements located below the active layer may be located above, inside, or below the silicon substrate on which the active layer is manufactured. That is, as used herein, the "backside" is relative to the active layer, not the silicon substrate.

[0024] Figure 1 Depicted are representations of embodiments of standard cells with backside layer power connections according to some embodiments. To simplify the drawings, only components relevant to the present disclosure are shown in the representations of the cells disclosed herein. Those skilled in the art will appreciate that additional components may be present in any of the cells depicted herein. For example, in Figure 1 In some depictions, the vertically extending gates in the drawings may be visible. Figure 1 , (A) is a top view representation of an embodiment of a standard cell 100 , and (B) is a bottom view representation of an embodiment of a standard cell. Figure 2 Depicted along the Figure 1 The cross-section of the standard cell 100 is shown along the section line 2-2. Figure 1 As shown in (B), the stub 2-2 is positioned across the power rail of the backside metal layer 126. A representation of the backside via 128 described further below is depicted in Figure 1 (B) in.

[0025] exist Figure 2 In the illustrated embodiment, the standard cell 100 includes a substrate 102. In some embodiments, the substrate 102 is a silicon substrate. In various embodiments, the substrate 102 may include additional components or features for implementation in the cell 100. For example, the substrate 102 may include an insulating layer 104 (e.g., an oxide layer), a diffusion (e.g., oxide diffusion) region, or a doped region for implementation in the cell 100. To simplify the drawings, the substrate 102 and the insulating layer 104 are depicted as a single layer. In some embodiments, the insulating layer 104 may include a plurality of insulating layers. For example, the insulating layer 104 may include a plurality of oxide layers, a plurality of nitride layers, or a combination of various insulating layers.

[0026] In various embodiments, the standard cell 100 includes a device 106 formed on a substrate 102. The device 106 can be, for example, a transistor, such as a FinFET device, a nanosheet FET (NSH) device, or a GAAFET ("Gate All Around" FET) device. Other embodiments of transistor devices are also contemplated. In various embodiments, the device 106 includes a gate 108, a gate spacer 110, a source / drain region 112, and a source / drain contact 114 formed in the substrate 102.

[0027] In certain embodiments, gate 108 (e.g., gate 108A, 108B) is an active gate in device 106. Gate 108 may be, for example, a polysilicon line (e.g., a polysilicon layer or a metal layer). Gate spacer 110 may be positioned between gate 108 and source / drain region 112. In various embodiments, gate spacer 110 is formed as part of gate 108 (e.g., the gate and spacer are formed in the same process flow). Source / drain region 112 (e.g., source / drain region 112A, 112B, 112C) is positioned on the sides of gate 108 and spacer 110. Source / drain region 112 may be, for example, an epitaxial layer grown on a fin or nanosheet stack or any 2D (two-dimensional) channel material. Various embodiments may also be envisioned in which source / drain region 112 is at least partially positioned in substrate 102.

[0028] In some embodiments, the isolation gate 116 is positioned on the opposite side of the device 106. The isolation gate 116 may include a metal fill 118 and a spacer 120. In some embodiments, the isolation gate 116 may include only an insulator material (eg, the fill 118 is an insulator material). Figure 2 In the illustrated embodiment, isolation gates 116 (e.g., gates 116A, 116B) provide isolation on each side of device 106, with metal fills 118A, 118B and spacers 120A, 120B extending into substrate 102 beneath active regions of the device (e.g., beneath transistors of device 106). Additionally, spacers 120 extend into insulating layer 104 such that isolation gates 116 define isolation of device 106 and provide electrical signal isolation between device 106 and adjacent devices.

[0029] In some embodiments, insulating layer 122 and topside metal layer 124 are formed over device 106 and isolation gate 116 (e.g., in the top side of the device). Insulating layer 122 can include one or more insulating layers formed over device 106. For example, insulating layer 122 can include one or more oxide layers. In various embodiments, insulating layer 122 at least partially surrounds or encapsulates regions of device 106 (e.g., gate 108, spacers 110, source / drain regions 112, and contacts 114) and isolation gate 116.

[0030] In the illustrated embodiment, the topside metal layer 124 includes one or more metal layers that provide routing for the device 106 and / or other devices in the cell 100. In various embodiments, the topside metal layer 124 provides routing for the connection of control signals to / from the device 106. For example, the gate 108 can be connected to various metal routes in the topside metal layer 124 through vias or other connections through the insulating layer 122. As used herein, the term "metal routing" refers to any combination of metal vias, metal lines, metal traces, etc. that provide a path / route between two structures. Additional embodiments can be envisioned in which the metal in the "metal routing" is replaced with an alternative conductive material. For example, the metal in the "metal routing" can be replaced with a superconductor material, a semiconductor material, or a non-metallic conductor.

[0031] In various embodiments of the cell 100, a backside metal layer 126 is formed below the device 106 (e.g., in the back side of the device). In certain embodiments, the backside metal layer 126 includes one or more metal layers that provide power connections for the device 106 (e.g., the backside metal layer is a power rail for the device 106). For example, the backside metal layer 126 can include one or more metal layers that provide power routing from the device 106 to Vdd (e.g., a supply voltage) and Vss (e.g., ground).

[0032] In the illustrated embodiment, power connections to the source / drain regions 112A in the device 106 are made from the backside metal layer 126 through the backside vias 128. The backside vias 128 provide connections between the source / drain regions 112A and the backside metal layer 126 through the substrate 102 and the insulating layer 104. In some embodiments, the backside vias 128 are buried vias through the substrate 102 and the insulating layer 104.

[0033] In various embodiments, such as Figure 2 As shown, the backside metal layer 126 is formed at or near the bottom surface of the substrate 102. In some embodiments, the backside metal layer 126 includes one or more backside layers of the active layer of the device 106 (e.g., the backside metal layer is vertically below the transistor area of ​​the device 106). In some embodiments, the backside metal layer 126 includes one or more buried layers in the substrate 102 (e.g., the metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 126 is buried below the carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments are envisioned in which the backside metal layer 126 is not located in the substrate 102.

[0034] Figure 1 and Figure 2 The embodiments of the standard cell 100 depicted in the drawings can improve area utilization within a cell layout. While providing backside power routing provides improvements in area utilization, further improvements in area utilization can be achieved by routing signal connections (e.g., connections for control signals, data signals, or other signals not associated with power) through the backside of the device in addition to the topside of the device. Providing additional signal connections or routing through the cell can reduce RC delays that typically come from the resistance of via connections in the topside layers of the cell.

[0035] However, the challenge of routing signals through the backside layer is to provide a reasonable and achievable method to route signals from the top side of the active gate to the backside metal layer. For example, routing signal connections from the gate to the backside layer can place signal connections and supply connections in close proximity, thereby causing parasitic problems that reduce the reliability of the device. Additionally, forming a signal connection from the backside layer to the gate may require a highly controlled process to be able to place signal connections and power connections in close proximity, thereby increasing costs and reducing device efficiency. The present disclosure contemplates using a signal path through an isolation region of the device (e.g., an isolation gate) to provide a routing path with low resistance, which can be implemented in both logic and memory cell designs. As described herein, the isolation gate may be part of any standard cell placed at the cell boundary, or may be placed inside the cell to provide access for backside signal routing. Providing the signal routing path described herein can provide better cell performance, power utilization, and area utilization.

[0036] Certain embodiments disclosed herein have three main elements: 1) a metal layer located below a transistor region of an integrated circuit device (e.g., a backside metal layer), 2) a gate structure formed in the transistor region on one side of an active gate of the transistor, wherein the gate structure includes a metal filler positioned between gate spacers, the metal filler connected to the metal layer, and 3) a metal line located above the transistor region, wherein the metal line connects the metal filler to a signal input of the active gate. In certain embodiments, the gate structure is an isolation gate structure positioned to one side of an active region of an integrated circuit device (e.g., on one side of an active gate in a device), and the metal layer is a backside metal layer with wiring for propagating signals (e.g., control signals). In some embodiments, the metal filler is connected to the backside metal layer through a gate contact or other connection structure.

[0037] In various embodiments, the metal line is located in the topside metal layer above the transistor region. A gate contact or other connection structure can connect the metal fill in the gate structure to the metal line in the topside metal layer. Thus, the metal fill in the gate structure connects the topside metal layer to the backside metal layer through the gate contact. In such embodiments, the gate structure provides a connection path between the signal input of the active gate and the backside metal layer to allow the signal to be routed from the active gate to the signal wiring in the backside metal layer.

[0038] In some embodiments, the metal line is located in the insulating layer between the transistor region and the topside metal layer. For example, the metal line can be a jumper or cross-coupler that connects the signal input of the active gate to the metal fill in the gate structure. The metal line may include a gate contact through the insulating layer to the signal input of the active gate and the top of the metal fill. In the case where the metal line connects the signal input of the active gate to the metal fill, the connection path between the signal input of the active gate and the backside metal layer is arranged to pass through the metal fill to allow the signal to be routed from the active gate to the signal wiring in the backside metal layer.

[0039] In short, the inventors have recognized that an isolation gate structure can be utilized to provide a connection path between a signal input of an active gate and a backside metal layer. Utilizing an isolation gate structure has little or no impact on area cost in an integrated circuit device, and does not significantly change the process of manufacturing the integrated circuit device. As described herein, being able to route control signals from an active gate through a backside metal layer within a device structure can improve performance, power utilization, and area scaling of an integrated circuit device.

[0040] Figure 3 Depicted is a representation of an embodiment of a cell having routing between an active gate and a backside metal layer through an isolation gate structure according to some embodiments. Figure 3 , (A) is a top view representation of an embodiment of unit 200, and (B) is a bottom view representation of an embodiment of the unit. Figure 4 Depicted along the Figure 3 The cross-section of unit 200 is shown along section line 4-4. Figure 3 As shown in (B), the stub 4-4 is positioned across the signal portion of the top side metal layer 224 and the back side metal layer 226. A representation of the gate contacts 227A, 227B described further below is depicted in FIG. Figure 3 (A), and the gate contact 228 described further below is depicted in Figure 3 (B) in.

[0041] exist Figure 4 In the illustrated embodiment, the cell 200 includes a substrate 202. In some embodiments, the substrate 202 is a silicon substrate. In various embodiments, the substrate 202 may include additional components or features for implementation in the cell 200. For example, the substrate 202 may include an insulating layer 204, a diffusion region, or a doped region for implementation in the cell 200. In some embodiments, the insulating layer 204 includes one or more oxide layers. To simplify the drawings, the substrate 202 and the insulating layer 204 are depicted as a single layer. In some embodiments, the insulating layer 204 may include multiple insulating layers (e.g., multiple oxide layers).

[0042] In the illustrated embodiment, the cell 200 includes a device 206 formed on a substrate 202. The device 206, as well as the device 106 described above, can be a transistor, such as a FinFET device, a nanosheet FET (NSH) device, or a GAAFET ("all around gate" FET) device. In some embodiments, the device 206 includes a gate 208A, 208B, a gate spacer 210, a source / drain region 212A-212C, and a source / drain contact 214A-214C formed in a transistor region 215 of the device 206 in the cell 100.

[0043] In some embodiments, the isolation gates 216A, 216B are positioned on opposite sides of the device 206. The isolation gates 216A, 216B may include metal fills 218A, 218B, respectively, and spacers 220A, 220B, respectively. Figure 4 As shown, the spacers 220A, 220B extend into the insulating layer 204. Thus, the isolation gates 216A, 216B provide isolation on each side of the device 206, wherein the metal fill 218A, 218B and the spacers 220A, 220B extend into the substrate 202 below the active region of the device (e.g., below the transistors). Thus, the isolation gate 216 defines an isolation region for the device 206 and provides electrical signal isolation between the device 206 and adjacent devices.

[0044] In certain embodiments, gates 108A, 108B are active gates in device 206. Gates 108A, 108B may include, for example, polysilicon lines (e.g., polysilicon layers or metal layers) forming active portions of gates. Gate spacers 210 may be positioned between gate 208 and source / drain regions 212 to define active gates. In various embodiments, gate spacers 210 are formed as part of gate 208 (e.g., gates and spacers are formed in the same process flow). Source / drain regions 212A, 212B, 212C are positioned on the sides of gates 208A, 208B, 208C. Source / drain regions 212A, 212B, 212C may be, for example, fins or nanosheet stacks in FinFET or NSH devices. Various embodiments may also be envisioned in which source / drain regions 212A, 212B, 212C are at least partially positioned in substrate 202.

[0045] In some embodiments, insulating layer 222 and topside metal layer 224 are formed over device 206 and isolation gate 216 (e.g., in the top side of the device over transistor region 215). Insulating layer 222 can include one or more insulating layers formed over transistor region 215. For example, insulating layer 222 can include one or more oxide or nitride layers. In various embodiments, insulating layer 222 at least partially surrounds or encapsulates transistor region 215 (e.g., gate 208, spacers 210, source / drain regions 212, contacts 214, and isolation gate 216) of device 106.

[0046] In various embodiments, topside metal layer 224 includes one or more metal layers above insulating layer 222. Topside metal layer 224 can provide signal routing (e.g., control signal routing) for device 206. For example, metal routing in topside metal layer 224 can provide signal routing for device 206. In the illustrated embodiment of cell 200, backside metal layer 226 is formed below insulating layer 204 in device 206 (e.g., in the back side of the device below transistor region 215).

[0047] In certain embodiments, such as Figure 4 As shown, the backside metal layer 226 is formed at or near the bottom surface of the substrate 202. In some embodiments, the backside metal layer 226 includes one or more backside layers of the active layer of the device 206 (e.g., the backside metal layer is vertically below the transistor region 215 of the device 206). In some embodiments, the backside metal layer 226 includes one or more buried layers in the substrate 202 (e.g., the metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 226 is buried below the carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments can be envisioned in which the backside metal layer 226 is not located in the substrate 202.

[0048] In some embodiments, backside metal layer 226 provides signal routing (e.g., control signal routing) between device 206 and / or other devices in cell 200. For example, backside metal layer 226 may include metal routing that routes a control signal from device 206 to another device in cell 200 (or a device in another cell).

[0049] As described herein, metal routing in backside metal layer 226 may be implemented in combination with metal routing above transistor region 215 (e.g., metal routing in topside metal layer 224) and metal routing through isolation gate structures (e.g., routing through metal fill 218 in isolation gate 216) to provide a signal routing path between a signal input of an active gate in device 206 and another device. Figure 4In the illustrated embodiment, the signal input terminal of the gate 208A is connected to the top side metal layer 224 through the gate contact 227A. In addition, the top of the metal fill 218B in the isolation gate 216B is connected to the top side metal layer 224 through the gate contact 227B. The gate contacts 227A, 227B can be metal vias or other connections formed between the transistor region 215 and the top side metal layer 224 through the insulating layer 222.

[0050] In some embodiments, gate contact 227A connects the signal input of gate 208A to a metal routing in topside metal layer 224, which is further connected to gate contact 227B. Gate contact 227B then connects the metal routing in topside metal layer 224 to metal fill 218B in isolation gate 216B. The bottom of metal fill 218B is then connected to metal routing in backside metal layer 226 through insulating layer 204 using gate contact 228 (e.g., a gate contact via through the insulating layer). Metal fill 218B thus provides a connection between the metal routing in topside metal layer 224 and the metal routing in backside metal layer 226. Thus, metal fill 218B in isolation gate 216B provides a path for routing control signals from the top side of device 206 to the back side of the device. Since isolation gate 216B is typically included in a standard cell layout, implementing metal fill 218B to provide connection between metal routing in topside metal layer 224 and metal routing in backside metal layer 226 has little or no impact on area utilization in cell 200 .

[0051] Additionally, for Figure 4 In the illustrated embodiment of the cell 200, the metal line in the top side metal layer 224 that provides the connection between the gate contact 227A and the gate contact 227B has a relatively short length that provides a small resistance. Therefore, the connection between the signal input terminal of the gate 208A and the metal filler 218B can provide a low RC delay for transmitting the signal. In addition, in the cell 200, the metal filler 218B can have a low resistance due to the metal volume that forms the metal filler. The low resistance of the metal filler 218B can reduce the effect of routing the signal through the isolation gate 216B on the RC delay of the signal.

[0052] An alternative to using metal routing in topside metal layer 224 to connect the signal input of gate 208A to metal filling 218B in isolation gate 216B may be to add metal lines (or other metal structures) in insulating layer 222 connecting the signal input of the gate and the metal filling in the isolation gate.

[0053] Figure 5Depicted is a representation of an embodiment of a cell having alternative routing between active gate and isolation gate structures according to some embodiments. Figure 5 , (A) is a top view representation of an embodiment of unit 200, and (B) is a bottom view representation of an embodiment of the unit. Figure 6 Depicted along the Figure 5 The cross-section of unit 200 is shown along section line 6-6. Figure 5 As shown in (B), the cutout line 5-5 is positioned across the signal portion of the top metal layer 224 and the back metal layer 226. Figure 5 A representation of a gate contact 230 described further below is depicted in (A) of FIG. Figure 5 A representation of the gate contact 228 described herein is depicted in FIG.

[0054] exist Figure 6 In the illustrated embodiment, the connection between the signal input of gate 208A and the top of metal fill 218B is formed by a gate contact 230 positioned in insulating layer 222. In certain embodiments, gate contact 230 includes a gate contact via made from the signal input of gate 208A and the top of metal fill 218B into insulating layer 222. The gate contact via is then connected to a metal line (or other metal routing) formed in insulating layer 222. In various embodiments, when the insulating layer includes multiple insulating layers, the metal line portion of gate contact 230 is formed in a single layer of insulating layer 222. In some embodiments, insulating layer 222 can have an increased thickness (compared to, for example, Figure 1 1 (compared to the insulating layer 122 shown) to provide space for positioning the metal line portion of the gate contact 230 within the insulating layer, with electrical isolation both above and below the metal line.

[0055] Using gate contact 230 to provide a connection between the signal input of gate 208A and the top of metal fill 218B provides this connection without utilizing resources in topside metal layer 224. For example, gate contact 230 is a local jumper or shunt between the signal input of gate 208A and the top of metal fill 218B.

[0056] In some embodiments, gate contact 230 can be implemented to additionally pick up signals from source / drain regions in device 206 . Figure 7A cross-sectional representation of a cell with a gate contact connected to a signal input and source / drain of an active gate according to some embodiments is depicted. In the illustrated embodiment, a gate contact 230' positioned in insulating layer 222 is connected to a contact 214C for source / drain region 212C in addition to being connected to the signal input of gate 208A and the top of metal fill 218B. Connections to both the signal input of gate 208A and source / drain region 212C in device 206 may allow for additional implementations of cell 200.

[0057] Embodiments described herein provide routing of signal paths (eg, control signal paths) through the backside of an integrated circuit device by utilizing metal fills in isolation gates in a layout of the integrated circuit device to provide connections between active gates and backside layers. Figure 8 Depicted is a representation of an embodiment of an integrated circuit layout having an isolation gate with signal routing in both topside and backside layers according to some embodiments. Figure 8 In FIG. 8 , (A) is a top view representation of an embodiment of an integrated circuit layout 800, and (B) is a bottom view representation of an embodiment of an integrated circuit layout. In order to better understand the present disclosure, the layout 800 shows a cell 200 (in Figure 3 and Figure 4 ).

[0058] In the layout 800, the regions 810A, 810B are active regions of the integrated circuit device. The layout 800 includes multiple instances of active gates 208 and isolation gates 216 arranged along the regions 810A, 810B between the topside metal layer 224 in (A) and the backside metal layer 226 in (B). In the illustrated embodiment, the layout 800 includes topside signal tracks 820A, 820B shown in (A) and backside signal tracks 830A, 830B shown in (B). The topside signal track 820A and the backside signal track 830A correspond to the region 810A, while the topside signal track 820B and the backside signal track 830B correspond to the region 810B.

[0059] like Figure 8As shown, signal routing through the active area can be implemented in both the top and back sides of the device using routing connections between the top-side metal layer 224 and the back-side metal layer 226 provided at the isolation gate 216. For example, for the active area 810A, the top-side signal track 820A provides signal routing until the isolation gate 216' is reached, as shown from left to right in (A). At the isolation gate 216', the signal routing is routed to the back-side signal track 830A and propagates out of the layout to the right, as shown in (B). In the active area 810B, the top-side signal track 820B provides signal routing until the isolation gate 216" is reached, as shown from left to right in (A), where the signal routing is routed to the back-side signal track 830B and propagates out of the layout to the right, as shown in (B). It should be understood that although Figure 8 Layout 800 in FIG. 1 depicts an embodiment utilizing topside metal layer 224 for topside signal routing (eg, Figure 3 and Figure 4 ), but a layout similar to layout 800 may be used to implement metal lines in an insulating layer for top-side signal routing (e.g., Figures 5 to 7 implementation scheme).

[0060] like Figure 8 As shown in , adding the ability to route signals through the back side of the device in the integrated circuit layout 800 at the isolation gate 216 allows the back side signal routing to be combined with the top side signal routing. Combining signal routing on the back side of the integrated circuit device with signal routing on the top side of the integrated circuit device (e.g., signal routing on both the top side and the back side) can provide features such as, but not limited to, reducing RC delays for signal routing in the integrated circuit while achieving improved power routing characteristics with little or no impact on area scaling in the integrated circuit device.

[0061] Furthermore, utilizing backside signal routing in addition to topside routing can reduce the number of topside signal tracks required in the integrated circuit layout. In topside signal routing only, multiple signal tracks are typically required to route signals for parallel active areas. For example, three topside signal tracks with two active areas are typically required to provide spacing for making contact with each active area. Fig. 9 A representation of topside signal tracks in an integrated circuit layout with topside-only signal routing according to some embodiments is depicted. In the illustrated embodiment, three signal tracks 910A, 910B, 910C are required to provide sufficient spacing (e.g., xy spacing in the depiction) for the various gate contacts 920 to form connections to the underlying gate.

[0062] Fig.10Depicted are representations of topside signal tracks and backside signal tracks in an integrated circuit layout with topside and backside signal routing according to some embodiments. Fig.10 In the illustrated embodiment, the addition of backside signal routing allows the integrated circuit layout to have only a single topside signal track 1010 and a single backside signal track 1020. Only a single track is required because the topside gate contact 1015 and the backside gate contact 1025 can be positioned at a closer xy spacing in the depiction due to the change in depth (z direction in the depiction).

[0063] Various additional embodiments of integrated circuit devices are contemplated, including utilizing routing through topside metal layers (e.g. Figure 4 ) and routing through metal lines in the top side insulating layer (as shown in the embodiment of Figure 6 The combination shown in the embodiment of the present invention is a connection between the signal input terminal of the active gate and the metal filling in the isolation gate. Fig.11 A cross-sectional representation of an integrated circuit device having two types of routing connections between signal inputs of active gates and metal fills in isolation gates according to some embodiments is depicted. In various embodiments, the integrated circuit device 1100 includes two isolation gates 216', 216", with multiple active gates 208 between the isolation gates in a transistor region above the substrate 202 and the insulating layer 204 (and two active gates to the right of the isolation gate 216" in the depiction). The active gates 208 have source / drain regions 212 with contacts 214 positioned between the gates, and the isolation gates 216', 216" have metal fills 218', 218" surrounded by gate spacers 220', 220".

[0064] In the illustrated embodiment, the metal fill 218' in the isolation gate 216' is connected to the signal routing in the topside metal layer 224 through the gate contact 227'. The metal fill 218' is also connected to the signal routing in the backside metal layer 226 through the gate contact 228'. The signal routing in the topside metal layer 224 is then connected to the signal input of the active gate 208A through the gate contact 227A to complete the routing between the signal input of the active gate 208A and the signal routing in the backside metal layer 226.

[0065] The metal filling 218″ in the isolation gate 216″ is connected to the signal input of the active gate 208A′ through the gate contact 230 positioned in the insulating layer 222. The metal filling 218′ is also connected to the signal routing in the backside metal layer 226 through the gate contact 228″. Therefore, the signal routing between the signal input of the active gate 208A′ and the signal routing in the backside metal layer 226 is completed through the metal filling 218″ in the isolation gate 216″, the gate contact 228″ and the gate contact 230. Additionally, the device 1100 may include one or more source / drain contacts 1110 that provide a signal connection between the source / drain region 212 and the routing in the topside metal layer 224.

[0066] Various embodiments of device 1100 may also include power routing to backside metal layer 226. For example, Fig.11 As shown, the device 1100 includes a backside via 128 connecting the source / drain region 212 to the backside metal layer 226. The backside via 128 can be connected to the power routing in the backside metal layer 226. The power routing in the backside metal layer 226 can be different from the signal routing in the backside metal layer. Therefore, the backside metal layer 226 provides electrical isolation between different routing paths for power and signal routing in the device 1100. Additional implementations that utilize the connection between the signal input of the active gate and the metal fill in the isolation gate via a combination of routing through the topside metal layer and routing through the metal line in the topside insulating layer are contemplated without departing from the scope of the present disclosure.

[0067] In various embodiments, the structure of the isolation gate 216 in the cell 200 described herein ( Figures 3 to 7 216 can be implemented in a filler cell in an integrated circuit layout. Implementing the isolation gate 216 in the filler cell can provide a backside path for a functional unit located adjacent to the filler cell. Fig.12 A top view representation of an integrated circuit layout with functional cells and filler cells is depicted in accordance with some embodiments. In the illustrated embodiment, layout 1200 includes functional cells 1210 and filler cells 1220 .

[0068] Fig.13A cross-sectional representation of a filler unit having an isolation gate structure for providing a backside access is depicted in accordance with some embodiments. In the illustrated embodiment, the filler unit 1220 includes three isolation gate structures 1310. It should be understood that the filler unit 1220 may include any number of isolation gate structures 1310. For example, the number of isolation gate structures 1310 may be determined by the size of the filler unit 1220, with a larger filler unit having a larger number of isolation gate structures. Increasing the number of isolation gate structures 1310 in the filler unit 1220 may reduce the resistance of the connection between the topside metal layer 224 and the backside metal layer 226, while reducing the number of isolation gate structures may reduce material or processing costs. Additionally, the width of the isolation gate structure 1310 may be varied to determine the resistance and material cost associated with the filler unit 1220.

[0069] The isolation gate structure 1310 has a similar structure to the isolation gate 216 described herein. In the illustrated embodiment, the isolation gate structure 1310 includes a metal fill 218 between the spacer 220 and the source / drain region 212, wherein the contact 214 is positioned between the isolation gate structure. The source / drain 212 and the contact 214 may be inactive in the filler unit 1220 (e.g., the transistor region of the filler unit 1220 is inactive). Embodiments in which the source / drain region 212 and the contact 214 are not formed in the filler unit 1220 are contemplated.

[0070] The gate contact 227 connects the top of the metal fill 218 in the isolation gate structure 1310 to the topside metal layer 224, and the gate contact 228 connects the bottom of the metal fill to the backside metal layer 226. Therefore, the metal fill 218 connects the topside metal layer 224 to the backside metal layer 226. In the case where the connection between the topside metal layer 224 and the backside metal layer 226 is formed in the filler unit 1220, the functional unit 1210 ( Fig.12 The topside metal layer 224 or the backside metal layer 226 is formed between the filler cell 1220 and the functional unit 1210 in the layout 1200. Therefore, the filler cell 1220 provides a backside metal layer 226 access point for the functional unit 1210 in the layout 1200.

[0071] Example Computer System

[0072] Next go to Fig.14, which shows a block diagram of one embodiment of a system 1400 that can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 1400 includes at least one instance of a system on a chip (SoC) 1406, which can include multiple types of processing units (such as a central processing unit (CPU), a graphics processing unit (GPU), or others), communication structures, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 1406 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 1406 is coupled to an external memory 1402, peripherals 1404, and a power supply 1408.

[0073] A power supply 1408 is also provided that supplies a supply voltage to the SoC 1406 and one or more supply voltages to the memory 1402 and / or the peripherals 1404. In various embodiments, the power supply 1408 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer or other device). In some embodiments, more than one instance of the SoC 1406 is included (and more than one external memory 1402 is also included).

[0074] The memory 1402 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device can be mounted together with the SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0075] Depending on the type of system 1400, peripherals 1404 include any desired circuitry. For example, in one embodiment, peripherals 1404 include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripherals 1404 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripherals 1404 include user interface devices, such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0076] As illustrated, system 1400 is shown to have applications in a wide range of fields. For example, system 1400 can be used as a part of a chip, circuit, component, etc. of a desktop computer 1410, a laptop computer 1420, a tablet computer 1430, a cellular or mobile phone 1440, or a TV 1450 (or a set-top box coupled to a TV). A smart watch and a health monitoring device 1460 are also illustrated. In some embodiments, a smart watch may include various general computing related functions. For example, a smart watch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watch may or may not include some or any health monitoring related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, and the like.

[0077] The system 1400 may also be used as part of a cloud-based service 1470. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 1400 may be used in one or more devices in a home 1480 other than those previously mentioned. For example, a home appliance may monitor and detect noteworthy situations. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device, and an alert may be provided to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home, and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Fig.14 Also illustrated in the 1400 are applications of various modes of transportation 1490. For example, the system 1400 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), and the like. In various cases, the system 1400 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and the like. Any of these and many other implementations are possible and contemplated. Note that Fig.14 The illustrated devices and applications are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated.

[0078] ***

[0079] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0080] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0081] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0082] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0083] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0084] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0085] ***

[0086] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0087] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a group of two or more items.

[0088] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0089] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0090] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0091] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0092] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0093] The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0094] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0095] ***

[0096] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0097] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0098] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform the particular function.

[0099] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0100] Different "circuits" may be described in the present disclosure. These circuits constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from a standard library. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits.

[0101] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0102] In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements defined by the functions or operations they are configured to implement, with respect to the arrangement of each other and such circuits / units / components and the manner in which they interact, form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by encoding a description of the circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without undue experimentation and with the application of ordinary technicians. HDL descriptions are often expressed in a manner that can be rendered functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0103] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0104] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising: A transistor formed in a transistor region of an integrated circuit, the transistor having an active gate with a signal input terminal; a metal layer, the metal layer being located below the transistor region in a vertical dimension perpendicular to the transistor region; a gate structure formed in the transistor region of the integrated circuit, the gate structure comprising a metal fill positioned between gate spacers in the transistor region, wherein the gate structure is positioned on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension, and wherein the metal fill is connected to the metal layer; and A metal line is located above the transistor region in the vertical dimension, wherein the metal line connects the metal fill to the signal input terminal of the active gate. 2 . The device of claim 1 , further comprising an upper metal layer located above the transistor region in the vertical dimension, wherein the metal line is positioned in the upper metal layer.

3. The device according to claim 1, further comprising: an upper metal layer, the upper metal layer being located above the transistor region in the vertical dimension; and An insulating layer is positioned between the transistor region and the upper metal layer, wherein the metal line is positioned in the insulating layer.

4. The device of claim 1 , wherein the metal fill in the gate structure and the gate spacers extend below the transistor in the vertical dimension, and wherein the metal fill in the gate structure is separated from the first side of the transistor by at least one of the gate spacers to provide electrical isolation between the metal fill and the active gate.

5. The device of claim 1 , further comprising a second gate structure formed in the transistor region of the integrated circuit, the second gate structure comprising a second metal filling positioned between second gate spacers positioned in the transistor region, wherein the second gate structure is positioned on a second side of the transistor in the horizontal dimension, the second side being on an opposite side of the first side of the transistor in the horizontal dimension. 6 . The apparatus of claim 1 , further comprising a control signal routed to the signal input of the active gate, wherein the control signal is routed from the metal layer to the signal input through the metal fill and the metal line. 7 . The device of claim 1 , further comprising a metal signal line in the metal layer, wherein the metal filler connects the signal input terminal of the active gate to the metal signal line.

8. The apparatus of claim 7, wherein the metal signal line is connected to at least one additional transistor formed in the transistor region of the integrated circuit.

9. The device according to claim 1, further comprising: an insulating layer, the insulating layer being positioned between the transistor region and the metal layer; and A gate contact via is in the insulating layer, the gate contact via providing a connection between the metal fill and the metal layer.

10. A device, comprising: a transistor formed in a transistor region of an integrated circuit; a first metal layer, the first metal layer being located above the transistor region in a vertical dimension perpendicular to the transistor region; a second metal layer, the second metal layer being located below the transistor region in the vertical dimension; and A gate structure is formed in the transistor region of the integrated circuit, the gate structure comprising a metal fill positioned between gate spacers in the transistor region, wherein the gate structure is positioned on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension, and wherein the metal fill connects the first metal layer and the second metal layer.

11. The device according to claim 10, further comprising: An active gate is provided in the transistor, wherein the active gate has a signal input terminal, wherein the signal input terminal is connected to the metal filler through the first metal layer.

12. The device according to claim 10, further comprising: An active gate, the active gate being in the transistor, the active gate having a signal input terminal; and A first metal line is located in a first metal layer, wherein the first metal line connects the signal input terminal to the metal filler.

13. The device according to claim 12, further comprising: a second metal line, the second metal line being located in the second metal layer; The second metal line is connected to the signal input terminal through the metal filler and the first metal line.

14. The device of claim 10, wherein the transistor and the gate structure are positioned in a filler cell, the transistor in the transistor region of the filler cell being inactive, the device further comprising: A functional unit is positioned adjacent to the filler unit, wherein the functional unit includes an active transistor having an active gate with a signal input terminal, wherein the signal input terminal of the active transistor is coupled to the first metal layer, and wherein the second metal layer provides routing for control signals between the signal input terminal and a backside metal layer of the functional unit.

15. The apparatus according to claim 10, further comprising: an insulating layer, the insulating layer being positioned between the transistor region and the first metal layer; a first gate contact via, the first gate contact via being in the insulating layer, the first gate contact via connecting the metal filler and the first metal layer; and A second gate contact via is provided in the insulating layer, wherein the second gate contact via connects a signal input terminal of an active gate in the transistor and the first metal layer.

16. A device, comprising: a transistor formed in a transistor region of an integrated circuit; a first insulating layer, the first insulating layer being located above the transistor region in a vertical dimension perpendicular to the transistor region; a metal layer, the metal layer being located below the transistor region in the vertical dimension; a second insulating layer, the second insulating layer being located between the transistor region and the metal layer in the vertical dimension; a gate structure formed in the transistor region of the integrated circuit, the gate structure comprising a metal fill positioned between gate spacers in the transistor region, wherein the gate structure is positioned on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension; a metal line positioned in the first insulating layer, wherein the metal line is connected to the metal filler; and A gate contact via is positioned in the second insulating layer, wherein the gate contact via connects the metal fill to the metal layer. 17 . The device of claim 16 , further comprising an active gate in the transistor, wherein a signal input terminal of the active gate is connected to the metal layer through the metal line, the metal fill, and the gate contact via.

18. The device of claim 17, wherein source / drain regions of the active gate are connected to the metal line.

19. The apparatus according to claim 17, further comprising: a first gate contact via, the first gate contact via being in the first insulating layer, the first gate contact via connecting the metal filler and the metal line; and A second gate contact via is provided in the first insulating layer, wherein the second gate contact via connects the signal input terminal of the active gate and the metal line.

20. The device of claim 16, further comprising an upper metal layer over the transistor region, wherein the upper metal layer is electrically isolated from the metal line.

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