A data processing method and device, computer equipment and storage medium

Abstract

The application relates to the technical field of storage, and discloses a data processing method and device, computer equipment and a storage medium, which are applied to a read master core of a hard disk controller, and the hard disk controller further comprises at least one read backup core; the method comprises the following steps: in the process of reading and writing a source data block and a target data block, a first variable value is obtained from a hard disk cache at a first time, the first variable is used for measuring the load amount of the read master core at the first time; if the first variable value is a first numerical value at the first time, a request reading message is generated and sent to the at least one read backup core, the request reading message is used for instructing the at least one read backup core to start and assisting the read master core to execute the reading and writing operation on the source data block and the target data block, and the first numerical value is used for indicating that the read master core is in a load state. The application can solve the problem that, in the hard disk garbage collection process, if the read processing core is occupied by other services or is insufficient in performance, the reading speed is slow, and the service performance is affected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a data processing method and device, computer equipment and a storage medium. BACKGROUND

[0002] When a solid state disk (SSD) needs to perform garbage collection (GC), a source data block with the most garbage data is usually selected first, then a P2L (Physical-to-Logical) reverse table of the source data block is read, and garbage data is identified by comparing the read result with the corresponding content of the L2P (Logical-to-Physical) mapping table of the source data block. Data with consistent comparison results is determined as valid data that needs to be moved to a target data block, otherwise, data with inconsistent comparison results is determined as garbage data to be erased.

[0003] In related technologies, when the SSD controller reads valid data, the GC read processing core in the SSD controller continuously sends read requests to the non-volatile flash controller (NFC), and the NFC reads the valid data in the source data block. After the NFC finishes reading, the GC read processing core is returned, and the GC read processing core sends the read valid data to the GC write processing core, and the GC write processing core rewrites the read valid data to a new target data block according to a certain organization format. In this SSD garbage collection mode, if the GC read processing core is occupied by other services or has insufficient performance, it will cause the GC read processing core to read data slowly, affecting the performance of the SSD service. SUMMARY

[0004] Therefore, the present application provides a data processing method to solve the problem of slow data reading speed and poor service performance caused by the read processing core being occupied by other services or having insufficient performance during the garbage collection process of the hard disk.

[0005] In a first aspect, the present application provides a data processing method applied to a read master core of a hard disk controller, the hard disk controller further comprising at least one read backup core; the method comprising: acquiring a first variable value from a hard disk cache at a first time during a read-write operation on a source data block and a target data block, the first variable being used to measure the load of the read master core at the first time; if the first variable value is a first numerical value at the first time, generating and sending a request read message to the at least one read backup core, the request read message being used to instruct the at least one read backup core to start and assist the read master core to perform the read-write operation on the source data block and the target data block, the first numerical value being used to indicate that the read master core is in a load state.

[0006] Based on the method of the first aspect, the read master core can obtain the first variable value from the hard disk cache at the first time during the read-write operation on the source data block and the target data block, and if the first variable value is the first numerical value at the first time, a request read message is generated and sent to at least one read backup core to instruct the at least one read backup core to start and assist the read master core to perform the read-write operation on the source data block and the target data block.

[0007] Since the first variable value is the first numerical value at the first time, it means that the read master core is in an overload state at the first time. At this time, the request read message is generated and sent to the at least one read backup core to start the at least one read backup core to assist the read master core to perform the read-write operation on the source data block and the target data block. That is, when the read master core is heavily loaded in data processing or data read-write operation, the at least one read backup core is used to share the load of the read master core in data processing, so as to achieve load balancing, avoid the problem of slow data reading speed caused by the read processing core being occupied by other services or insufficient performance during the hard disk garbage collection process, and improve the overall performance of the hard disk garbage collection.

[0008] In combination with the first aspect, in an optional implementation, the method further includes: obtaining the first variable value from the hard disk cache at a second time during the read-write operation on the source data block and the target data block, the second time being after the first time; and if the first variable value is a second numerical value at the second time, a stop read message is sent to the at least one read backup core, the stop read message being used to instruct the at least one read backup core to stop, and the second numerical value being used to indicate that the read master core is in a low-load state.

[0009] In the embodiment of the application, the first variable value is the second numerical value at the second time, which means that the read master core is in a low-load state at the second time. At this time, the stop read message is generated and sent to the at least one read backup core to make the at least one read backup core stop assisting the read master core to perform the read-write operation on the source data block and the target data block. That is, when the read master core is lightly loaded in data processing or data read-write operation, the at least one read backup core is actively stopped to reduce the impact on the services on the at least one backup core and improve the response speed of the at least one backup core.

[0010] In combination with the first aspect, in an optional implementation, the hard disk controller further includes a write processing core; and the read-write operation on the source data block and the target data block includes: sequentially sending a plurality of read commands to the flash memory controller, each read command being used to instruct the flash memory controller to read valid data of at least one address in the source data block, and generating and returning a read information to the read master core based on the valid data; sequentially receiving a plurality of read information returned from the flash memory controller, and sequentially sending the plurality of read information to the write processing core to make the write processing core write the valid data into the target data block.

[0011] In the embodiment of the present application, the read commands can be sequentially issued and the returned read information can be sequentially received, so as to avoid high delay caused by issuing a large number of commands at one time and improve overall performance.

[0012] With reference to the first aspect, in an optional implementation, the hard disk cache pre-stores a second variable value, and the second variable value is used to indicate the number of times that the detected message concurrency of the read master core being processed is greater than or equal to a first threshold value; the method further includes: obtaining the second variable value in the process of performing read-write operations on the source data block and the target data block; if the second variable value is less than a second threshold value, detecting a first number of read commands that have been sent and for which read information returned by the flash controller has not been received, and detecting a second number of read messages that have not been sent to the write processing core, and the sum of the first number and the second number is the message concurrency; if it is detected that the message concurrency is greater than or equal to the first threshold value, the second variable value is incremented by one; and if it is detected that the message concurrency is less than the first threshold value, the second variable value is cleared.

[0013] In the embodiment of the present application, the hard disk pre-stores the second variable value, so as to record the number of times that the detected message concurrency of the read master core being processed is greater than or equal to the first threshold value, so as to facilitate subsequent determination of the value of the first variable value based on the second variable value, so as to judge the load state of the read master core.

[0014] With reference to the first aspect, in an optional implementation, the method further includes: if the obtained second variable value is greater than or equal to the second threshold value, setting the first variable value to the first value.

[0015] In the embodiment of the present application, when the recorded number of times that the detected message concurrency of the read master core being processed is greater than or equal to the first threshold value is greater than or equal to the second threshold value, the load state of the read master core is set to the first value corresponding to the high load state, so as to facilitate subsequent starting of at least one read backup core based on the high load state of the read master core.

[0016] With reference to the first aspect, in an optional implementation, the hard disk cache pre-stores a third variable value, and the third variable value is used to indicate the number of times that the detected message concurrency of the read master core being processed is less than a third threshold value; the third threshold value is less than the first threshold value; the method further includes: obtaining the third variable value in the process of performing read-write operations on the source data block and the target data block; if the third variable value is less than a second threshold value, detecting the message concurrency; if it is detected that the message concurrency is less than the third threshold value, the third variable value is incremented by one; and if it is detected that the message concurrency is greater than or equal to the third threshold value, the third variable value is cleared.

[0017] In the embodiment of the present application, the hard disk pre-stores the third variable value, and the number of times that the detected message concurrency of the read master core is less than the third threshold value is recorded, so that the value of the first variable value is determined based on the third variable value subsequently, to determine the load state of the read master core.

[0018] In combination with the first aspect, in an optional embodiment, the method further includes: if the obtained third variable value is greater than or equal to the second threshold value, setting the first variable value as the second value.

[0019] In the embodiment of the present application, when the number of times that the detected message concurrency of the read master core is less than the third threshold value is greater than or equal to the second threshold value, the load state of the read master core is set as the second value corresponding to the low load state, so that the at least one read standby core is stopped based on the low load state of the read master core subsequently.

[0020] In the second aspect, the present application provides a processor, the processor and the at least one read standby core belong to a hard disk controller; the processor includes: an acquisition module, configured to acquire a first variable value from a hard disk cache at a first time during a read-write operation on a source data block and a target data block, the first variable value being used to measure the load of the processor at the first time; and a processing module, configured to generate and send a request read message to the at least one read standby core if the first variable value at the first time is a first value, the request read message being used to instruct the at least one read standby core to start and assist the processor to perform the read-write operation on the source data block and the target data block, and the first value being used to indicate that the processor is in an overload state.

[0021] In the third aspect, the present application provides a computer device, including a memory and a processor, the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the data processing method of the first aspect or any of the corresponding embodiments thereof.

[0022] In the fourth aspect, the present application provides a computer readable storage medium, the computer readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute the data processing method of the first aspect or any of the corresponding embodiments thereof.

[0023] In the fifth aspect, the present application provides a computer program product, including computer instructions, and the computer instructions are used to make a computer execute the data processing method of the first aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a topology diagram of a data processing system according to an embodiment of the present invention;

[0026] Figure 2 This is a flowchart illustrating a data processing method according to an embodiment of the present invention;

[0027] Figure 3 This is a flowchart illustrating another data processing method according to an embodiment of the present invention;

[0028] Figure 4 This is a structural block diagram of a processor according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] This invention is applied to scenarios where solid-state drives (SSDs) require garbage collection, especially when the SSD controller is reading valid data from the source database containing the most garbage data.

[0032] Currently, during the garbage collection process of solid-state drives (SSDs), if the GC read processing core is occupied by other services or has insufficient performance while the SSD controller is reading valid data, it will cause the GC read processing core to read data slowly, affecting the performance of SSD services.

[0033] To address the aforementioned technical problems, this invention provides a data processing method that improves data reading speed by enabling a standby core to assist the main core in reading valid data while the main core is reading the data.

[0034] The following is based on Figure 1 Taking the data processing system 100 shown as an example, the method provided in the embodiments of this application will be described.Figure 1 It is only a schematic and does not limit the applicable scenarios of the technical solutions provided by the present application.

[0035] As Figure 1 shown, Figure 1 is a topological graph of a data processing system according to an embodiment of the present application. Figure 1 In the embodiment, the data processing system 100 can include a read master core 101, a read backup core 102, a write processing core 103, a control core 104, a flash memory controller 105, and a hard disk 106. The hard disk 106 includes a source data block 1061 and a target data block 1062.

[0036] The read master core 101, the read backup core 102, the write processing core 103, or the control core 104 in the embodiment of the present application can be any one processing core in a hard disk controller. It can be understood that the hard disk controller can further include more other processing cores.

[0037] The flash memory controller (Nand Flash Control, NFC) 105 in the embodiment of the present application is used to control scheduling read-write-erase operations of flash memory particles corresponding to the source data block or the write data block.

[0038] The source data block 1061 or the target data block 1062 in the embodiment of the present application can be any one data block in the hard disk 106. The flash memory controller 105 reads data from the source data block 1061. The write processing core 103 writes the read data into the target data block 1062.

[0039] Figure 1 The data processing system 10 shown is only used for example and is not used to limit the technical solutions of the present application. It should be understood by those skilled in the art that in the specific implementation process, the data processing system 10 can further include other read backup cores, and the number of read backup cores can also be determined according to specific needs, and is not limited.

[0040] According to the embodiment of the present application, a data processing method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0041] In the embodiment, a data processing method is provided, which can be used for the read master core, Figure 2 is a flowchart of a data processing method according to an embodiment of the present application, as Figure 2 shown, the flowchart includes the following steps:

[0042] S201: During the read and write operations on the source data block and the target data block, the first variable value is obtained from the disk cache at the first moment.

[0043] The first variable value can also be called the `gc_multi_flag` variable. The first variable value measures the load on the read core at the first moment. The first variable value can be either a first value or a second value. The first value indicates that the read core is in an overloaded state. The second value indicates that the read core is in a low-load state. For example, the first value can be 1, and the second value can be 0.

[0044] Understandably, the first variable value is pre-stored in the hard disk cache.

[0045] In some optional implementations, the read master core sequentially sends multiple read commands to the flash memory controller; sequentially receives multiple read messages returned from the flash memory controller, and sequentially sends the multiple read messages to the write processing core, so that the write processing core writes valid data into the target data block.

[0046] Each read command instructs the flash memory controller to read valid data from at least one address (e.g., a multiplane address) in the source data block, and based on the valid data, generates and returns a read message to the read master core.

[0047] Each read message includes multiple valid data entries.

[0048] For example, with Figure 1 For example, when the number of free data blocks in hard disk 106 is less than a preset threshold, control core 104 sends a first message to read master core 101, which instructs read master core 101 to start the GC read process. Read master core 101 receives the first message and begins to send multiple read commands to flash controller 105 sequentially; simultaneously, it sequentially receives multiple read messages returned from flash controller 106 and sends these messages sequentially to write processing core 103. Write processing core 103 writes valid data to target data block 1062.

[0049] In one example, the read master core receives multiple read messages returned from the flash memory controller and sends the multiple read messages to the write processing core in sequence. This includes: the read master core receiving multiple read messages returned from the flash memory controller, assembling the valid data included in the multiple read messages into the memory format required by the write processing core, and forwarding it to the write processing core according to the memory format.

[0050] The memory format can be wordline (WL) format. For example, a memory unit on a wordline can be organized into three independent pages.

[0051] S202: If the first variable value is the first value at the first time, a request read message is generated and sent to at least one read backup core.

[0052] The request read message is used to instruct the at least one read backup core to start and assist the read master core to perform read-write operations on the source data block and the target data block. The request read message carries N multi-plane addresses. The N multi-plane addresses are read addresses allocated by the read master core to the at least one read backup core.

[0053] The selection of N is related to the allocation mode of the GC read buff. If the GC read buff is managed by the read master core, N is as small as possible (for example, N is 2); if the GC read buff is managed by the NFC or the backup core, N can be larger (for example, N is 10).

[0054] In an example, the second variable value and the third variable value are pre-stored in the hard disk cache.

[0055] The second variable value is also referred to as a gc_rd_high_press_cnt variable. The second variable value is used to indicate the number of times that the detected message concurrency of the read master core being processed is greater than or equal to a first threshold value.

[0056] The third variable value is also referred to as a gc_rd_low_press_cnt variable. The third variable value is used to indicate the number of times that the detected message concurrency of the read master core being processed is less than a third threshold value.

[0057] The third threshold value is less than the first threshold value. The selection of the first threshold value and the third threshold value is related to the division of the data blocks in the hard disk. If each data block in the hard disk contains N physical lun, the first threshold value is 1.5 times of the maximum concurrency, that is, N x 1.5; and the third threshold value is one third of the first threshold value.

[0058] For example, if each data block in the hard disk contains 128 physical lun, the first threshold value is 192; and the third threshold value is 64.

[0059] In some optional embodiments, the read master core acquires the second variable value during the read-write operations on the source data block and the target data block; if the second variable value is less than a second threshold value, a first number of read commands that have been sent and have not received read information returned by the flash controller is detected, and a second number of read messages that have not been sent to the write processing core is detected; if the detected message concurrency is greater than or equal to a first threshold value, the second variable value is incremented by one; and if the detected message concurrency is less than the first threshold value, the second variable value is cleared.

[0060] The sum of the first number and the second number is the message concurrency.

[0061] For example, the read master core periodically acquires the second variable value at a preset interval during the read-write operation on the source data block and the target data block; if the second variable value is less than a second threshold, the message concurrency is detected, and if it is detected that the message concurrency is less than a first threshold, the second variable value is cleared.

[0062] The preset interval can be set according to actual needs. For example, the preset interval can be an interval at which the read master core sends 10 read commands.

[0063] In some optional embodiments, if the second variable value acquired by the read master core is greater than or equal to the second threshold, the first variable value is set to the first numerical value.

[0064] The second threshold can be set according to actual needs and is not limited. For example, the second threshold is 10.

[0065] It can be understood that if the second variable value (indicating that the message concurrency is greater than 192 times) acquired by the read master core is greater than or equal to the second threshold (indicating that 10 consecutive detections are made), it can be determined that the read master core is in a high-load state, and the first variable value corresponding to the load of the read master core can be set to the first numerical value.

[0066] In some optional embodiments, if the at least one read backup core receives the request read message sent by the read master core and reads the valid data on the N multi-plane addresses in the source data block based on the N multi-plane addresses carried by the request read message, the read master core again acquires the first variable value at a third time; if the first variable value at the third time is the first numerical value, a second request read message is generated and sent to the at least one read backup core.

[0067] The second request read message is used to instruct the at least one read backup core to continue assisting the read master core to perform the read-write operation on the source data block and the target data block. The second request read message carries other M multi-plane addresses in addition to the N multi-plane addresses. The M multi-plane addresses are read addresses allocated by the read master core to the at least one read backup core again.

[0068] It can be understood that when the first variable value acquired at the third time is the first numerical value, it indicates that the read master core is still in a high-load state, and at this time, the at least one read backup core has performed the read-write operation corresponding to the read addresses allocated by the read master core at the first time. Therefore, a second request read message needs to be sent again to instruct the at least one read backup core to continue assisting the read master core to perform the read-write operation on the source data block and the target data block, thereby improving the data read rate.

[0069] In some alternative embodiments, the read master core obtains the first variable value from the hard disk cache at a second time during the read-write operation on the source data block and the target data block; and sends a stop read message to the at least one read backup core if the first variable value is the second value at the second time.

[0070] The stop read message is used to instruct the at least one read backup core to stop. The second time is after the first time.

[0071] It can be understood that, after receiving the stop read message, the at least one read backup core no longer issues a read command to the flash controller, but still needs to read the read command from the source data block to the valid data returned to the write processing core. During the return of the valid data to the write processing core by the at least one read backup core, the at least one read backup core needs to return the valid data to the write processing core in the memory format required by the write processing core. If the last piece of valid data returned to the write processing core cannot be made into the memory format, the at least one read backup core needs to supplement "dummy" data to make the memory format returned to the write processing core.

[0072] In some alternative embodiments, the read master core obtains a third variable value during the read-write operation on the source data block and the target data block; detects the message concurrency if the third variable value is less than a second threshold value; increments the third variable value by one if the message concurrency is detected to be less than a third threshold value; and clears the third variable value if the message concurrency is detected to be greater than or equal to the third threshold value.

[0073] For example, the read master core periodically obtains a third variable value at a preset interval during the read-write operation on the source data block and the target data block; detects the message concurrency if the third variable value is less than a second threshold value; increments the third variable value by one if the message concurrency is detected to be less than a third threshold value; and clears the third variable value if the message concurrency is detected to be greater than or equal to the third threshold value.

[0074] In some alternative embodiments, the read master core sets the first variable value to the second value if the third variable value obtained by the read master core is greater than or equal to the second threshold value.

[0075] It can be understood that, if the second variable value (indicating that the message concurrency is less than 64 times) obtained by the read master core is greater than or equal to the second threshold value (indicating that 10 consecutive detections are detected), it can be determined that the read master core is in a low load state, and the first variable value corresponding to the load of the read master core can be set to the second value.

[0076] It can be understood that, in the case that all the GC reads on the flash memory positions of all the valid data in the source data block have been initiated and all the GC read messages are completed, it is considered that the current GC is completed, and a new GC process can be initiated on the next selected source data block.

[0077] Based on the above Figure 2 In the method, the read master core can obtain the first variable value from the hard disk cache at the first time point during the read-write operation on the source data block and the target data block, and if the first variable value is the first numerical value at the first time point, a request read message is generated and sent to at least one read standby core to instruct the at least one read standby core to start and assist the read master core to perform the read-write operation on the source data block and the target data block.

[0078] Since the first variable value is the first numerical value at the first time point, it indicates that the read master core is in an overload state at the first time point. At this time, the request read message is generated and sent to the at least one read standby core to start the at least one read standby core to assist the read master core to perform the read-write operation on the source data block and the target data block. That is, when the read master core has a large load in data processing or data read-write operation, the load of the read master core in data processing is shared by the at least one read standby core to achieve the goal of load balancing, and the problem of slow data reading speed caused by occupation of the read processing core by other services or insufficient performance during the hard disk garbage collection process is avoided, and the overall performance of the hard disk garbage collection is improved.

[0079] In this embodiment, another data processing method is provided, Figure 3 is a flowchart of another data processing method according to an embodiment of the present application, as shown in Figure 3 The flowchart includes the following steps:

[0080] When the number of idle available blocks in the hard disk is lower than the gc water line (i.e., the preset threshold), the read master core issues a GC read (i.e., a read command) to the NFC; the NFC returns a GC read completion (i.e., a read message) to the read master core. The read master core reads valid data to fill one WL data and initiates a GC write.

[0081] When the read master core detects that gc_multi_flag=0 and the number of concurrent messages is greater than or equal to 192 for 10 consecutive times, a request GC read message is issued to at least one read standby core; the at least one read standby core issues a GC read to the NFC; and the NFC returns multiple GC read completions to the at least one read standby core.

[0082] After the at least one read standby core executes the request read message, a request GC read completion message is returned to the read master core. The at least one read standby core reads valid data to fill one WL data and initiates a GC write.

[0083] When the read master core detects that gc_multi_flag=1 and the number of concurrent messages is less than or equal to 64 for 10 consecutive times, a request GC read stop message is issued to at least one read standby core. After the at least one read standby core supplements dummy data to the last read data, one WL data is filled and a GC write is initiated.

[0084] A processor is also provided in the embodiments, which is configured to implement the above-described embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0085] The embodiments provide a processor, as shown in Figure 4 Figure 4 is a structural block diagram of a processor according to an embodiment of the present application; the processor belongs to a hard disk controller with at least one reading backup core; the processor comprises:

[0086] The obtaining module 401 is configured to obtain a first variable value from the hard disk cache at a first time during the read-write operation on the source data block and the target data block, the first variable value being used to measure the load of the processor at the first time.

[0087] The processing module 402 is configured to generate and send a request reading message to the at least one reading backup core if the first variable value is a first numerical value at the first time, the request reading message being used to instruct the at least one reading backup core to start and assist the processor to perform the read-write operation on the source data block and the target data block, the first numerical value being used to indicate that the reading master core is in an overload state.

[0088] In some optional embodiments, the obtaining module 401 is configured to obtain the first variable value from the hard disk cache at a second time during the read-write operation on the source data block and the target data block, the second time being after the first time; and the processing module 402 is configured to send a stop reading message to the at least one reading backup core if the first variable value is a second numerical value at the second time, the stop reading message being used to instruct the at least one reading backup core to stop, the second numerical value being used to indicate that the processor is in a low-load state.

[0089] In some optional embodiments, the hard disk controller further comprises a writing processing core; and the processing module 402 is specifically configured to sequentially send a plurality of reading commands to the flash memory controller, each reading command being used to instruct the flash memory controller to read valid data of at least one address in the source data block, and generate and return a reading information to the processor based on the valid data; sequentially receive a plurality of reading information returned from the flash memory controller, and sequentially send the plurality of reading information to the writing processing core, so that the writing processing core writes the valid data into the target data block.

[0090] ​In some optional embodiments, the second variable value is pre-stored in the hard disk cache, and the second variable value is used to indicate the number of times that the detected message concurrency processed by the processor is greater than or equal to the first threshold value; the obtaining module 401 is further configured to obtain the second variable value during the read / write operation on the source data block and the target data block. The processing module 402 is further configured to, if the second variable value is less than a second threshold value, detect a first number of read commands that have been sent and for which read information returned by the flash controller has not been received, and detect a second number of read messages that have not been sent to the write processing core, and the sum of the first number and the second number is the message concurrency; if it is detected that the message concurrency is greater than or equal to the first threshold value, the second variable value is incremented by one; and if it is detected that the message concurrency is less than the first threshold value, the second variable value is cleared.

[0091] In some optional embodiments, the processing module 402 is further configured to, if the obtained second variable value is greater than or equal to the second threshold value, set the first variable value to the first numerical value.

[0092] In some optional embodiments, the third variable value is pre-stored in the hard disk cache, and the third variable value is used to indicate the number of times that the detected message concurrency processed by the processor is less than a third threshold value; the third threshold value is less than the first threshold value; the obtaining module 401 is further configured to obtain the third variable value during the read / write operation on the source data block and the target data block. The processing module 402 is further configured to, if the third variable value is less than the second threshold value, detect the message concurrency; if it is detected that the message concurrency is less than the third threshold value, the third variable value is incremented by one; and if it is detected that the message concurrency is greater than or equal to the third threshold value, the third variable value is cleared.

[0093] In some optional embodiments, the processing module 402 is further configured to, if the obtained third variable value is greater than or equal to the second threshold value, set the first variable value to the second numerical value.

[0094] Further function descriptions of the above-mentioned various modules and units are the same as those of the above-mentioned corresponding embodiments, and will not be described here again.

[0095] The processor in this embodiment is presented in the form of a functional unit. The unit herein refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory executing one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0096] The embodiment of the present application also provides a computer device having the above-mentioned Figure 4 processor.

[0097] Please refer to Figure 5 , which is a structural schematic diagram of a computer device provided by an optional embodiment of the present application, as shown inFigure 5 As shown, the computer device includes a multi-core processor 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with one another using different buses, and can be mounted on a common motherboard or other mounting arrangement as desired.

[0098] The multi-core processor 10 can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device, such as a display device coupled to the interface. In some alternative embodiments, the multi-core processor 10 and / or the plurality of buses can be used with multiple memories and multiple memory banks, if desired. Also, multiple computer devices can be connected, each device providing a portion of the necessary operations (e.g., as a server array, a group of blade servers, or a multi-processor system).

[0099] The multi-core processor 10 includes a plurality of cores or processing modules, such as a control core, a read master core, a write processing core, and a read standby core, as shown. Figure 1 The number of cores can be set according to actual needs, and the present embodiment does not limit this.

[0100] In addition, the multi-core processor 10 can also include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic gate array, a general array logic, or any combination thereof.

[0101] The memory 20 stores instructions executable by the multi-core processor 10, so that the multi-core processor 10 executes the method shown in the above embodiments.

[0102] The memory 20 can include a program storage area and a data storage area, wherein the program storage area can store an operating system, application programs required by at least one function; and the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some alternative embodiments, the memory 20 can optionally include a memory disposed remotely with respect to the multi-core processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0103] The memory 20 can include a volatile memory, such as a random access memory, and / or a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can also include a combination of the above-mentioned types of memories.

[0104] The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

[0105] The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0106] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the existence form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc. Correspondingly, the execution mode of computer program instructions by computer includes but is not limited to: the computer directly executes the instructions, or the computer executes the corresponding compiled program after compiling the instructions, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0107] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A data processing method, characterized by, The application is applied to a read master core of a hard disk controller, the hard disk controller further comprising at least one read backup core; the method comprising: sending multiple read commands to a flash memory controller in sequence, each read command being used to instruct the flash memory controller to read valid data of at least one address in a source data block, and based on the valid data, generating and returning a read information to the read master core; a second variable value is pre-stored in a hard disk cache, the second variable value being used to indicate a number of times that a detected message concurrency of the read master core being processed is greater than or equal to a first threshold value; the second variable value is acquired during a read-write operation on the source data block and a target data block; if the second variable value is less than a second threshold value, a first number of read commands that have been sent and have not received the read information returned by the flash memory controller is detected, and a second number of read information that has not been sent to a write processing core is detected, a sum of the first number and the second number being the message concurrency; if it is detected that the message concurrency is greater than or equal to the first threshold value, the second variable value is incremented by one; if it is detected that the message concurrency is less than the first threshold value, the second variable value is cleared; if the acquired second variable value is greater than or equal to the second threshold value, a first variable value is set to a first numerical value; a third variable value is pre-stored in the hard disk cache, the third variable value being used to indicate a number of times that a detected message concurrency of the read master core being processed is less than a third threshold value, the first threshold value and the third threshold value being associated with division of data blocks in the hard disk; the third threshold value is less than the first threshold value; the method further comprises: acquiring the third variable value during the read-write operation on the source data block and the target data block; if the third variable value is less than the second threshold value, the message concurrency is detected; if it is detected that the message concurrency is less than the third threshold value, the third variable value is incremented by one; if it is detected that the message concurrency is greater than or equal to the third threshold value, the third variable value is cleared; if the acquired third variable value is greater than or equal to the second threshold value, the first variable value is set to a second numerical value, the second numerical value being used to indicate that the read master core is in a low load state; during the read-write operation on the source data block and the target data block, the first variable value is acquired from the hard disk cache at a first time, the first variable value being used to measure a load of the read master core at the first time; if the first variable value is the first numerical value at the first time, a request read message is generated and sent to the at least one read backup core, the request read message being used to instruct the at least one read backup core to start and assist the read master core to perform the read-write operation on the source data block and the target data block, the first numerical value being used to indicate that the read master core is in an overload state.

2. The method of claim 1, wherein, the method further comprises: during the read-write operation on the source data block and the target data block, the first variable value is acquired from the hard disk cache at a second time, the second time being after the first time; If the first variable value is a second numerical value at the second time, a stop reading message is sent to the at least one reading standby core, and the stop reading message is used to instruct the at least one reading standby core to stop.

3. The method of claim 2, wherein, The hard disk controller further comprises a write processing core; and the read-write operation on the source data block and the target data block comprises: The multiple pieces of read information returned by the flash memory controller are received in sequence, and the multiple pieces of read information are sent to the write processing core in sequence, so that the write processing core writes the valid data into the target data block.

4. A processor, comprising: The processor and the at least one reading standby core belong to a hard disk controller; and the processor comprises: The processing module is configured to send multiple read commands to the flash memory controller in sequence, each read command is used to instruct the flash memory controller to read valid data of at least one address in a source data block, and based on the valid data, generate and return a piece of read information to the reading master core; The second variable value is pre-stored in the hard disk cache, the second variable value is used to indicate the number of times that the detected message concurrency of the reading master core being processed is greater than or equal to a first threshold value; the obtaining module is configured to obtain the second variable value in the read-write operation on the source data block and the target data block; and the processing module is further configured to, if the second variable value is less than a second threshold value, detect a first number of read commands that have been sent and for which the read information returned by the flash memory controller has not been received, and detect a second number of read information that has not been sent to the write processing core, and the sum of the first number and the second number is the message concurrency; if it is detected that the message concurrency is greater than or equal to the first threshold value, the second variable value is incremented by one; and if it is detected that the message concurrency is less than the first threshold value, the second variable value is cleared. The processing module is further configured to, if the obtained second variable value is greater than or equal to the second threshold value, set a first variable value as a first numerical value. The third variable value is pre-stored in the hard disk cache, the third variable value is used to indicate the number of times that the detected message concurrency of the reading master core being processed is less than a third threshold value, the selection of the first threshold value and the third threshold value is associated with the division of data blocks in the hard disk; the third threshold value is less than the first threshold value; the obtaining module is further configured to obtain the third variable value in the read-write operation on the source data block and the target data block; and the processing module is further configured to, if the third variable value is less than the second threshold value, detect the message concurrency; if it is detected that the message concurrency is less than the third threshold value, the third variable value is incremented by one; and if it is detected that the message concurrency is greater than or equal to the third threshold value, the third variable value is cleared. The processing module is further configured to, if the obtained third variable value is greater than or equal to the second threshold value, set the first variable value as a second numerical value, and the second numerical value is used to indicate that the reading master core is in a low load state. The acquisition module is configured to acquire the first variable value from the hard disk cache at a first time point during a read-write operation on a source data block and a target data block, the first variable value being used to measure a load of the processor at the first time point; The processing module is configured to generate and send a request read message to the at least one read standby core if the first variable value at the first time point is a first numerical value, the request read message being used to instruct the at least one read standby core to start and assist the processor to perform the read-write operation on the source data block and the target data block, the first numerical value being used to indicate that the processor is in an overload state.

5. A computer device, comprising: The data processing method comprises the following steps: A memory and a processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the data processing method of any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute the data processing method of any one of claims 1 to 3.

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