Arbitrary number system calculation method, device, equipment, medium and product
By mapping the target address to multiple sub-memory and rearranging the data using the cross switch matrix, the problem of waste of resources and high communication costs during wider bit width calculation in the prior art is solved, and efficient wider bit width calculation is achieved.
Patent Information
- Application Number
- CN202411656165.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-04-15
AI Technical Summary
When processing wider bit width calculations, the prior art needs to increase the data bit width of the storage structure or use registers, resulting in waste of resources and increased communication costs.
By mapping the target address to the sub-store physical addresses of multiple sub-memorys and rearranging the initial read data using the cross-switch matrix, the target read data is obtained, so that the calculation of the wider bit width number system is completed without changing the bit width of the storage structure data and without using registers.
It realizes the calculation of a wider bit width system while keeping the memory structure access bit width unchanged, reducing resource waste and communication costs.
Smart Images
Figure CN119829127A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to an arbitrary number system calculation method, device, equipment, medium and product. Background Art
[0002] Multithreading refers to the technology of implementing multiple threads concurrently in software or hardware. A computer with multithreading capability can execute more than one thread at the same time due to hardware support, which enables it to process information faster and thus improve overall processing performance.
[0003] The calculation process of a multi-threaded processor usually reads the data to be calculated from the storage structure and then sends it to the calculator for calculation. The storage structure has a fixed read data bit width, which matches the main number system calculation path. For example, in a 16-thread 16-bit half-precision floating-point (fp16) processor, this bit width is usually 16*16=256 bits. When the processor is expected to support wider number system calculations, the read data bit width of the storage structure no longer matches the data bit width required for calculation. To solve this problem, the existing technology mainly has the following two processing solutions: 1) Increase the data bit width of the storage structure. In this case, the main number system calculation only uses half or less of the read port resources; 2) Read out the data of the data bit width required for calculation in multiple times, store the data read out last time in the register, and then obtain part of the data from the storage structure and obtain another part of the data from the register for number system calculation.
[0004] However, with respect to the above two prior arts, the former wastes read port resources, and the latter requires the arrangement of registers, both of which cause waste of resources and increase communication costs. Summary of the invention
[0005] The present invention provides an arbitrary number system calculation method, device, equipment, medium and product, which are used to solve the defects in the prior art of increasing the data bit width of the storage structure or adding registers to waste resources and increase communication costs. The technical solution of the present invention can complete the calculation of a wider bit width number system while keeping the data bit width of the storage structure unchanged and without setting registers, thereby reducing resource waste and communication costs.
[0006] The present invention provides an arbitrary number system calculation method, comprising the following steps.
[0007] When receiving a calculation instruction of a target number system, mapping at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; For each of the target addresses, based on a plurality of sub-storage physical addresses corresponding to the target address, determining the target read data corresponding to the target address; Based on the target read data corresponding to each of the target addresses, a target calculation result of the target number system is determined.
[0008] According to an arbitrary number system calculation method provided by the present invention, determining the target read data corresponding to the target address based on the multiple sub-storage physical addresses corresponding to the target address includes: Acquire initial read data corresponding to the target address from a plurality of sub-storage physical addresses corresponding to the target address; Based on the crossbar switch matrix, the initial read data is rearranged to obtain target read data corresponding to the target address.
[0009] According to an arbitrary number system calculation method provided by the present invention, the initial read data is rearranged based on a crossbar switch matrix to obtain target read data corresponding to the target address, including: Based on the crossbar switch matrix, a plurality of sub-data in the initial read data are reordered according to a thread sequence to obtain the target read data corresponding to the target address.
[0010] According to an arbitrary number system calculation method provided by the present invention, determining the target calculation result of the target number system based on the target read data corresponding to each target address includes: Sending the target read data corresponding to each of the target addresses to a number system calculator, the number system calculator being used to calculate and determine the target calculation result of the target number system based on each of the target read data; Receive the target calculation result of the target number system sent by the number system calculator.
[0011] According to an arbitrary number system calculation method provided by the present invention, the number system calculator includes a main number system calculator and an expected number system calculator; the method further includes: In the case where the bit width of the target number system is the bit width of the main number system, the target read data corresponding to each target address is sent to the main number system calculator, and the target calculation result sent by the main number system calculator is received; or
[0012] In the case where the bit width of the target number system is the bit width of the maximum supported calculation number system, the target read data corresponding to each target address is sent to the expected number system calculator, and the target calculation result sent by the expected number system calculator is received.
[0013] According to an arbitrary number system calculation method provided by the present invention, the number of the sub-memories is the quotient of the maximum supported calculation number system bit width and the main number system bit width.
[0014] The present invention also provides an arbitrary number system calculation device, comprising the following modules: A mapping module, configured to, upon receiving a calculation instruction of a target number system, map at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; A storage module, configured to determine, for each of the target addresses, target read data corresponding to the target address based on a plurality of sub-storage physical addresses corresponding to the target address; The calculation module is used to determine the target calculation result of the target number system based on the target read data corresponding to each of the target addresses.
[0015] The present invention also provides an electronic device, comprising a sub-memory, a processor, and a computer program stored in the sub-memory and executable on the processor, wherein when the processor executes the computer program, any of the above-mentioned arbitrary number system calculation methods is implemented.
[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the arbitrary number system calculation method described in any one of the above is implemented.
[0017] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned arbitrary number system calculation methods.
[0018] The arbitrary number system calculation method, device, equipment, medium and product provided by the present invention, when receiving the calculation instruction of the target number system, maps at least one target address corresponding to the calculation instruction to the sub-storage physical address of the corresponding sub-memory according to the address remapping rule; wherein the number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; for each target address, based on the multiple sub-storage physical addresses corresponding to the target address, the target read data corresponding to the target address is determined; based on the target read data corresponding to each target address, the target calculation result of the target number system is determined. In the technical solution of the present invention, the storage structure adopts multiple sub-memories, and the number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width, and then the target address is mapped to the sub-storage physical address of the corresponding sub-memory, and the target read data is obtained, and the target calculation result is further obtained. It can complete the calculation of the wider bit width number system while keeping the access bit width of the storage structure unchanged and without setting registers, thereby reducing resource waste and communication costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0020] Figure 1 It is one of the flow charts of the arbitrary number system calculation method provided by the present invention.
[0021] Figure 2 This is the second flow chart of the arbitrary number system calculation method provided by the present invention.
[0022] Figure 3 It is a schematic diagram of the structure of the arbitrary number system calculation device provided by the present invention.
[0023] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0025] In view of the above problems in the prior art, the present invention provides an arbitrary number system calculation method. The execution subject of the method of the present invention may be a storage structure or other subjects. The embodiments of the present invention are not specifically limited. The following embodiments are described with the storage structure as the execution subject. Figure 1 It is one of the flow charts of the arbitrary number system calculation method provided by the present invention, such as Figure 1 As shown, the method includes the following steps 110, 120 and 130.
[0026] Step 110: When receiving a calculation instruction of a target number system, map at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system.
[0027] Specifically, when receiving a calculation instruction of a target number system sent by the controller, at least one target address corresponding to the calculation instruction can be mapped to a sub-storage physical address of a sub-memory corresponding to each target address according to an address remapping rule. Among them, the address remapping rule can be set in advance as needed, and the embodiment of the present invention does not make specific restrictions here. The number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system. The main number system bit width is the bit width corresponding to the number system for main calculation, and the maximum supported calculation number system bit width is the number system bit width expected to be calculated. It should be noted that the maximum supported calculation number system bit width is greater than the read port bit width and the main number system bit width of the storage structure. For example, the main number system bit width is 256 bits, the read port bit width of the storage structure is also 256 bits, and the maximum supported calculation number system bit width can be 512 bits or 1024 bits. The main number system bit width is 128 bits, and the read port bit width of the storage structure is also 128 bits. The maximum supported calculation number system bit width can be 256 bits, 512 bits, or 1024 bits. Since the maximum supported calculation number system bit width and the main number system bit width can be set as needed, the present invention can perform calculations in any number system.
[0028] It should be noted that the number of physical addresses in the sub-memory (ie, the storage depth) can be set as needed, and the embodiment of the present invention does not make any specific limitation here.
[0029] For example, Figure 2 This is the second flow chart of the arbitrary number system calculation method provided by the present invention, such as Figure 2As shown, sub-memory 1 and sub-memory 2 each have 8 physical addresses, and the first to last rows of sub-memory 1 and sub-memory 2 correspond to the first physical address, the second physical address, the third physical address, the fourth physical address, the fifth physical address, the sixth physical address, the seventh physical address, and the eighth physical address, respectively. Assume that the storage structure read port width is 256 bits, the main number system width is 256 bits, and the maximum supported computing number system width is 512 bits. When the bit width of the target number system is 256, and the computing instruction indicates to calculate addr0+1, the target address corresponding to the computing instruction is addr0. Then, according to the address remapping rule, the address addr0 of thread 0-thread 7 is mapped to the first physical address in sub-memory 1, and the address addr0 of thread 8-thread 15 is mapped to the fifth physical address in sub-memory 2. When the bit width of the target number system is 512 bits, and the calculation instruction indicates to calculate the concatenation result of addr0 and addr1 + 1, the target address corresponding to the calculation instruction is addr0 and addr1. Then, according to the address remapping rule, the address addr0 of thread 0-thread 7 is mapped to the first physical address in sub-memory 1, the address addr0 of thread 8-thread 15 is mapped to the fifth physical address in sub-memory 2, the address addr1 of thread 0-thread 7 is mapped to the first physical address in sub-memory 2, and the address addr1 of thread 8-thread 15 is mapped to the fifth physical address in sub-memory 1.
[0030] Step 120: For each of the target addresses, based on a plurality of sub-storage physical addresses corresponding to the target address, determine the target read data corresponding to the target address.
[0031] Specifically, for each target address, the target read data corresponding to the target address can be determined based on a plurality of sub-storage physical addresses corresponding to the target address. It is easy to understand that the target address corresponds to the target read data one by one.
[0032] In one embodiment, the number of the sub-memories is the quotient of the maximum supported computing number system bit width and the main number system bit width.
[0033] Specifically, the maximum supported computing number system bit width can be divided by the main number system bit width to obtain the number of sub-memories. For example, if the maximum supported computing number system bit width is 512 bits and the main number system bit width is 256 bits, then the number of sub-memories can be determined to be 2. In addition, the read port bit width of a single sub-memory is the main number system bit width divided by the number of sub-memories. For example, if the main number system bit width is 256 bits and the number of sub-memories is 2, then the read port bit width of a single sub-memory is 128 bits.
[0034] In the above example, the quotient of the maximum supported computing number system bit width and the main number system bit width is determined as the number of sub-memories, and the read data can be output through multiple sub-memories, which facilitates subsequent calculations.
[0035] In one embodiment, determining the target read data corresponding to the target address based on the multiple sub-storage physical addresses corresponding to the target address includes: Acquire initial read data corresponding to the target address from a plurality of sub-storage physical addresses corresponding to the target address; Based on the crossbar switch matrix, the initial read data is rearranged to obtain target read data corresponding to the target address.
[0036] Specifically, the initial read data corresponding to the target address can be obtained from multiple sub-storage physical addresses corresponding to the target address, but the order of the sub-data in the initial read data may be wrong. Therefore, it is necessary to rearrange each initial read data based on the cross-switch matrix to obtain the target read data corresponding to each initial read data. The initial read data corresponding to the target address represents the same address data. For example, when the calculation instruction of the target number system indicates to calculate addr0+1, the calculation is a main number system calculation, so the target address is also only addr0, and the initial read data corresponding to the target address is the data corresponding to addr0. When the calculation instruction of the target number system indicates to calculate the concatenation result of addr0 and addr1+1, the target address includes addr0 and addr1, then one initial read data is the data corresponding to addr0, and the other initial read data is the data corresponding to addr1. It should be noted that the setting of the cross-switch matrix is related to the number of sub-memories and the number of calculators. If the number of sub-memories is 2 and the number of calculators is also 2, then the cross-switch matrix is as follows Figure 2 As shown, a 2 to 2 crossbar switch matrix.
[0037] In the above embodiment, the initial read data corresponding to the multiple target addresses can be accurately obtained based on the multiple sub-storage physical addresses of each sub-memory, and then the initial read data are rearranged based on the cross switch matrix, so that the target read data can be suitable for calculation of the subsequent calculator.
[0038] In one embodiment, the reordering of the initial read data based on the crossbar switch matrix to obtain the target read data corresponding to the target address includes: Based on the crossbar switch matrix, a plurality of sub-data in the initial read data are reordered according to a thread sequence to obtain the target read data corresponding to the target address.
[0039] Specifically, the initial read data includes multiple sub-data. For each initial read data, the multiple sub-data in the initial read data can be reordered according to the thread sequence based on the crossbar switch matrix to obtain the target read data corresponding to the initial read data.
[0040] For example, refer to Figure 2 , when the calculation instruction of the target number system indicates to calculate the concatenation result of addr0 and addr1 + 1, the target address corresponding to the target number system is addr0 and addr1, then according to the address remapping rule, the address addr0 of thread 0-thread 7 is mapped to the first physical address in sub-memory 1, the address addr0 of thread 8-thread 15 is mapped to the fifth physical address in sub-memory 2, the address addr1 of thread 0-thread 7 is mapped to the first physical address in sub-memory 2, and the address addr1 of thread 8-thread 15 is mapped to the fifth physical address in sub-memory 1, and then the data of address addr0 of thread 0-thread 7 can be obtained from the first physical address of sub-memory 1, and the data of address addr0 of thread 0-thread 7 can be obtained from the fifth physical address of sub-memory 1. The data of address addr1 of thread 8-thread 15 is obtained, the data of address addr1 of thread 0-thread 7 is obtained from the first physical address of sub-memory 2, and the data of address addr0 of thread 8-thread 15 is obtained from the fifth physical address of sub-memory 2. In this case, the output order of the physical addresses is the data of address addr0 of thread 0-thread 7, the data of address addr1 of thread 8-thread 15, the data of address addr1 of thread 0-thread 7 and the data of address addr0 of thread 8-thread 15. The output order of sub-data in the initial read data corresponding to the target address addr0 itself conforms to the thread order. Therefore, the initial read data is correct and does not need to be rearranged. That is, the initial read data is directly determined as the target read data. The output order of the sub-data in the initial read data corresponding to the target address addr1 is first the data of address addr1 of thread 8-thread 15, and then the data of address addr1 of thread 0-thread 7. To ensure the correctness of subsequent calculations, the data corresponding to the low thread (i.e., thread 0-thread 7) should be in front, and the data corresponding to the high thread (i.e., thread 8-thread 15) should be in the back. Therefore, it is necessary to use the crossbar switch matrix to rearrange the data of address addr1 of thread 0-thread 7 in front and the data of address addr1 of thread 8-thread 15 in the back.
[0041] In the above embodiment, based on the crossbar switch matrix, multiple sub-data in the initial read data are reordered according to the thread order to obtain the target read data corresponding to the target address, so that the target read data conforms to the thread order, ensuring the reliability of subsequent calculation results.
[0042] Step 130: Determine the target calculation result of the target number system based on the target read data corresponding to each of the target addresses.
[0043] In one embodiment, determining the target calculation result of the target number system based on the target read data corresponding to each of the target addresses includes: Sending the target read data corresponding to each of the target addresses to a number system calculator, the number system calculator being used to calculate and determine the target calculation result of the target number system based on each of the target read data; Receive the target calculation result of the target number system sent by the number system calculator.
[0044] Specifically, the target read data corresponding to each target address can be sent to a number system calculator, which is used to calculate and determine the target calculation result of the target number system based on each target read data, and then the number system calculator can write the target calculation result back to the storage structure, and the storage structure can receive the target calculation result of the target number system sent by the number system calculator. The number system calculator can also be a number system calculation unit, or a number system calculation circuit.
[0045] It should be noted that there may be one or more number calculators, and the number of calculation threads and thread bit width of the number calculator may also be set as needed. The embodiment of the present invention does not make specific limitations here. For example, the number calculator may include a 16-by-fp16 number calculator, or an 8-by-fp32 number calculator. Each target read data may be input into the number calculator, and the target calculation results corresponding to each target read data output by the number calculator may be obtained. After obtaining the target calculation results, the target calculation results may also be written back to the storage structure.
[0046] In the above embodiment, the target read data corresponding to each target address is sent to the digital calculator, so that the digital calculator can output the target calculation result according to the target read data corresponding to each target address.
[0047] In one embodiment, the number system calculator includes a main number system calculator and a desired number system calculator; the method further includes: In the case where the bit width of the target number system is the bit width of the main number system, the target read data corresponding to each target address is sent to the main number system calculator, and the target calculation result sent by the main number system calculator is received; or
[0048] In the case where the bit width of the target number system is the bit width of the maximum supported calculation number system, the target read data corresponding to each target address is sent to the expected number system calculator, and the target calculation result sent by the expected number system calculator is received.
[0049] Specifically, when the bit width of the target number system is the bit width of the main number system, that is, when the calculation instruction indicates to perform main number system calculation, each target read data can be sent to the main number system calculator to obtain the target calculation result output by the main number system calculator. The main number system calculator calculates the target read data respectively, and the obtained target calculation result corresponds to the target read data.
[0050] When the bit width of the target number system is the maximum supported calculation number system bit width, that is, the calculation instruction instructs to perform expected number system calculation, each target read data is sent to the expected number system calculator to obtain the target calculation result output by the expected number system calculator. It should be noted that, when the target number system calculation instruction instructs to perform expected number system calculation, after the target read data is input into the expected number system calculator, the expected number system unit calculates the target read data according to the thread rather than the address, and the obtained target calculation result does not correspond one-to-one to the target read data.
[0051] Exemplarily, the maximum supported calculation number system bit width is 512 bits, the main number system bit width is 256 bits, the main number system calculator is a 16 times fp16 number system calculator, the expected number system calculator is an 8 times fp32 number system calculator, and when the target number system bit width is 256 bits of the main number system bit width, and the calculation instruction indicates to calculate addr0+1, the data bit width of addr0+1 is 256 bits, and there is only one target read data, so the calculation can be performed through the main number system calculator (16 times fp16 number system calculator). In the case where the bit width of the target number system is 512 bits, the maximum supported calculation number system bit width, and the calculation instruction indicates to calculate the splicing result of addr0 and addr1 + 1, the data bit width of the splicing result of addr0 and addr1 + 1 is 512 bits, so it is necessary to obtain the target calculation result based on all the target read data through the expected number system calculator (8 times fp32 number system calculator), and the target calculation result includes two sub-calculation results, that is, one sub-calculation result is the calculation result corresponding to thread 0-thread 7, and the other sub-calculation result is the calculation result corresponding to thread 8-thread 15, and both sub-calculation results are 256 bits, and the two sub-calculation results can be written back to the storage structure. In the above manner, the present invention can complete a total of 512 bits of calculation by using 8 times fp32 number system calculators.
[0052] In the above embodiment, when the bit width of the target number system is a bit width of a different number system, the target read data is sent to calculators of different number systems, which can ensure that the calculation of the desired number system is completed.
[0053] The arbitrary number system calculation method provided by the present invention, when receiving the calculation instruction of the target number system, maps at least one target address corresponding to the calculation instruction to the sub-storage physical address of the corresponding sub-memory according to the address remapping rule; wherein the number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; for each target address, based on the multiple sub-storage physical addresses corresponding to the target address, the target read data corresponding to the target address is determined; based on the target read data corresponding to each target address, the target calculation result of the target number system is determined. In the technical solution of the present invention, the storage structure adopts multiple sub-memories, and the number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width, and then the target address is mapped to the sub-storage physical address of the corresponding sub-memory, and the target read data is obtained, and the target calculation result is further obtained. The calculation of a wider bit width number system can be completed while keeping the access bit width of the storage structure unchanged and without setting registers, thereby reducing resource waste and communication costs.
[0054] In addition, there is also a method in the prior art to split a single number system calculation into multiple small bit width calculations. For example, if the target number system is 512 bits, and the calculation instruction of the target number system indicates to calculate the concatenation result of addr0 and addr1 + 1, the target address corresponding to the target number system is addr0 and addr1. The prior art first calculates the first data corresponding to the address addr0 of thread 0-thread 15 (the first data is 256 bits), and then calculates the second data corresponding to the address addr1 of thread 0-thread 15 (the second data is 256 bits), and further calculates the concatenation result of addr0 and addr1 + 1, and then performs multiple calculations based on the first data and the second data to obtain the result of the target number system. The complexity of the prior art is relatively high, and in calculations related to floating-point numbers, it is also difficult to split a single number system calculation into multiple small bit width calculations.
[0055] The arbitrary number system calculation device provided by the present invention is described below. The arbitrary number system calculation device described below and the arbitrary number system calculation method described above can be referenced to each other.
[0056] Figure 3 is a schematic diagram of the structure of the arbitrary number system calculation device provided by the present invention, such as Figure 3 As shown, the arbitrary number system calculation device 300 includes the following modules: A mapping module 310 is used for, when receiving a calculation instruction of a target number system, mapping at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; The storage module 320 is used to determine, for each of the target addresses, target read data corresponding to the target address based on a plurality of sub-storage physical addresses corresponding to the target address; The calculation module 330 is used to determine the target calculation result of the target number system based on the target read data corresponding to each of the target addresses.
[0057] In one embodiment, the storage module 320 is specifically used for: Acquire initial read data corresponding to the target address from a plurality of sub-storage physical addresses corresponding to the target address; Based on the crossbar switch matrix, the initial read data is rearranged to obtain target read data corresponding to the target address.
[0058] In one embodiment, the storage module 320 is further configured to: Based on the crossbar switch matrix, a plurality of sub-data in the initial read data are reordered according to a thread sequence to obtain the target read data corresponding to the target address.
[0059] In one embodiment, the calculation module 330 is specifically used for: Sending the target read data corresponding to each of the target addresses to a number system calculator, the number system calculator being used to calculate and determine the target calculation result of the target number system based on each of the target read data; Receive the target calculation result of the target number system sent by the number system calculator.
[0060] In one embodiment, the number system calculator includes a main number system calculator and an expected number system calculator, and the calculation module 330 is further used for: In the case where the bit width of the target number system is the bit width of the main number system, the target read data corresponding to each target address is sent to the main number system calculator, and the target calculation result sent by the main number system calculator is received; or
[0061] In the case where the bit width of the target number system is the bit width of the maximum supported calculation number system, the target read data corresponding to each target address is sent to the expected number system calculator, and the target calculation result sent by the expected number system calculator is received.
[0062] In one embodiment, the number of the sub-memories is the quotient of the maximum supported computing number system bit width and the main number system bit width.
[0063] The arbitrary number system calculation device provided by the present invention, when receiving the calculation instruction of the target number system, maps at least one target address corresponding to the calculation instruction to the sub-storage physical address of the corresponding sub-memory according to the address remapping rule; wherein the number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; for each target address, based on the multiple sub-storage physical addresses corresponding to the target address, the target read data corresponding to the target address is determined; based on the target read data corresponding to each target address, the target calculation result of the target number system is determined. In the technical solution of the present invention, the storage structure adopts multiple sub-memories, and the number of sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width, and then the target address is mapped to the sub-storage physical address of the corresponding sub-memory, and the target read data is obtained, and the target calculation result is further obtained. It can complete the calculation of the wider bit width number system while keeping the access bit width of the storage structure unchanged and without setting registers, thereby reducing resource waste and communication costs.
[0064] Figure 4 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 4 As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420 and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute an arbitrary number system calculation method, which includes: When receiving a calculation instruction of a target number system, mapping at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; For each of the target addresses, based on a plurality of sub-storage physical addresses corresponding to the target address, determining the target read data corresponding to the target address; Based on the target read data corresponding to each of the target addresses, a target calculation result of the target number system is determined.
[0065] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.
[0066] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can perform the arbitrary number system calculation method provided by the above methods, the method comprising: When receiving a calculation instruction of a target number system, mapping at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; For each of the target addresses, based on a plurality of sub-storage physical addresses corresponding to the target address, determining the target read data corresponding to the target address; Based on the target read data corresponding to each of the target addresses, a target calculation result of the target number system is determined.
[0067] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to perform the arbitrary number system calculation method provided by the above methods, the method comprising: When receiving a calculation instruction of a target number system, mapping at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; For each of the target addresses, based on a plurality of sub-storage physical addresses corresponding to the target address, determining the target read data corresponding to the target address; Based on the target read data corresponding to each of the target addresses, a target calculation result of the target number system is determined.
[0068] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0069] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for calculating arbitrary numbers, characterized in that: include: When receiving a calculation instruction of a target number system, mapping at least one target address corresponding to the calculation instruction to a sub-storage physical address of each sub-memory according to an address remapping rule; wherein the number of the sub-memory is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; For each of the target addresses, based on a plurality of sub-storage physical addresses corresponding to the target address, determining the target read data corresponding to the target address; Based on the target read data corresponding to each of the target addresses, a target calculation result of the target number system is determined.
2. The arbitrary number system calculation method according to claim 1, characterized in that: The determining the target read data corresponding to the target address based on the multiple sub-storage physical addresses corresponding to the target address includes: Acquire initial read data corresponding to the target address from a plurality of sub-storage physical addresses corresponding to the target address; Based on the crossbar switch matrix, the initial read data is rearranged to obtain target read data corresponding to the target address.
3. The arbitrary number system calculation method according to claim 2, characterized in that: The step of rearranging the initial read data based on the crossbar switch matrix to obtain target read data corresponding to the target address includes: Based on the crossbar switch matrix, a plurality of sub-data in the initial read data are reordered according to a thread sequence to obtain the target read data corresponding to the target address.
4. The arbitrary number system calculation method according to claim 1, characterized in that: The step of determining the target calculation result of the target number system based on the target read data corresponding to each of the target addresses comprises: Sending the target read data corresponding to each of the target addresses to a number system calculator, the number system calculator being used to calculate and determine the target calculation result of the target number system based on each of the target read data; Receive the target calculation result of the target number system sent by the number system calculator.
5. The arbitrary number system calculation method according to claim 4, characterized in that: The number system calculator at least includes a main number system calculator and a desired number system calculator; the method further includes: In the case where the bit width of the target number system is the bit width of the main number system, the target read data corresponding to each target address is sent to the main number system calculator, and the target calculation result sent by the main number system calculator is received; or In the case where the bit width of the target number system is the bit width of the maximum supported calculation number system, the target read data corresponding to each target address is sent to the expected number system calculator, and the target calculation result sent by the expected number system calculator is received.
6. The arbitrary number system calculation method according to any one of claims 1 to 5, characterized in that: The number of the sub-memories is the quotient of the maximum supported computing number system bit width and the main number system bit width.
7. An arbitrary number system calculation device, characterized in that: include: A mapping module, configured to, upon receiving a calculation instruction of a target number system, map at least one target address corresponding to the calculation instruction to a sub-storage physical address of a corresponding sub-memory according to an address remapping rule; wherein the number of the sub-memories is determined based on the maximum supported calculation number system bit width and the main number system bit width corresponding to the target number system; A storage module, configured to determine, for each of the target addresses, target read data corresponding to the target address based on a plurality of sub-storage physical addresses corresponding to the target address; The calculation module is used to determine the target calculation result of the target number system based on the target read data corresponding to each of the target addresses.
8. An electronic device comprising a sub-memory, a processor, and a computer program stored in the sub-memory and executable on the processor, characterized in that: When the processor executes the computer program, the arbitrary number system calculation method according to any one of claims 1 to 6 is implemented.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the arbitrary number system calculation method according to any one of claims 1 to 6 is implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the arbitrary number system calculation method according to any one of claims 1 to 6 is implemented.