Double-write-back embedded scalar processor micro-architecture

Abstract

The invention discloses a double-write-back embedded scalar processor micro-architecture, which belongs to the technical field of embedded scalar processors, and comprises an arbitration component for arbitrating a program counter value flowing into an assembly line; the instruction fetching part is used for acquiring instruction data; the decoding component is used for acquiring a memory access operation code and a memory access operand when the instruction is a memory access instruction, and acquiring a non-memory access operation code and a non-memory access operand when the instruction is a non-memory access instruction; the execution component is used for calculating a memory access address according to the memory access operand; executing the non-memory access instruction according to the non-memory access operation code and the non-memory access operand to obtain a non-memory access instruction execution result; the memory access component is used for executing the memory access instruction according to the memory access operation code and the memory access address to obtain memory access data; and the write-back component is used for executing write-back operation of the memory access instruction and / or the non-memory access instruction according to the memory access data and / or the non-memory access instruction. According to the double-write-back embedded scalar processor micro-architecture, the performance, reliability and flexibility of an embedded scalar processor can be improved, and power consumption can be reduced.

Description

Technical Field

[0001] The invention relates to a dual write-back embedded scalar processor micro-architecture, belonging to the technical field of embedded scalar processors. Background Art

[0002] At present, the design of embedded scalar processors mainly focuses on improving performance, reducing power consumption and reducing chip area, etc. The performance and efficiency of processors are continuously improved by adopting advanced semiconductor processes, optimizing processor architecture and instruction sets, etc.

[0003] In terms of microarchitecture, some embedded scalar processors use a simple dynamic submission mechanism, which can improve the performance and reliability of the processor to a certain extent.

[0004] However, these existing technologies still have some shortcomings when facing complex application scenarios: (1) Limited performance: Existing microarchitectures do not perform well when processing complex tasks. Due to their relatively simple design, they cannot fully tap the performance potential of the processor, resulting in slow processing speeds and affecting the operating efficiency of the entire embedded system.

[0005] (2) Insufficient reliability: In some key application scenarios, the existing microarchitecture may cause erroneous submission or data loss, reducing the reliability of the processor. This is a serious problem for some embedded systems with high reliability requirements, such as automotive electronics and medical equipment.

[0006] (3) Poor flexibility: Existing microarchitectures are usually designed for specific processor architectures and application scenarios and lack flexibility. When the processor architecture or application scenario changes, the microarchitecture needs to be redesigned, which increases design costs and time.

[0007] (4) High power consumption: Existing microarchitectures consume a lot of power when working, which is a disadvantage for some embedded systems with strict power consumption requirements. High power consumption not only increases the cooling cost of the system, but also shortens the battery life. Summary of the invention

[0008] The object of the present invention is to provide a dual write-back embedded scalar processor micro-architecture, which can improve the performance, reliability and flexibility of the embedded scalar processor while reducing power consumption to meet the needs of different embedded application scenarios.

[0009] In order to achieve the above object, the present invention provides the following technical solutions: A dual write-back embedded scalar processor microarchitecture, comprising: An arbitration unit for arbitrating program counter values ​​flowing into the pipeline; An instruction fetch unit, used to obtain instruction data according to a program counter value; A decoding component, used for decoding instruction data, obtaining a memory access operation code and a memory access operand when the instruction is a memory access instruction, and obtaining a non-memory access operation code and a non-memory access operand when the instruction is a non-memory access instruction; An execution unit, used for calculating a memory access address according to a memory access operand; and for executing a non-memory access instruction according to a non-memory access operation code and a non-memory access operand, and obtaining a non-memory access instruction execution result; A memory access component, used to execute a memory access instruction according to a memory access operation code and a memory access address to obtain memory access data; The write-back component is used to update the system register according to the memory access data and / or the non-memory access instruction execution result, and to perform the memory access instruction and / or the non-memory access instruction write-back operation.

[0010] Further, arbitrating the program counter value flowing into the pipeline includes: arbitrating the program counter value flowing into the pipeline according to an arbitration algorithm; wherein the arbitration algorithm includes a first-come-first-served algorithm and a priority algorithm.

[0011] Further, according to the program counter value, obtaining instruction data includes: According to the program counter value, obtain the current instruction virtual address; Perform instruction transfer prediction based on the current instruction virtual address and obtain the next instruction virtual address; Replace the virtual address of the current instruction with the real address of the next instruction to obtain the physical address of the current instruction and the physical address of the next instruction; The instruction cache is queried according to the current instruction physical address and the next instruction physical address to obtain instruction data.

[0012] Further, executing a memory access instruction according to a memory access operation code and a memory access address to obtain memory access data includes: Replace the virtual address with the real address to obtain the physical address. The data cache is queried according to the memory access operation code and the memory access physical address to obtain the memory access data.

[0013] Furthermore, it also includes: a general control component, which is used to respond to interrupt events occurring during the operation of the processor and send corresponding interrupt processing signals to each component; and is used to respond to abnormal events occurring in each component during the operation of the processor and send corresponding abnormal processing signals to each component.

[0014] Further, interrupt events include: processor internal clock interrupts and processor external interrupts; Interrupt processing signals include: interrupt clear signal and interrupt pause signal; Abnormal events include: arbitration delay abnormality of arbitration unit, virtual-real address substitution abnormality and instruction data verification abnormality of instruction fetch unit, illegal instruction abnormality of decoding unit, calculation overflow abnormality of execution unit, and virtual-real address substitution abnormality and memory access data verification abnormality of memory access unit; Exception handling signals include: exception clear signal and exception pause signal.

[0015] Furthermore, the processing flow of memory access instructions includes: instruction fetch-decode-execute-memory access-write back; the processing flow of non-memory access instructions includes: instruction fetch-decode-execute-write back; if the current memory access instruction misses, and the current memory access instruction generates multi-beat memory access behavior, then the next memory access instruction or the next non-memory access instruction related to the current memory access instruction is blocked until the multi-beat memory access behavior generated by the current memory access instruction ends.

[0016] Furthermore, if the current instruction is a memory access instruction and hits, the current instruction is fetched at the 1st moment, decoded at the 2nd moment, executed at the 3rd moment, memory accessed at the 4th moment, and written back at the 5th moment; then when the next instruction is a non-memory access instruction, the next instruction is fetched at the 2nd moment, decoded at the 3rd moment, executed at the 4th moment, and written back at the 5th moment.

[0017] Furthermore, if the current instruction is a memory access instruction and it misses, the current instruction is fetched at the 1st moment, decoded at the 2nd moment, executed at the 3rd moment, memory accessed at the 4th to 4+N moments, and written back at the 5+N moment; then when the next instruction is a non-memory access instruction unrelated to the current instruction, the next instruction is fetched at the 2nd moment, decoded at the 3rd moment, executed at the 4th moment, and written back at the 5th moment; wherein N represents the number of multi-beat memory access behaviors generated when the memory access instruction misses.

[0018] Further, if the current instruction is a memory access instruction and it misses, the current instruction is fetched at the 1st moment, decoded at the 2nd moment, executed at the 3rd moment, memory accessed at the 4th to 4+N moments, and written back at the 5+N moment; then when the next instruction is a non-memory access instruction related to the current instruction, the next instruction is fetched at the 2nd moment, decoded at the 3rd to 5+N moments, executed at the 6+N moments, and written back at the 7+N moments; wherein N represents the number of multi-beat memory access behaviors generated when the memory access instruction misses.

[0019] Compared with the prior art, the present invention has the following beneficial effects: The dual write-back embedded scalar processor micro-architecture provided by the present invention supports simultaneous write-back of memory access instructions and non-memory access instructions, and can improve the performance, reliability and flexibility of the embedded scalar processor. For memory access instructions, the processing flow includes: instruction fetch-decode-execute-memory access-write-back, a total of 5 beats, and for non-memory access instructions, the processing flow includes: instruction fetch-decode-execute-write-back, a total of 4 beats. Compared with the existing micro-architecture, the processing flow of non-memory access instructions is shortened from the general 5 beats to 4 beats, which can reduce the power consumption of the embedded scalar processor and is suitable for different embedded application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a dual write-back embedded scalar processor micro-architecture provided by an embodiment of the present invention; Figure 2 is a flowchart of memory access instruction and non-memory access instruction processing provided by an embodiment of the present invention; Figure 3 This is a multi-case write-back flow chart provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The technical solution of the present application is further described in detail below in conjunction with specific implementation methods.

[0022] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments may be combined with each other.

[0023] Embodiment 1: This embodiment provides a dual write-back embedded scalar processor microarchitecture, such as Figure 1 As shown, the dual write-back embedded scalar processor micro-architecture provided in this embodiment specifically includes: An arbitration unit for arbitrating program counter values ​​flowing into the pipeline; An instruction fetch unit, used to obtain instruction data according to a program counter value; A decoding component, used for decoding instruction data, obtaining a memory access operation code and a memory access operand when the instruction is a memory access instruction, and obtaining a non-memory access operation code and a non-memory access operand when the instruction is a non-memory access instruction; An execution unit, used for calculating a memory access address according to a memory access operand; and for executing a non-memory access instruction according to a non-memory access operation code and a non-memory access operand, and obtaining a non-memory access instruction execution result; A memory access component, used to execute a memory access instruction according to a memory access operation code and a memory access address to obtain memory access data; The write-back component is used to update the system register according to the memory access data and / or the non-memory access instruction execution result, and to perform the memory access instruction and / or the non-memory access instruction write-back operation.

[0024] In this embodiment, updating the system register according to the memory access data and / or the non-memory access instruction execution result, and executing the memory access instruction and / or the non-memory access instruction write-back operation specifically includes: Update the system registers according to the memory access data and execute the memory access instruction write-back operation; Or, the system register is updated according to the execution result of the non-memory access instruction, and the non-memory access instruction write-back operation is performed; Alternatively, the system register is updated according to the memory access data and the non-memory access instruction execution result, and the memory access instruction and the non-memory access instruction write back operation are performed at the same time.

[0025] Specifically, the write-back component can update the system registers according to the memory access data and perform a memory access instruction write-back operation; or update the system registers according to the execution results of non-memory access instructions and perform a non-memory access instruction write-back operation; or update the system registers according to the memory access data and the execution results of non-memory access instructions, and simultaneously perform memory access instructions and non-memory access instruction write-back operations.

[0026] In this embodiment, arbitrating the program counter value flowing into the pipeline specifically includes: arbitrating the program counter value flowing into the pipeline according to an arbitration algorithm; wherein the arbitration algorithm includes a first-come-first-served algorithm and a priority algorithm.

[0027] In this embodiment, obtaining instruction data according to the program counter value specifically includes the following steps: Step ①: Get the current instruction virtual address according to the program counter value; Step 2: Perform instruction transfer prediction based on the current instruction virtual address to obtain the next instruction virtual address; Step 3: Replace the virtual address of the current instruction with the real address of the next instruction to obtain the physical address of the current instruction and the physical address of the next instruction; Step ④: Query the instruction cache according to the current instruction physical address and the next instruction physical address to obtain instruction data.

[0028] In this embodiment, executing a memory access instruction according to a memory access operation code and a memory access address to obtain memory access data specifically includes the following steps: Step 1: Replace the virtual address with the real address to obtain the physical address; Step ②: Query the data cache according to the memory access operation code and the memory access physical address to obtain the memory access data.

[0029] In this embodiment, the processing flow of memory access instructions includes: instruction fetch-decode-execute-memory access-write back; the processing flow of non-memory access instructions includes: instruction fetch-decode-execute-write back.

[0030] Specifically, Figure 2 As shown, the processing flow of non-memory access instructions includes: fetch-decode-execute-write back, a total of 4 beats.

[0031] When a memory access instruction hits, the processing flow of the memory access instruction includes: fetch-decode-execute-memory access-write back, a total of 5 beats.

[0032] When a memory access instruction misses, the memory access instruction generates multi-beat memory access behavior.

[0033] If the current memory access instruction misses and generates multi-beat memory access behavior, the next memory access instruction or the next non-memory access instruction related to the current memory access instruction is blocked until the multi-beat memory access behavior generated by the current memory access instruction ends.

[0034] The dual write-back embedded scalar processor microarchitecture provided in this embodiment may have the following three write-back situations: Case 1: Double write-back.

[0035] If the current instruction is a memory access instruction and it hits, the current instruction is fetched at the 1st time, decoded at the 2nd time, executed at the 3rd time, memory accessed at the 4th time, and written back at the 5th time; then when the next instruction is a non-memory access instruction, the next instruction is fetched at the 2nd time, decoded at the 3rd time, executed at the 4th time, and written back at the 5th time.

[0036] That is, the memory access instruction write back operation and the non-memory access instruction write back operation are executed simultaneously.

[0037] Case 2: Non-memory access instructions are written back early.

[0038] If the current instruction is a memory access instruction and it misses, the current instruction is fetched at the 1st time, decoded at the 2nd time, executed at the 3rd time, memory accessed at the 4th to 4+N times, and written back at the 5+N time; then when the next instruction is a non-memory access instruction unrelated to the current instruction, the next instruction is fetched at the 2nd time, decoded at the 3rd time, executed at the 4th time, and written back at the 5th time; where N represents the number of multi-beat memory access behaviors generated when the memory access instruction misses.

[0039] That is, the write-back operation of non-memory access instructions is executed in advance.

[0040] Case 3: Dependency conflict instruction blocks writeback.

[0041] If the current instruction is a memory access instruction and it misses, the current instruction is fetched at time 1, decoded at time 2, executed at time 3, memory accessed at time 4 to time 4+N, and written back at time 5+N; then when the next instruction is a non-memory access instruction related to the current instruction, the next instruction is fetched at time 2, decoded at time 3 to time 5+N, executed at time 6+N, and written back at time 7+N; where N represents the number of multi-beat memory access behaviors generated when the memory access instruction misses.

[0042] That is, after the multi-beat memory access behavior caused by the memory access instruction miss is completed, the non-memory access instruction write-back operation is executed.

[0043] The dual write-back embedded scalar processor microarchitecture provided in this embodiment supports simultaneous write-back of memory access instructions and non-memory access instructions, which can improve the performance, reliability and flexibility of embedded scalar processors. For memory access instructions, the processing flow includes: instruction fetch-decode-execute-memory access-write-back, a total of 5 beats, and for non-memory access instructions, the processing flow includes: instruction fetch-decode-execute-write-back, a total of 4 beats. Compared with the existing microarchitecture, the processing flow of non-memory access instructions is shortened from the general 5 beats to 4 beats, which can reduce the power consumption of embedded scalar processors and is suitable for different embedded application scenarios.

[0044] Embodiment 2: This embodiment provides a dual write-back embedded scalar processor micro-architecture. Based on the embodiment 1, Figure 3 As shown, the dual write-back embedded scalar processor micro-architecture provided by this embodiment has the following write-back situations: Instruction PC0 is a memory access instruction and hits. Instruction PC0 is fetched at time T0, decoded at time T1, executed at time T2, accessed at time T3, and written back at time T4; Instruction PC1 is a non-memory access instruction. Instruction PC1 is fetched at time T1, decoded at time T2, executed at time T3, and written back at time T4. Instruction PC2 is a memory access instruction and misses. Instruction PC2 is fetched at time T2, decoded at time T3, executed at time T4, accessed at time T5 to T8, and written back at time T9; Instruction PC3 is a non-memory access instruction that is unrelated to instruction PC2. Instruction PC3 is fetched at time T3, decoded at time T4, executed at time T5, and written back at time T6. Instruction PC4 is a non-memory access instruction related to instruction PC2. Instruction PC4 is fetched at time T4, decoded at times T5 to T9, executed at time T10, and written back at time T11.

[0045] In this embodiment, Figure 3As shown, if the current memory access instruction hits, the next non-memory access instruction will be written back at the same time as the current memory access instruction. If the current memory access instruction does not hit, the next non-memory access instruction that is not related to the current memory access instruction will be written back in advance. If the current memory access instruction does not hit, the next non-memory access instruction that is related to the current memory access instruction will need to wait until the current memory access instruction is written back before it can be written back.

[0046] Embodiment 3: This embodiment provides a dual write-back embedded scalar processor micro-architecture. Based on the embodiment 1, Figure 1 As shown, the dual write-back embedded scalar processor micro-architecture provided in this embodiment specifically includes: An arbitration unit for arbitrating program counter values ​​flowing into the pipeline; An instruction fetch unit, used to obtain instruction data according to a program counter value; A decoding component is used to decode the instruction data and determine whether the instruction is a memory access instruction or a non-memory access instruction; if the instruction is determined to be a memory access instruction, the memory access instruction is retained; if the instruction is determined to be a non-memory access instruction, the non-memory access instruction is parsed to obtain a non-memory access operation code and a non-memory access operand; An execution unit, used to parse the memory access instruction to obtain the memory access operation code and the memory access address; and to execute the non-memory access instruction according to the non-memory access operation code and the non-memory access operand to obtain the non-memory access instruction execution result; A memory access component, used to execute a memory access instruction according to a memory access operation code and a memory access address to obtain memory access data; A write-back component, used to update the system register according to the memory access data and / or the non-memory access instruction execution result, and to perform the memory access instruction and / or the non-memory access instruction write-back operation; The general control component is used to respond to interrupt events occurring during the operation of the processor and send corresponding interrupt processing signals to each component; and to respond to abnormal events occurring in each component during the operation of the processor and send corresponding abnormal processing signals to each component.

[0047] In this embodiment, the interruption events include: processor internal clock interruption and processor external interruption; the interruption processing signal includes: interruption clearing signal and interruption suspending signal.

[0048] Specifically, when an interrupt event occurs during the operation of the processor, the general control component receives an interrupt signal and sends a corresponding interrupt processing signal to each component according to the interrupt signal.

[0049] The interrupt signal may be generated by the processor inside or outside. The interrupt signal includes the processor internal clock interrupt signal and the processor external interrupt signal.

[0050] Specifically, when a processor internal clock interrupt occurs during processor operation, the general control component will receive the processor internal clock interrupt signal, and the general control component will send an interrupt clear signal or an interrupt pause signal to the corresponding component according to the processor internal clock interrupt signal.

[0051] When a processor external interrupt occurs during the operation of the processor, the main control component will receive the processor external interrupt signal, and the main control component will send an interrupt clear signal or an interrupt pause signal to the corresponding component according to the processor external interrupt signal.

[0052] In this embodiment, abnormal events include: arbitration delay exception of arbitration component, virtual-real address substitution exception and instruction data verification exception of instruction fetch component, illegal instruction exception of decoding component, calculation overflow exception of execution component, and virtual-real address substitution exception and memory access data verification exception of memory access component; exception handling signals include: exception clear signal and exception pause signal.

[0053] Specifically, when an abnormal event occurs in each component during the operation of the processor, the general control component will receive the abnormal signal uploaded by each component, and send a corresponding abnormal processing signal to each component according to the abnormal signal uploaded by each component.

[0054] The exception signals include: the arbitration delay exception signal uploaded by the arbitration component, the virtual-real address substitution exception signal and the instruction data verification exception signal uploaded by the instruction fetch component, the instruction illegal exception signal uploaded by the decoding component, the calculation overflow exception signal uploaded by the execution component, and the virtual-real address substitution exception signal and the memory access data verification exception signal uploaded by the memory access component.

[0055] Specifically, the arbitration component will arbitrate the program counter value flowing into the pipeline; when an arbitration delay exception occurs in the arbitration component, the arbitration component will upload an arbitration delay exception signal to the general control component, and the general control component will send an exception clear signal or an exception pause signal to the arbitration component based on the arbitration delay exception signal.

[0056] The instruction fetch unit will predict the instruction transfer according to the current instruction virtual address and obtain the next instruction virtual address; it will replace the virtual address of the current instruction with the real address of the next instruction virtual address and obtain the current instruction physical address and the next instruction physical address; it will query the instruction cache according to the current instruction physical address and the next instruction physical address to obtain the instruction data; and it will verify the instruction data; when the instruction fetch unit has a virtual-real address replacement exception or an instruction data verification exception, the instruction fetch unit will upload a virtual-real address replacement exception signal and an instruction data verification exception signal to the main control unit, and the main control unit will send an exception clearing signal or an exception pause signal to the instruction fetch unit according to the virtual-real address replacement exception signal and the instruction data verification exception signal.

[0057] The decoding component will decode the instruction data; when the decoding component finds an illegal instruction, that is, when an illegal instruction exception occurs in the decoding component, the decoding component will upload an illegal instruction exception signal to the general control component, and the general control component will send an exception clearing signal or an abnormal pause signal to the decoding component based on the illegal instruction exception signal.

[0058] The execution unit will execute non-memory access instructions (such as calculation instructions, read and write register instructions, miscellaneous instructions, etc.) according to the non-memory access opcode and non-memory access operand to obtain the execution result of the non-memory access instruction; when a calculation overflow exception occurs in the execution unit, the execution unit will upload the calculation overflow exception signal to the main control unit, and the main control unit will send an exception clear signal or an exception pause signal to the execution unit according to the calculation overflow exception signal.

[0059] The memory access component will replace the virtual-real address with the real address to obtain the memory access physical address; query the data cache according to the memory access operation code and the memory access physical address to obtain the memory access data; and verify the memory access data; when the memory access component has a virtual-real address replacement exception or a memory access data verification exception, the memory access component will upload the virtual-real address replacement exception signal and the memory access data verification exception signal to the main control component, and the main control component will send an exception clearing signal or an exception pause signal to the memory access component based on the virtual-real address replacement exception signal and the memory access data verification exception signal.

[0060] Embodiment 4: This embodiment provides a dual write-back embedded scalar processor micro-architecture. Based on the embodiment 1, Figure 1 As shown, the dual write-back embedded scalar processor microarchitecture provided in this embodiment is divided into an instruction fetch station, a decoding station, an execution station, a memory access station, a memory access write-back station, and a non-memory access instruction bypass memory access station according to the instruction execution process. The non-memory access instruction bypass memory access station is located at the execution unit. Figure 1 Not shown.

[0061] In this embodiment, the instruction fetch unit is provided with an instruction cache, and the memory access unit is provided with a data cache.

[0062] The dual write-back embedded scalar processor micro-architecture provided in this embodiment enables memory access instructions and non-memory access instructions to be written back simultaneously by designing a non-memory access instruction to bypass the memory access station.

[0063] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A dual write-back embedded scalar processor microarchitecture, characterized in that: include: An arbitration unit for arbitrating program counter values ​​flowing into the pipeline; An instruction fetch unit, used to obtain instruction data according to a program counter value; A decoding component, used for decoding instruction data, obtaining a memory access operation code and a memory access operand when the instruction is a memory access instruction, and obtaining a non-memory access operation code and a non-memory access operand when the instruction is a non-memory access instruction; An execution unit, used for calculating a memory access address according to a memory access operand; and for executing a non-memory access instruction according to a non-memory access operation code and a non-memory access operand, and obtaining a non-memory access instruction execution result; A memory access component, used to execute a memory access instruction according to a memory access operation code and a memory access address to obtain memory access data; The write-back component is used to update the system register according to the memory access data and / or the non-memory access instruction execution result, and to perform the memory access instruction and / or the non-memory access instruction write-back operation.

2. The dual write-back embedded scalar processor microarchitecture according to claim 1, characterized in that: Arbitrating the program counter value flowing into the pipeline includes: arbitrating the program counter value flowing into the pipeline according to an arbitration algorithm; wherein the arbitration algorithm includes a first-come-first-served algorithm and a priority algorithm.

3. The dual write-back embedded scalar processor microarchitecture according to claim 1, characterized in that: According to the program counter value, the instruction data is obtained including: According to the program counter value, obtain the current instruction virtual address; Perform instruction transfer prediction based on the current instruction virtual address and obtain the next instruction virtual address; Replace the virtual address of the current instruction with the real address of the next instruction to obtain the physical address of the current instruction and the physical address of the next instruction; The instruction cache is queried according to the current instruction physical address and the next instruction physical address to obtain instruction data.

4. The dual write-back embedded scalar processor microarchitecture according to claim 1, characterized in that: Execute the memory access instruction according to the memory access operation code and the memory access address, and obtain the memory access data including: Replace the virtual address with the real address to obtain the physical address. The data cache is queried according to the memory access operation code and the memory access physical address to obtain the memory access data.

5. The dual write-back embedded scalar processor microarchitecture according to claim 1, characterized in that: Also includes: The general control component is used to respond to interrupt events that occur during the operation of the processor and send corresponding interrupt processing signals to each component; And it is used to respond to abnormal events occurring in various components during the operation of the processor and send corresponding abnormal processing signals to each component.

6. The dual write-back embedded scalar processor microarchitecture according to claim 5, characterized in that: Interrupt events include: processor internal clock interrupt and processor external interrupt; Interrupt processing signals include: interrupt clear signal and interrupt pause signal; Abnormal events include: arbitration delay abnormality of arbitration unit, virtual-real address substitution abnormality and instruction data verification abnormality of instruction fetch unit, illegal instruction abnormality of decoding unit, calculation overflow abnormality of execution unit, and virtual-real address substitution abnormality and memory access data verification abnormality of memory access unit; Exception handling signals include: exception clear signal and exception pause signal.

7. The dual write-back embedded scalar processor microarchitecture according to claim 1, characterized in that: The processing flow of memory access instructions includes: instruction fetch-decode-execute-memory access-write back; the processing flow of non-memory access instructions includes: instruction fetch-decode-execute-write back; if the current memory access instruction does not hit, and the current memory access instruction generates multi-beat memory access behavior, then the next memory access instruction or the next non-memory access instruction related to the current memory access instruction is blocked until the multi-beat memory access behavior generated by the current memory access instruction ends.

8. The dual write-back embedded scalar processor microarchitecture according to claim 7, characterized in that: If the current instruction is a memory access instruction and it hits, the current instruction is fetched at the 1st time, decoded at the 2nd time, executed at the 3rd time, memory accessed at the 4th time, and written back at the 5th time; then when the next instruction is a non-memory access instruction, the next instruction is fetched at the 2nd time, decoded at the 3rd time, executed at the 4th time, and written back at the 5th time.

9. The dual write-back embedded scalar processor microarchitecture according to claim 7, characterized in that: If the current instruction is a memory access instruction and it misses, the current instruction is fetched at the 1st time, decoded at the 2nd time, executed at the 3rd time, memory accessed at the 4th to 4+N times, and written back at the 5+N time; then when the next instruction is a non-memory access instruction unrelated to the current instruction, the next instruction is fetched at the 2nd time, decoded at the 3rd time, executed at the 4th time, and written back at the 5th time; where N represents the number of multi-beat memory access behaviors generated when the memory access instruction misses.

10. The dual write-back embedded scalar processor microarchitecture according to claim 7, characterized in that: If the current instruction is a memory access instruction and it misses, the current instruction is fetched at time 1, decoded at time 2, executed at time 3, memory accessed at time 4 to time 4+N, and written back at time 5+N; then when the next instruction is a non-memory access instruction related to the current instruction, the next instruction is fetched at time 2, decoded at time 3 to time 5+N, executed at time 6+N, and written back at time 7+N; where N represents the number of multi-beat memory access behaviors generated when the memory access instruction misses.

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