Method for instruction fusion with superscalar processors and related devices

Abstract

The application provides a method for instruction fusion using a superscalar processor and related equipment. A decoding unit obtains first instruction control signals of multiple instructions to be executed, and sends the first instruction control signals to a fusion decoding unit. The fusion decoding unit determines, for any one of at least one instruction pair, that a first instruction in the any one instruction pair is an I-type instruction, a second instruction in the any one instruction pair is an I-type instruction or an R-type instruction, and judges whether there is an instruction pair matching the any one instruction pair in a plurality of preset instruction pairs. If there is, instruction fusion is performed under the condition that a source operand of the first instruction is equal to a destination operand of the first instruction and the destination operand of the first instruction is equal to at least one source operand of the second instruction, to obtain a fusion instruction. A fusion instruction execution unit executes the fusion instruction according to an operation logic of the fusion instruction.

Description

Technical Field

[0001] This application relates to the field of instruction fusion technology, and in particular to a method and related equipment for instruction fusion using a superscalar processor. Background Technology

[0002] Currently, in superscalar processors, the main stages of an instruction execution are: fetch, decode, out-of-order scheduling, execution and write-back, and commit. When there are many instructions to be processed, the performance of the superscalar processor is affected. Therefore, several methods have emerged to optimize superscalar processors, including software and hardware optimizations. Software methods primarily optimize the compiler, while hardware methods mainly involve instruction elimination and instruction fusion. However, existing instruction fusion techniques require additional hardware logic to process the fused instructions, complicating the operation of the superscalar processor. Summary of the Invention

[0003] To address the aforementioned issues, this application provides a method and related apparatus for instruction fusion using a superscalar processor. This method helps reduce the number of instructions executed by the superscalar processor, accelerates processor processing efficiency, and enables fused and non-fused instructions to reuse the same instruction execution unit, thereby reducing the maintenance cost of the superscalar processor.

[0004] To achieve the above objectives, the first aspect of this application provides a superscalar processor for instruction fusion, including a decoding unit, a fusion decoding unit, and an instruction execution unit, wherein the instruction execution unit includes a fusion instruction execution unit;

[0005] The decoding unit is used to obtain the first instruction control signal of each instruction among the multiple instructions to be executed, and send the first instruction control signal to the fusion decoding unit;

[0006] The fusion decoding unit is used to obtain at least one instruction pair consisting of two adjacent instructions from multiple instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, and the second instruction in the instruction pair is an I-type instruction or an R-type instruction. It also determines whether there is an instruction pair among the preset multiple instruction pairs that matches the instruction pair. If there is, then, if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction.

[0007] The fusion instruction execution unit is used to execute fusion instructions according to the operation logic of fusion instructions.

[0008] In conjunction with the first aspect, in one possible implementation, the fusion decoding unit is further configured to, if there is no instruction pair among the plurality of instruction pairs that matches any one of the instruction pairs, set the validity bit of the first instruction to a first state and the flag bit to a second state, and set the validity bit of the second instruction to a first state and the flag bit to a second state.

[0009] In conjunction with the first aspect, in one possible implementation, the fusion decoding unit is further configured to, when the source operand and destination operand of the first instruction are not equal or the destination operand of the first instruction is not equal to any one of the source operands of the second instruction, set the validity bit of the first instruction to a first state and the flag bit to a second state, and set the validity bit of the second instruction to a first state and the flag bit to a second state.

[0010] In conjunction with the first aspect, in one possible implementation, the fusion decoding unit is further configured to generate a second instruction control signal for the fusion instruction, set the valid bit of the fusion instruction to a first state and the flag bit to a first state, and set the valid bit of the second instruction to a second state and the flag bit to a second state.

[0011] In conjunction with the first aspect, in one possible implementation, the instruction execution unit further includes a non-fusion instruction execution unit;

[0012] The instruction execution unit is used to receive the first and second instructions sent by the reserved station after out-of-order scheduling, determine whether the flag bits of the first and second instructions after out-of-order scheduling are in the second state, and if so, send the first and second instructions after out-of-order scheduling to the non-converged instruction execution unit.

[0013] A non-fusion instruction execution unit is used to execute a first instruction according to the operation logic of a first instruction and to execute a second instruction according to the operation logic of a second instruction.

[0014] In conjunction with the first aspect, in one possible implementation, the instruction execution unit is further configured to receive the out-of-order fusion instruction sent by the reservation station, determine whether the flag bit of the out-of-order fusion instruction is in the first state, and if so, send the out-of-order fusion instruction to the fusion instruction execution unit.

[0015] In conjunction with the first aspect, in one possible implementation, the second instruction control signal includes the operation type of the fused instruction, the destination register number where the destination operand is located, and the register number where the source operand is located.

[0016] The second aspect of this application provides a method for instruction fusion using the superscalar processor provided in the first aspect. The superscalar processor includes a decoding unit, a fusion decoding unit, and an instruction execution unit. The instruction execution unit includes a fusion instruction execution unit.

[0017] The decoding unit obtains the first instruction control signal of each of the multiple instructions to be executed, and sends the first instruction control signal to the fusion decoding unit;

[0018] The fusion decoding unit acquires at least one instruction pair consisting of two adjacent instructions from multiple instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, and the second instruction in the instruction pair is an I-type instruction or an R-type instruction. It also determines whether there is an instruction pair among the preset multiple instruction pairs that matches the instruction pair. If there is, then, if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction.

[0019] The fusion instruction execution unit executes the fusion instruction according to the fusion instruction's operational logic.

[0020] A third aspect of this application provides a computer device including a processor and a memory. The processor is connected to the memory, which stores a computer program. The processor executes the computer program stored in the memory to cause the computer device to perform the method steps as described in the second aspect.

[0021] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that is executed by a processor to implement the method steps as described in the second aspect.

[0022] The above-mentioned solution in this application includes at least the following beneficial effects:

[0023] In this embodiment, the superscalar processor includes a decoding unit, a fusion decoding unit, and an instruction execution unit, the instruction execution unit including a fusion instruction execution unit. First, the decoding unit obtains the first instruction control signal for each of the multiple instructions to be executed and sends it to the fusion decoding unit to identify the first instruction control signal for each instruction. Then, the fusion decoding unit obtains at least one instruction pair consisting of every two adjacent instructions from the multiple instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, and the second instruction in the instruction pair is either an I-type instruction or an R-type instruction. It also determines whether there exists an instruction pair among the preset multiple instruction pairs that matches any instruction pair. If such a pair exists, then, if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction. Instruction fusion aims to reduce the number of instructions executed. It determines whether the first instruction control signals of two adjacent instructions conform to preset instruction and register modes. If both conform, the two instructions are fused to obtain a fused instruction. Finally, the fused instruction execution unit executes the fused instruction according to its operational logic. After instruction fusion processing, the control signal content of the fused instruction changes, and the fused instruction execution unit executes the instruction according to its operational logic.

[0024] This application's solution reduces the number of instructions executed by a superscalar processor through instruction fusion using a fusion decoding unit, thereby reducing execution time and improving operational efficiency. Furthermore, the fused instructions obtained after instruction fusion processing contain the same number of destination and source operands as the original instructions, allowing for the reuse of existing instruction execution units without requiring a separate instruction execution unit, thus reducing costs. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A flowchart illustrating a method for instruction fusion using a superscalar processor, provided as an embodiment of this application;

[0027] Figure 2 A schematic diagram illustrating the sending of instructions via an instruction buffer, as provided in an embodiment of this application;

[0028] Figure 3 A schematic diagram of the overall processing logic of a superscalar processor provided in an embodiment of this application;

[0029] Figure 4 A schematic diagram of instruction fusion provided for an embodiment of this application;

[0030] Figure 5 This application provides an overall schematic diagram of determining whether two adjacent instructions conform to an instruction fusion mode.

[0031] Figure 6 A schematic diagram of a superscalar processor for instruction fusion is provided as an embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0034] The terms "comprising" and "having," and any variations thereof, appearing in this specification, claims, and drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects and are not used to describe a specific order.

[0035] Please see Figure 1 , Figure 1 This application provides a flowchart illustrating a method for instruction fusion using a superscalar processor, wherein the superscalar processor includes a decoding unit, a fusion decoding unit, and an instruction execution unit, and the instruction execution unit includes a fusion instruction execution unit. The method includes steps 101-103:

[0036] 101: The decoding unit obtains the first instruction control signal of each of the multiple instructions to be executed, and sends the first instruction control signal to the fusion decoding unit.

[0037] 102: The fusion decoding unit acquires at least one instruction pair consisting of two adjacent instructions from multiple instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, and the second instruction in the instruction pair is an I-type instruction or an R-type instruction. It also determines whether there is an instruction pair among the preset multiple instruction pairs that matches any instruction pair. If there is, then when the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction.

[0038] 103: The fusion instruction execution unit executes the fusion instruction according to the operation logic of the fusion instruction.

[0039] Before performing instruction fusion on two adjacent instructions, the instruction buffer needs to acquire multiple instructions for the decision. For example, a superscalar processor also includes a basic pre-decoding unit, which acquires multiple instructions from the instruction cache and sends them to the instruction buffer, so that the instruction buffer sends the acquired instructions to the decoding unit. Meanwhile, as... Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the sending of instructions via an instruction buffer, as provided in an embodiment of this application. The instruction buffer will also hold multiple instructions (e.g., Figure 2 Each pair of two adjacent instructions in the six instructions in the code forms an instruction pair, thereby obtaining at least one instruction pair, and at least one instruction pair is sent to the fusion decoding unit.

[0040] Specifically, the decoding unit decodes each instruction in the multiple instructions to obtain the instruction control signal for each instruction, and then sends this instruction control signal to the fusion decoding unit. The fusion decoding unit determines whether the instruction control signals of two adjacent instructions in the instruction pair conform to a preset instruction fusion mode, which includes instruction mode and register mode. Only two adjacent instructions that conform to both modes can be fused to obtain a fused instruction, which is then executed by the fused instruction execution unit in the instruction execution unit according to the operation logic of the fused instruction. If neither mode is conformed to, instruction fusion cannot be performed, and the instruction that cannot be fused will be executed by the instruction execution unit according to the original operation logic of the instruction. Therefore, in this scheme, there are three cases: first, two adjacent instructions conform to both modes and are fused; second, two adjacent instructions do not conform to the instruction mode and are not fused, but are executed according to the original operation logic of the instruction; third, two adjacent instructions conform to the instruction mode but not the register mode and are not fused, but are executed according to the original operation logic of the instruction. The following will explain the above three embodiments in detail.

[0041] This application's solution reduces the number of instructions executed by a superscalar processor through instruction fusion using a fusion decoding unit, thereby reducing execution time and improving operational efficiency. Furthermore, the fused instructions obtained after instruction fusion processing contain the same number of destination and source operands as the original instructions, allowing for the reuse of existing instruction execution units without requiring a separate instruction execution unit, thus reducing costs.

[0042] Please see Figure 3 , Figure 3 This is a schematic diagram of the overall processing logic of a superscalar processor provided in an embodiment of this application. The superscalar processor includes a decoding unit, a fusion decoding unit, and an instruction execution unit. The instruction execution unit includes a fusion instruction execution unit and a non-fusion instruction unit. The overall logic is as follows: multiple instructions are retrieved from the instruction cache by the instruction buffer; the decoding unit performs decoding processing; and the first control signals of the multiple instructions are sent to the fusion decoding unit. The fusion decoding unit determines whether the first control signals of the multiple instructions conform to the instruction pattern. For conforming instruction pairs, a fusion instruction is generated and sent to the reservation station; for non-conforming instructions, the first control signals are directly sent to the reservation station. Finally, the fusion instruction execution unit of the instruction execution unit executes the fusion instruction according to the logic of the fusion instruction, while the non-fusion instruction unit executes the instructions according to the instruction logic. Figure 3 The above three situations will be explained.

[0043] The first scenario is when two adjacent instructions conform to either of the above two patterns, in which case instruction fusion is performed:

[0044] First, the decoding unit obtains the first instruction control signal of each of the multiple instructions to be executed, and sends the first instruction control signal to the fusion decoding unit.

[0045] Specifically, after the decoding unit receives multiple instructions from the instruction buffer, it performs a decoding operation to obtain the instruction control signal (i.e., the first instruction control signal) and the valid bits of each instruction. The first instruction control signal contains the destination operand and the source operand of the instruction. For example, instruction 1: slli r1,r1,1, where the first bit r1 is the destination operand of instruction 1, the second bit r1 is the source operand of instruction 1, and the third bit 1 is the source operand of instruction 1. In order to determine the instruction fusion mode of the multiple instructions, the decoding unit sends the first instruction control signal of each instruction in the decoded multiple instructions to the fusion decoding unit for judgment.

[0046] Then, the fusion decoding unit obtains at least one instruction pair consisting of every two adjacent instructions from multiple instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, the second instruction in the instruction pair is an I-type instruction or an R-type instruction, and determines whether there is an instruction pair among the preset multiple instruction pairs that matches any instruction pair. If there is, then, if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction.

[0047] Here, the first instruction can be any instruction in the instruction pair, such as the first instruction, and the second instruction can be another instruction in the instruction pair besides the first instruction, such as the second instruction. Specifically, after obtaining the first instruction control signal of each instruction in the multiple instructions, the fusion decoding unit judges the first instruction control signals of two adjacent instructions in any instruction pair. First, the first instruction in the two adjacent instructions must be an I-type instruction, and the second instruction must be either an I-type instruction or an R-type instruction. For example, instruction pair 1: slli r1,r1,32 and srli r1,r1,31, where the first instruction slli r1,r1,32 is an I-type instruction, and the second instruction srli r1,r1,31 is an I-type instruction. If the first instruction in the two adjacent instructions is an I-type instruction, and the second instruction is either an I-type instruction or an R-type instruction, it is necessary to determine whether there is an instruction pair among the preset multiple instruction pairs that matches this instruction pair. In this unit, multiple preset instruction pairs are cached in the fusion decoding unit. The first instruction control signals of two adjacent instructions in any given instruction pair are matched with the instruction control signals of the instructions in the multiple preset instruction pairs. If a matching instruction pair exists among the multiple preset instruction pairs, then the instruction pair is determined to conform to the instruction fusion mode.

[0048] Even when an instruction meets the instruction fusion mode, register mode determination is still required to perform instruction fusion on two adjacent instructions. Register mode requires that the source operand and destination operand of the first instruction are equal, and the destination operand of the first instruction is equal to at least one source operand of the second instruction. For example, in instruction pair 1: sllir1,r1,32 and srli r1,r1,31, the destination operand r1 of the first instruction slli r1,r1,32 is equal to the destination operand r1 of the second instruction srli r1,r1,31. Furthermore, the destination operand r1 of the first instruction slli r1,r1,32 is equal to the source operand r1 of the second instruction srli r1,r1,31, thus meeting the register mode requirement. Therefore, instruction pair 1: slli r1,r1,32 and srli r1,r1,31 meet the instruction fusion mode and can be fused. When both instruction mode and register mode are met, instruction fusion is performed on two adjacent instructions that meet the requirements to obtain a fused instruction. Simultaneously, the instruction control signal for the fusion instruction (i.e., the second instruction control signal) is generated, setting the validity bit and flag bit of the fusion instruction to the first state, and setting the validity bit and flag bit of the second instruction to the second state. Here, a true first state and a false second state indicate that the second instruction is invalid. The second instruction control signal includes the operation type of the fusion instruction, the destination register number of the destination operand, and the register number of the source operand. For example, instruction pair 1: slli r1,r1,32 and srli r1,r1,31, after instruction fusion, yields the fusion instruction szew1 rd,rs1,rs2. Here, szew1 is the instruction name corresponding to the operation type of this fusion instruction, rd is the destination register number, and rs1 and rs2 are the register numbers of the source operands. Because both the fusion instruction and the original instruction's instruction control signals contain one destination operand and two source operands, the same execution unit can be reused.

[0049] Finally, the fusion instruction execution unit executes the fusion instruction according to the fusion instruction's operational logic.

[0050] Specifically, the instruction execution unit receives the out-of-order fusion instruction sent by the reserved station and determines whether the flag bit of the out-of-order fusion instruction is in the first state (i.e., whether it is true). If so, it sends the out-of-order fusion instruction to the fusion instruction execution unit. Figure 4 As shown, Figure 4This is a schematic diagram of instruction fusion provided in an embodiment of this application. Each instruction obtained after processing by the fusion decoding unit, in addition to having a corresponding second instruction control signal and a valid bit, also has a corresponding flag bit. If both the valid bit and the flag bit are false, it indicates that the instruction has been generated into a fused instruction along with other instructions. For example... Figure 4 In the process, instruction 3 and instruction 2 generate a fused instruction, which is located at the position of instruction 2. Instruction 3 is marked as an invalid instruction accordingly. The fused instruction, along with the unfused instruction, undergoes out-of-order scheduling steps such as renaming, dispatching, and accessing registers before arriving at the reservation station to await scheduling.

[0051] It should be noted that the fusion instruction execution unit in the implementation scheme of this application is not a functional unit independent of the instruction execution unit. The fused instruction and the unfused instruction reuse the same instruction execution unit. That is to say, the instruction execution unit contains two kinds of logic. First, the original execution logic of the unfused instruction; second, the execution logic of the fused instruction. The fusion instruction execution unit executes the fused instruction according to the operation logic of the fused instruction.

[0052] This embodiment reduces the number of instructions executed by the superscalar processor by using a fusion decoding unit, thereby reducing execution time and improving operating efficiency. Furthermore, the fused instructions obtained after instruction fusion processing contain the same number of destination and source operands as the original instructions, allowing for the reuse of existing instruction execution units without requiring a separate instruction execution unit, thus reducing costs.

[0053] The second scenario occurs when two adjacent instructions in any instruction pair do not conform to the instruction pattern. In this case, instruction fusion is not performed, and the instructions are executed according to their original operational logic.

[0054] First, the decoding unit obtains the first instruction control signal of each of the multiple instructions to be executed, and sends the first instruction control signal to the fusion decoding unit.

[0055] Specifically, after the decoding unit receives multiple instructions from the instruction buffer, before determining the instruction fusion mode, the decoding unit performs a decoding operation to obtain the first instruction control signal for each instruction. This first instruction control signal contains the destination operand and the source operand of the instruction. For example, in instruction 1: slli r1,r1,1, the first bit r1 is the destination operand of instruction 1, the second bit r1 is the source operand of instruction 1, and the third bit 1 is the source operand of instruction 1. To determine the instruction fusion mode for the multiple instructions, the decoding unit sends the first instruction control signal of each instruction in the decoded instructions to the fusion decoding unit for judgment.

[0056] Then, if there is no matching instruction pair among the preset multiple instruction pairs, it is determined that the two adjacent instructions do not conform to the instruction pattern. The fusion decoding unit then sets the valid bit of the first instruction to the first state and the flag bit to the second state, and sets the valid bit of the second instruction to the first state and the flag bit to the second state.

[0057] Finally, the instruction execution unit receives the out-of-order first and second instructions sent by the reserved station, and determines whether the flag bits of the out-of-order first and second instructions are in the second state. If so, it sends the out-of-order first and second instructions to the non-fusion instruction execution unit. The second state is false. The instruction execution unit includes a fusion instruction execution unit and a non-fusion instruction execution unit. The fusion instruction execution unit executes the fusion instruction according to the logic of the fusion instruction, while the non-fusion instruction execution unit executes the first instruction according to the operation logic of the first instruction and the second instruction according to the operation logic of the second instruction.

[0058] The third scenario is when two adjacent instructions in any instruction pair do not conform to register mode. In this case, instruction fusion is not performed, and the instructions are executed according to their original operation logic.

[0059] First, the decoding unit obtains the first instruction control signal of each of the multiple instructions to be executed, and sends the first instruction control signal to the fusion decoding unit.

[0060] Specifically, after the decoding unit receives multiple instructions from the instruction buffer, before determining the instruction fusion mode, the decoding unit performs a decoding operation to obtain the first instruction control signal for each instruction. This first instruction control signal contains the destination operand and the source operand of the instruction. For example, in instruction 1: slli r1,r1,1, the first bit r1 is the destination operand of instruction 1, the second bit r1 is the source operand of instruction 1, and the third bit 1 is the source operand of instruction 1. To determine the instruction fusion mode for the multiple instructions, the decoding unit simultaneously sends the first instruction control signal of each instruction from the decoded instructions to the fusion decoding unit for evaluation.

[0061] Then, if the source operand and destination operand of the first instruction are not equal, or if the destination operand of the first instruction is not equal to any of the source operands of the second instruction, the fusion decoding unit sets the validity bit of the first instruction to a first state and the flag bit to a second state, and sets the validity bit of the second instruction to a first state and the flag bit to a second state. The first state is true, and the second state is false.

[0062] Finally, the instruction execution unit receives the out-of-order first and second instructions sent by the reserved station, and determines whether the flag bits of the out-of-order first and second instructions are in the second state. If so, it sends the out-of-order first and second instructions to the non-fusion instruction execution unit. The second state is false. The instruction execution unit includes a fusion instruction execution unit and a non-fusion instruction execution unit. The fusion instruction execution unit executes the fusion instruction according to the logic of the fusion instruction, while the non-fusion instruction execution unit executes the first instruction according to the operation logic of the first instruction and the second instruction according to the operation logic of the second instruction.

[0063] Please see Figure 5 , Figure 5 This is an overall schematic diagram of an embodiment of the present application for determining whether two adjacent instructions conform to the instruction fusion mode.

[0064] Specifically, the process involves determining whether the first instruction in an instruction pair is an I-type instruction, whether the second instruction is an I-type instruction or an R-type instruction, and whether a pre-defined set of instruction pairs exists that matches any one of the instruction pairs, i.e., the instruction pattern. If neither matches, normal instruction decoding is performed. If both matches, the process checks whether the source operand and destination operand of the first instruction are equal, and whether the destination operand of the first instruction is equal to at least one source operand of the second instruction. If neither matches, normal instruction decoding is performed. If both matches, the first and second instructions are fused to obtain a fused instruction.

[0065] Based on the description of the above embodiments of the method for instruction fusion using a superscalar processor, please refer to... Figure 6 , Figure 6 A schematic diagram of a superscalar processor for instruction fusion is provided as an embodiment of this application, as shown below. Figure 6 As shown, it includes a decoding unit 601, a fusion decoding unit 602, and an instruction execution unit 603. The instruction execution unit 603 includes a fusion instruction execution unit 6031, wherein:

[0066] The decoding unit 601 is used to obtain the first instruction control signal of each instruction among the multiple instructions to be executed, and send the first instruction control signal to the fusion decoding unit 602;

[0067] The fusion decoding unit 602 is used to obtain at least one instruction pair consisting of two adjacent instructions from multiple instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, and the second instruction in the instruction pair is an I-type instruction or an R-type instruction. It also determines whether there is an instruction pair among the preset multiple instruction pairs that matches the instruction pair. If there is, then, if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction.

[0068] The fusion instruction execution unit 6031 is used to execute fusion instructions according to the operation logic of fusion instructions.

[0069] In one possible implementation, the fusion decoding unit 602 is further configured to, if there is no instruction pair among the plurality of instruction pairs that matches any one of the instruction pairs, set the validity bit of the first instruction to a first state and the flag bit to a second state, and set the validity bit of the second instruction to a first state and the flag bit to a second state.

[0070] In one possible implementation, the fusion decoding unit 602 is further configured to, when the source operand and destination operand of the first instruction are not equal or the destination operand of the first instruction is not equal to any one of the source operands of the second instruction, set the valid bit of the first instruction to a first state and the flag bit to a second state, and set the valid bit of the second instruction to a first state and the flag bit to a second state.

[0071] In one possible implementation, the fusion decoding unit 602 is further configured to generate a second instruction control signal for the fusion instruction, set the valid bit of the fusion instruction to a first state and the flag bit to a first state, and set the valid bit of the second instruction to a second state and the flag bit to a second state.

[0072] In one possible implementation, the instruction execution unit further includes a non-fusion instruction execution unit;

[0073] The instruction execution unit 603 is used to receive the first instruction and the second instruction after out-of-order scheduling sent by the reserved station, determine whether the flag bits of the first instruction and the second instruction after out-of-order scheduling are in the second state, and if so, send the first instruction and the second instruction after out-of-order scheduling to the non-converged instruction execution unit.

[0074] A non-fusion instruction execution unit is used to execute a first instruction according to the operation logic of a first instruction and to execute a second instruction according to the operation logic of a second instruction.

[0075] In one possible implementation, the instruction execution unit 603 is further configured to receive the fusion instruction after out-of-order scheduling sent by the reserved station, determine whether the flag bit of the fusion instruction after out-of-order scheduling is in the first state, and if so, send the fusion instruction after out-of-order scheduling to the fusion instruction execution unit 6031.

[0076] In one possible implementation, the second instruction control signal includes the operation type of the fused instruction, the destination register number where the destination operand is located, and the register number where the source operand is located.

[0077] in, Figure 6 The specific implementation of the superscalar processor shown is in Figures 1-5 The embodiments shown have already been described, and they can achieve the same or similar beneficial effects. To avoid repetition, they will not be repeated here.

[0078] Based on the description of the above embodiments, this application also provides a computer device. Please refer to... Figure 7 , Figure 7 This is a schematic diagram of a computer device provided in an embodiment of this application. The computer device includes at least a processor 701 and a memory 702. The processor 701 is connected to the memory 702, which stores computer programs. The processor 701 executes the computer programs stored in the memory 702. The memory 702 can be stored in the computer device's memory. The memory 702 stores computer programs, which include program instructions. The processor 701 executes the program instructions stored in the memory 702. The processor 701 (or CPU (Central Processing Unit)) is the computing and control core of the computer device, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to achieve corresponding method flows or corresponding functions.

[0079] In one embodiment, the processor 701 of the computer device provided in this application can be used for processing a series of instruction fusion methods:

[0080] Obtain the first instruction control signal for each of the multiple instructions to be executed;

[0081] Obtain at least one instruction pair consisting of two adjacent instructions from multiple instructions. For any instruction pair in the at least one instruction pair, determine, based on the first instruction control signal of the instruction in the instruction pair, whether the first instruction in the instruction pair is an I-type instruction, and whether the second instruction in the instruction pair is an I-type instruction or an R-type instruction. Also, determine whether there is an instruction pair among the preset multiple instruction pairs that matches any instruction pair. If there is, then, if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, perform instruction fusion on the first instruction and the second instruction to obtain a fused instruction.

[0082] The fusion instruction is executed according to the operation logic of the fusion instruction.

[0083] In another embodiment, the processor 701 is further configured to, if there is no instruction pair among the plurality of instruction pairs that matches any one of the instruction pairs, set the validity bit of the first instruction to a first state and the flag bit to a second state, and set the validity bit of the second instruction to a first state and the flag bit to a second state.

[0084] In another embodiment, the processor 701 is further configured to, when the source operand and destination operand of the first instruction are not equal or the destination operand of the first instruction is not equal to any of the source operands of the second instruction, set the validity bit of the first instruction to a first state and the flag bit to a second state, and set the validity bit of the second instruction to a first state and the flag bit to a second state.

[0085] In another embodiment, the processor 701 is further configured to generate a second instruction control signal for the fusion instruction, set the valid bit of the fusion instruction to a first state and the flag bit to a first state, and set the valid bit of the second instruction to a second state and the flag bit to a second state.

[0086] In another embodiment, the processor 701 is further configured to determine whether the flag bits of the first instruction and the second instruction after out-of-order scheduling are in the second state. If so, the processor executes the first instruction according to the operation logic of the first instruction and executes the second instruction according to the operation logic of the second instruction.

[0087] In another embodiment, before executing the fusion instruction according to the operation logic of the fusion instruction, the processor 701 is also used to determine whether the flag bit of the fusion instruction after out-of-order scheduling is in the first state.

[0088] In another embodiment, the second instruction control signal includes the operation type of the fused instruction, the destination register number where the destination operand is located, and the register number where the source operand is located.

[0089] For example, the computer device can be a server, a computer, a virtual machine, etc., and the processor 701 can be... Figure 6 The superscalar processor for instruction fusion shown in the diagram includes, but is not limited to, processor 701 and memory 702. Those skilled in the art will understand that the diagram is merely an example of a computer device and does not constitute a limitation on the computer device; it may include more or fewer components than shown, or combine certain components, or use different components.

[0090] It should be noted that since the computer device implements the steps in the above-described method of instruction fusion using a superscalar processor when executing a computer program, all embodiments of the above-described method of instruction fusion using a superscalar processor are applicable to the computer device and can achieve the same or similar beneficial effects.

[0091] This application also provides a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in a terminal and extended storage media supported by the terminal. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by the processor 701. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device; optionally, it can also be at least one computer-readable storage medium located remotely from the aforementioned processor 701. In one embodiment, the processor 701 can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the above-described method for instruction fusion using a superscalar processor.

[0092] For example, a computer program on a computer-readable storage medium includes computer program code, which may be in the form of source code, object code, executable file, or some intermediate form. Computer-readable media may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0093] It should be noted that since the computer program on the computer-readable storage medium implements the steps in the above-described method of instruction fusion using a superscalar processor when executed by a processor, all embodiments of the above-described method of instruction fusion using a superscalar processor are applicable to the computer-readable storage medium and can achieve the same or similar beneficial effects.

[0094] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A superscalar processor for instruction fusion, characterized in that, It includes a decoding unit, a fusion decoding unit, and an instruction execution unit, wherein the instruction execution unit includes a fusion instruction execution unit; The decoding unit is used to acquire the first instruction control signal of each instruction among the multiple instructions to be executed, and send the first instruction control signal to the fusion decoding unit; The fusion decoding unit is used to obtain at least one instruction pair consisting of two adjacent instructions from the plurality of instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, the second instruction in the instruction pair is an I-type instruction or an R-type instruction, and determines whether there is an instruction pair that matches the instruction pair among the preset plurality of instruction pairs. If they exist, then if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction. In determining whether there is an instruction pair that matches any one of the preset instruction pairs, the fusion decoding unit is specifically used to: match the first instruction control signal of the instruction in the arbitrary instruction pair with the instruction control signal of the instruction in the plurality of instruction pairs to determine whether there is an instruction pair that matches any one of the instruction pairs. The fusion instruction execution unit is used to execute the fusion instruction according to the operation logic of the fusion instruction.

2. The superscalar processor according to claim 1, characterized in that, The fusion decoding unit is further configured to, if there is no instruction pair among the plurality of instruction pairs that matches any one of the instruction pairs, set the validity bit of the first instruction to a first state and the flag bit to a second state, and set the validity bit of the second instruction to a first state and the flag bit to a second state.

3. The superscalar processor according to claim 1, characterized in that, The fusion decoding unit is further configured to set the validity bit of the first instruction to a first state and the flag bit to a second state, and to set the validity bit of the second instruction to a first state and the flag bit to a second state, when the source operand and destination operand of the first instruction are not equal or the destination operand of the first instruction is not equal to any one of the source operands of the second instruction.

4. The superscalar processor according to any one of claims 1-3, characterized in that, The fusion decoding unit is further configured to generate a second instruction control signal for the fusion instruction, set the valid bit of the fusion instruction to a first state and the flag bit to a first state, and set the valid bit of the second instruction to a second state and the flag bit to a second state.

5. The superscalar processor according to claim 2 or 3, characterized in that, The instruction execution unit further includes a non-fusion instruction execution unit; The instruction execution unit is used to receive the first instruction and the second instruction after out-of-order scheduling sent by the retention station, determine whether the flag bits of the first instruction and the second instruction after out-of-order scheduling are in the second state, and if so, send the first instruction and the second instruction after out-of-order scheduling to the non-fusion instruction execution unit. The non-fusion instruction execution unit is used to execute the first instruction according to the operation logic of the first instruction and to execute the second instruction according to the operation logic of the second instruction.

6. The superscalar processor according to claim 1, characterized in that, The instruction execution unit is further configured to receive the fusion instruction sent by the reserved station after out-of-order scheduling, determine whether the flag bit of the fusion instruction after out-of-order scheduling is in the first state, and if so, send the fusion instruction after out-of-order scheduling to the fusion instruction execution unit.

7. The superscalar processor according to claim 4, characterized in that, The second instruction control signal includes the operation type of the fusion instruction, the destination register number where the destination operand is located, and the register number where the source operand is located.

8. A method for instruction fusion using the superscalar processor according to any one of claims 1-7, characterized in that, The superscalar processor includes a decoding unit, a fusion decoding unit, and an instruction execution unit, wherein the instruction execution unit includes a fusion instruction execution unit. The decoding unit acquires the first instruction control signal of each instruction among the multiple instructions to be executed, and sends the first instruction control signal to the fusion decoding unit; The fusion decoding unit acquires at least one instruction pair consisting of two adjacent instructions from the plurality of instructions. For any instruction pair in the at least one instruction pair, based on the first instruction control signal of the instruction in the instruction pair, it determines that the first instruction in the instruction pair is an I-type instruction, the second instruction in the instruction pair is an I-type instruction or an R-type instruction, and determines whether there is an instruction pair among the preset plurality of instruction pairs that matches the instruction pair. If they exist, then if the source operand and destination operand of the first instruction are equal and the destination operand of the first instruction is equal to at least one source operand of the second instruction, the first instruction and the second instruction are fused to obtain a fused instruction. The step of determining whether there is an instruction pair that matches any one of the preset multiple instruction pairs includes: matching the first instruction control signal of the instruction in the arbitrary instruction pair with the instruction control signal of the instruction in the multiple instruction pairs to determine whether there is an instruction pair that matches any one of the multiple instruction pairs. The fusion instruction execution unit executes the fusion instruction according to the operation logic of the fusion instruction.

9. A computer device, characterized in that, include: A processor and a memory, the processor being connected to the memory for storing computer programs, and the processor for executing the computer programs stored in the memory to cause the computer device to perform the method as described in claim 8.

10. A computer-readable storage medium, characterized in that, A computer-readable storage medium stores a computer program that is executed by a processor to implement the method as claimed in claim 8.

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