DPU-based register diagnosis method, system and equipment and storage medium
By implementing pure software register diagnostic methods on DPU, using MRS/MSR and SMC instructions for secure and flexible register access, the shortcomings of hardware debuggers in mass production environments are solved, the universality and security of diagnosis is improved, and the cost is reduced.
Patent Information
- Application Number
- CN202411856432.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-04-15
AI Technical Summary
The existing hardware debugger-based register diagnostic methods have shortcomings in terms of physical access, security and cost, which are difficult to use in mass production environments, and have security risks and high authorization fees.
It provides a pure software register diagnosis method based on DPU. By judging the exception level and security status in the kernel state, using MRS/MSR instructions or SMC instructions for register access, ensuring security and access rights, and recording diagnostic results to analyze faults.
Improves the universality and security of the diagnostic process, reduces costs, can still be used when the debug interface is disabled in mass-produced products, and provides a unified way to access registers of all exception levels.
Smart Images
Figure CN119829306A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of register diagnosis of a data processing unit (DPU), and in particular to a register diagnosis method, system, device and storage medium based on a DPU. Background Art
[0002] With the development of cloud technology and big data technology, massive computing has become the mainstream. In order to unload the pressure of CPU, smart network card (Data Processing Unit, DPU) came into being. Smart network card generally has network card (NIC) and solid state storage device (SSD) or hard disk (HDD). Smart network card can provide network and storage as well as encryption and decryption functions.
[0003] In the DPU designed based on the Arm64 architecture, the debug access port (DAP) provides a hardware means to access system registers, usually through the Joint Test Action Group (JTAG) or Serial Wire Debug (SWD). This type of interface allows developers to directly access memory and registers during the debugging or testing phase, including registers at different exception levels (EL0-EL3), where EL0 is the lowest privilege level, usually used for user-mode applications; EL1 is the operating system kernel state; EL2 is the Hypervisor mode for virtualization extensions; EL3 is the highest privilege level, usually used for secure monitors or bootloaders.
[0004] This type of method based on the hardware debugging interface can bypass software restrictions and directly access register states, even registers in the safe state. It is also real-time and can directly read and write registers during system operation without software intervention. Commonly used hardware debuggers include: ARM's Dstream hardware debugger or Lauterbach's Trace32 hardware debugger.
[0005] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the connection between the hardware debugger and the debugged device in the prior art. When the ArmDS software is connected to the target device, the system register information can be viewed and edited in the register view interface of the ArmDS software. Figure 2 shown.
[0006] However, the existing hardware debugger-based method also has some shortcomings:
[0007] First, the debugging interface usually requires a physical connection to the hardware device, which makes it difficult to use in a mass production environment, especially in some stress testing environments.
[0008] Secondly, once the debug interface is enabled, the system may be exposed to external attackers, increasing the security risk of the system. To prevent this, the production environment usually disables the debug interface, but this in turn limits debugging and testing.
[0009] In addition, using a hardware debugger requires high licensing fees, which increases development and testing costs.
[0010] In summary, the existing hardware debugger-based methods have obvious deficiencies in physical access, security, and cost, and a new technical solution is needed to solve these problems. Summary of the invention
[0011] The technical problem to be solved by the present application is to provide a DPU-based register diagnosis method, system, device and storage medium, which can improve the versatility and security of the diagnosis process and reduce costs.
[0012] To solve the above technical problems, as one aspect of the present application, a register diagnosis method based on a DPU is provided, which comprises the following steps:
[0013] In kernel mode, the exception level of the current core and the security status of the register to be accessed are determined, wherein the exception level is EL0-EL2 which allows direct reading and writing of the corresponding register, or EL3 which does not allow direct reading and writing of the corresponding register, and the security status is: secure register or non-secure register;
[0014] If the current exception level allows direct reading and writing of the corresponding register, and the non-secure register to be accessed, use the MRS / MSR instruction to directly read or write the register;
[0015] If the current exception level does not allow direct reading and writing of the corresponding register, or the security register that needs to be accessed, the core is switched to the EL3 exception level through the SMC instruction; at the EL3 exception level, the required registers are read and written; after the reading and writing are completed, the core is switched back to the original exception level through the SMC instruction.
[0016] The following steps are also included:
[0017] Before executing the SMC instruction to switch the exception level, the context information of the current core is saved so as to be restored when switching back to the original exception level.
[0018] The following steps are also included:
[0019] When reading and writing registers, set the corresponding access rights according to the type and security status of the register to ensure that only authorized users or programs can perform read and write operations.
[0020] The following steps are also included:
[0021] The results of the register diagnosis are recorded in the form of logs and stored in the storage medium of the DPU, and the recorded logs are analyzed to identify possible register failures or abnormal behaviors.
[0022] Accordingly, another aspect of the present application further provides a DPU-based register diagnostic system, which at least includes:
[0023] The abnormal level and security state judgment module is used to judge the abnormal level of the current core and the security state of the register to be accessed in the kernel state, wherein the abnormal level is EL0-EL2 which allows direct reading and writing of the corresponding register, or EL3 which does not allow direct reading and writing of the corresponding register, and the security state is: secure register or non-secure register;
[0024] Direct access module, used to use MRS / MSR instructions to directly read or write the corresponding register when the current exception level allows direct reading and writing of the corresponding register and the non-secure register to be accessed;
[0025] The SMC switching processing module is used to switch the core to the EL3 exception level through the SMC instruction when the current exception level does not allow direct reading and writing of the corresponding register, or when the security register needs to be accessed; at the EL3 exception level, read and write the required registers; after the reading and writing are completed, switch the core back to the original exception level through the SMC instruction.
[0026] Wherein, the SMC switching processing module also includes:
[0027] The context save and restore module is used to save the context information of the current core before executing the SMC instruction to switch the exception level, and restore it when switching back to the original exception level.
[0028] Among them, it also includes:
[0029] The access permission control module is used to set corresponding access permissions according to the type and security status of the register when reading and writing the register, so as to ensure that only authorized users or programs can perform read and write operations.
[0030] Among them, it also includes:
[0031] The logging module is used to record the results of register diagnosis in the form of logs, store them in the storage medium of the DPU, and analyze the recorded logs to identify possible register failures or abnormal behaviors.
[0032] Accordingly, as another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned method are implemented.
[0033] Correspondingly, as another aspect of the present application, there is also provided an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the functions of the aforementioned system when executing the computer program.
[0034] Implementing this embodiment has the following beneficial effects:
[0035] The present application provides a DPU-based register diagnosis method, system, device and storage medium. By adopting a pure software solution, it does not rely on a hardware debugger and can still be used even when the debug interface is disabled in mass-produced products.
[0036] The software solution of this application can be easily integrated into the stress testing environment, improving the convenience and efficiency of the test.
[0037] In the present application, the high licensing fees of the hardware debugger are avoided, making the cost negligible.
[0038] In the present application, a unified method is provided to access registers of all exception levels of EL0, EL1, EL2, and EL3 in kernel mode, including registers in secure and non-secure states, thereby enhancing the flexibility and comprehensiveness of register access. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying creative labor, other drawings obtained based on these drawings still belong to the scope of the present application.
[0040] Figure 1 A schematic diagram of the connection between a hardware debugger and a debugged device in the prior art;
[0041] Figure 2 It is a schematic diagram of the register viewing interface of the ArmDS software used in the prior art;
[0042] Figure 3 A schematic diagram of an Arm64 architecture involved in this application;
[0043] Figure 4 A schematic diagram of the main process of an embodiment of a DPU-based register diagnosis method provided by the present application;
[0044] Figure 5 A more detailed flowchart of the method of the present application;
[0045] Figure 6 A schematic diagram of the structure of an embodiment of a DPU-based register diagnostic system provided in the present application. DETAILED DESCRIPTION
[0046] In order to make the objectives, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in conjunction with the accompanying drawings.
[0047] like Figure 3 As shown, a schematic diagram of the Arm64 architecture involved in this application is shown. Among them, the Arm64 architecture has 4 ELs and two security states, such as Figure 5 As shown. In general, the EL where the current core is located can only read the registers corresponding to the current or lower exception level. For example, if the current core is running in EL1, it can only read the registers of EL0 and EL1, and cannot read the registers of EL2 and EL3. In addition to the EL restrictions, there are also security level restrictions. The secure state can access the secure state register and the non-secure state register at the same time, but the non-secure state can only access the non-secure state register and cannot access the secure state register.
[0048] like Figure 4 FIG. 1 is a schematic diagram showing a main flow chart of an embodiment of a DPU-based register diagnosis method provided by the present application; and FIG. Figure 5 A more detailed flow chart of the present invention is shown in FIG. 1 . In this embodiment, the method comprises the following steps:
[0049] Step S10, in kernel mode, determining the exception level of the current core and the security state of the register to be accessed, wherein the exception level is EL0-EL2 which allows direct reading and writing of the corresponding register, or EL3 which does not allow direct reading and writing of the corresponding register, and the security state is: secure register or non-secure register;
[0050] Step S11, if the current exception level allows direct reading and writing of the corresponding register, and the non-secure register to be accessed is a non-secure register, then the MRS / MSR instruction is used to directly read or write the register;
[0051] It can be understood that in the Arm architecture, MRS / MSR instructions are provided for reading and writing architecture-related system registers.
[0052] Among them, the MRS instruction is a transfer instruction from the state register to the general register (Move to Register from State register), which is used to transfer the content of the program status register (CPSR or SPSR) to the general register. This is usually used in the following situations:
[0053] When the contents of the program status register need to be changed, the contents of the program status register can be read into the general register using MRS first, and then written back to the program status register after modification.
[0054] When exception handling or process switching occurs, the value of the program status register needs to be saved. You can first use MRS to read the value of the program status register and then save it.
[0055] The format of the MRS instruction is shown below.
[0056] Encoding
[0057] MRS <xt> ，( <systemreg> |S <op0> _ <op1> _ <cn> _ <cm> _ <op2>).
[0059] The MSR instruction is a general register to state register transfer instruction (Move from State register to Register), which is used to transfer the contents of the operand to a specific field of the program status register. In simple terms, the MSR instruction is used to write data from a general register to a system register. This is usually used to restore or change the contents of the program status register. When used, the field to be operated is generally specified in the MSR instruction.
[0060] The format of the MSR instruction is shown below.
[0061] Encoding
[0062] MSR( <systemreg> |S <op0> _ <op1> _ <cn> _ <cm> _ <op2> )， <xt>.
[0064] MRS and MSR instructions play an important role in the Arm architecture. They enable the processor to dynamically read and modify the state of system registers at runtime, thereby implementing various advanced functions.
[0065] Step S12: If the current exception level does not allow direct reading and writing of the corresponding register, or the security register that needs to be accessed is a security register, the core is switched to the EL3 exception level through a security monitoring call (SMC) instruction; at the EL3 exception level, the required registers are read and written; after the reading and writing are completed, the core is switched back to the original exception level through an SMC instruction.
[0066] It is understandable that the Secure Monitor Call (SMC) instruction is a special instruction in the ARM architecture for switching between different security states. It can switch between different exception levels (EL), for example, from a lower exception level group (such as EL0, EL1, EL2) to the most common exception level EL3. In this application, the calling process of the SMC instruction is as follows:
[0067] Entering Monitor mode: Through the SMC instruction, the processor enters Monitor mode and backs up the context of the non-secure area.
[0068] Switch to the security zone: Enter the privileged mode of the security zone and execute corresponding security services.
[0069] Return to non-safe area: After completing the safety service, return to the non-safe area.
[0070] In a specific example, the step S12 further includes the following steps:
[0071] Before executing the SMC instruction to switch the exception level, the context information of the current core is saved so as to be restored when switching back to the original exception level.
[0072] In a specific example, in the present application, the method further comprises the following steps:
[0073] When reading and writing registers, the corresponding access rights are set according to the type and security status of the register to ensure that only authorized users or programs can perform read and write operations. Generally, this can be achieved through a permission management mechanism such as an operating system or a specific security policy.
[0074] In a specific example, in the present application, the method further comprises the following steps:
[0075] The results of the register diagnosis are recorded in the form of logs and stored in the storage medium of the DPU, and the recorded logs are analyzed to identify possible register failures or abnormal behaviors. Specifically, in the logs, such as the value of the register, access time, accessor information, etc., can be recorded, and the log analysis can involve detecting abnormal values, identifying potential failures, etc.
[0076] It is understandable that in this application, a unified way is provided to access registers of all ELs of EL0, EL1, EL2, and EL3 in kernel state, including secure and non-secure ones. The main idea of this solution is that when the core is in kernel state and the current exception level can read and write the corresponding registers or access non-secure registers, the MRS and MSR instructions are used to read directly. Otherwise, it is necessary to switch the core to EL3 through SMC call, and any register can be read and written in EL3, and then returned to kernel state.
[0077] In this application, the exception level and security state management mechanism of the ARM architecture is used to ensure correct switching and access to registers between different security levels and exception levels. The current security state and exception level are judged by software logic to decide whether to use direct access or access after switching through the SMC. This method can be easily integrated into the kernel of the operating system as part of system diagnosis or debugging. By writing a specific diagnostic program or script, this method can be called when needed to perform register diagnosis. Since it does not rely on an external hardware debugging interface, the risk of external attacks on the system is reduced. Access rights are controlled by software logic to ensure that only authorized users or programs can perform register diagnostic operations.
[0078] like Figure 6 FIG. 1 is a schematic diagram showing a structure of an embodiment of a DPU-based register diagnostic system provided by the present application. In this embodiment, the DPU-based register diagnostic system 1 at least includes:
[0079] The abnormal level and security state judgment module 10 is used to judge the abnormal level of the current core and the security state of the register to be accessed in the kernel state, wherein the abnormal level is EL0-EL2 which allows direct reading and writing of the corresponding register, or EL3 which does not allow direct reading and writing of the corresponding register, and the security state is: secure register or non-secure register;
[0080] A direct access module 11 is used to use MRS / MSR instructions to directly read or write the corresponding register when the current exception level allows direct reading and writing of the corresponding register and the non-secure register to be accessed;
[0081] The SMC switching processing module 12 is used to switch the core to the EL3 exception level through the SMC instruction when the current exception level does not allow direct reading and writing of the corresponding register, or when the security register needs to be accessed; at the EL3 exception level, read and write the required registers; after the reading and writing are completed, switch the core back to the original exception level through the SMC instruction.
[0082] Wherein, the SMC switching processing module 12 further includes:
[0083] The context saving and restoring module 20 is used to save the context information of the current core before executing the SMC instruction to switch the exception level, and to restore it when switching back to the original exception level.
[0084] Among them, it also includes:
[0085] The access permission control module 13 is used to set corresponding access permissions according to the type and security status of the register when reading and writing the register, so as to ensure that only authorized users or programs can perform read and write operations.
[0086] Among them, it also includes:
[0087] The log recording module 14 is used to record the results of the register diagnosis in the form of logs, store them in the storage medium of the DPU, and analyze the recorded logs to identify possible register faults or abnormal behaviors.
[0088] For more details, please refer to and combine the above Figures 3 to 5 The description is not repeated here.
[0089] Accordingly, as another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned method are implemented.
[0090] Correspondingly, as another aspect of the present application, there is also provided an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the functions of the aforementioned system when executing the computer program.
[0091] Implementing this embodiment has the following beneficial effects:
[0092] The present application provides a DPU-based register diagnosis method, system, device and storage medium. By adopting a pure software solution, it does not rely on a hardware debugger and can still be used even when the debug interface is disabled in mass-produced products.
[0093] The software solution of this application can be easily integrated into the stress testing environment, improving the convenience and efficiency of the test.
[0094] In the present application, the high licensing fees of the hardware debugger are avoided, making the cost negligible.
[0095] In the present application, a unified method is provided to access registers of all exception levels of EL0, EL1, EL2, and EL3 in kernel mode, including registers in secure and non-secure states, thereby enhancing the flexibility and comprehensiveness of register access.
[0096] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
[0097] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0098] The above disclosure is only a preferred embodiment of the present application, and certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.< / xt> < / op2> < / cm> < / cn> < / op1> < / op0> < / systemreg> < / cm> < / cn> < / op1> < / op0> < / systemreg> < / xt>
Claims
1. A register diagnosis method based on DPU, characterized in that: The method comprises the following steps: In kernel mode, the exception level of the current core and the security state of the register to be accessed are determined, wherein the exception level is EL0 to EL2 which allows direct reading and writing of the corresponding register, or EL3 which does not allow direct reading and writing of the corresponding register, and the security state is a secure register or a non-secure register; If the current exception level allows direct reading and writing of the corresponding register, and the non-secure register to be accessed, use the MRS / MSR instruction to directly read or write the register; If the current exception level does not allow direct reading and writing of the corresponding register, or the security register that needs to be accessed, the core is switched to the EL3 exception level through the SMC instruction; at the EL3 exception level, the required registers are read and written; after the reading and writing are completed, the core is switched back to the original exception level through the SMC instruction.
2. The method according to claim 1, characterized in that The following steps are also included: Before executing the SMC instruction to switch the exception level, the context information of the current core is saved so as to perform recovery processing when switching back to the original exception level.
3. The method according to claim 1, characterized in that The following steps are also included: When reading and writing registers, set the corresponding access rights according to the type and security status of the register to ensure that only authorized users or programs can perform read and write operations.
4. The method according to claim 1, characterized in that The following steps are also included: The results of the register diagnosis are recorded in the form of logs and stored in the storage medium of the DPU, and the recorded logs are analyzed to identify possible register failures or abnormal behaviors.
5. A DPU-based register diagnostic system, characterized in that: At least: The exception level and security state judgment module is used to judge the exception level of the current core and the security state of the register to be accessed in the kernel state; the exception level is EL0-EL2 which allows direct reading and writing of the corresponding register, or EL3 which does not allow direct reading and writing of the corresponding register, and the security state is: secure register or non-secure register; Direct access module, used to use MRS / MSR instructions to directly read or write the corresponding register when the current exception level allows direct reading and writing of the corresponding register and the non-secure register to be accessed; The SMC switching processing module is used to switch the core to the EL3 exception level through the SMC instruction when the current exception level does not allow direct reading and writing of the corresponding register, or when the security register needs to be accessed; At the EL3 exception level, read and write the required registers; after the reading and writing are completed, the core is switched back to the original exception level through the SMC instruction.
6. The system according to claim 5, characterized in that The SMC switching processing module also includes: The context save and restore module is used to save the context information of the current core before executing the SMC instruction to switch the exception level, and perform recovery processing when switching back to the original exception level.
7. The system according to claim 6, characterized in that Also includes: The access permission control module is used to set corresponding access permissions according to the type and security status of the register when reading and writing the register, so as to ensure that only authorized users or programs can perform read and write operations.
8. The system according to claim 5, characterized in that Also includes: The logging module is used to record the results of register diagnosis in the form of logs, store them in the storage medium of the DPU, and analyze the recorded logs to identify possible register failures or abnormal behaviors.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.
10. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the functions of the system according to any one of claims 5 to 8 are realized.