Airplane management computer software verification environment system

Abstract

The invention provides an aircraft management computer software verification environment system, and relates to the technical field of equipment testing. The system comprises VMC comprehensive test equipment, bus network node simulation equipment, bus data acquisition and analysis equipment and development and comprehensive test equipment, and an Ethernet, a reflective memory network and a bus network which are used in the system are constructed; wherein the Ethernet, the reflective memory network and the bus network are used in the system for data interaction and equipment control, and the operation of each test equipment is integrated and fixed through the verification environment cabinet, the verification environment finished product cabinet and the verification environment workbench, so that a worker does not need to sort the current environment architecture, and the test efficiency is improved. Therefore, the operation can be carried out at the position of the test equipment to be used in the corresponding functional area. According to the method, the requirement that multiple airborne finished products are subjected to aircraft management software verification at the same time is met, a standard fixed normal form of aircraft management software verification is achieved, and a system joint debugging and joint test verification environment of the airborne finished products is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of equipment testing, and in particular to an aircraft management computer software verification environment system. Background Art

[0002] The finished airborne products used on the aircraft need to undergo aircraft management software verification before leaving the factory; this includes airborne subsystem testing, dual V testing, 1394 network testing and weapons bay expansion, etc.

[0003] The traditional testing method is to independently build a verification environment for different airborne finished products. However, when conducting system integration and testing, the system integration and testing verification environment needs to be rearranged, which is inefficient and the workload will increase with the number of airborne finished products to be integrated and debugged. In addition, the operation of each test equipment is complicated and changeable, and there is no standard fixed paradigm. Staff need to sort out the current environmental architecture before they can go to the location of the test equipment to be used to operate.

[0004] Therefore, it is necessary to build an aircraft management computer software verification environment system to meet the needs of aircraft management software verification for multiple airborne finished products at the same time. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides an aircraft management computer software verification environment system, which aims to meet the needs of simultaneously performing aircraft management software verification on multiple airborne finished products, realize a standard fixed paradigm for aircraft management software verification, and provide a system joint debugging and testing verification environment for airborne finished products.

[0006] The present invention provides an aircraft management computer software verification environment system, which is used to coordinate multiple airborne finished products to simultaneously conduct linkage comprehensive experiments and provide a software verification environment, including VMC comprehensive test equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and comprehensive test equipment, and constructs Ethernet, reflective memory network and bus network for internal use of the system; wherein,

[0007] The VMC integrated test equipment includes a programmable power supply, a VCM integrated test microservice computer, a test subsystem PXI device, a disconnect box, a VMC integrated test client computer, an MFD simulation device and an MBT / GMP device; wherein the programmable power supply is electrically connected to each airborne finished product, the VCM integrated test microservice computer is electrically connected to the test subsystem PXI device, and is respectively connected to Ethernet and a reflective memory network; the test subsystem PXI device is also electrically connected to the disconnect box, the disconnect box is respectively electrically connected to each airborne finished product, the VMC integrated test client computer is connected to the Ethernet, the MFD simulation device is connected to the reflective memory network, the MBT / GMP device is connected to the Ethernet, and is communicatively connected to each airborne component through a bus network;

[0008] The bus network node simulation device comprises a bus network node simulation client computer and a bus network node simulation PXI chassis; wherein the bus network node simulation client computer is respectively connected to the Ethernet and the reflective memory network, and the bus network node simulation PXI chassis is connected to each airborne finished product through the bus network, and is respectively connected to the Ethernet and the reflective memory network;

[0009] The bus data acquisition and analysis equipment includes a disk array, a server, a bus data acquisition client computer, a bus data acquisition front-end computer and a bus data acquisition front-end PXI chassis; wherein the disk array, the server, the bus data acquisition client computer, the bus data acquisition front-end computer and the bus data acquisition front-end PXI chassis are respectively connected to the Ethernet, the bus data acquisition front-end PXI chassis is connected to the reflective memory network, and is communicatively connected to each airborne finished product through the bus network; the development and comprehensive test equipment is set up through the VMC debugging computer, and is electrically connected to each airborne finished product respectively; the airborne finished products are also communicatively connected to the bus repeater through the bus network.

[0010] As a further solution, the bus network is a 1394 bus network set up based on the 1394 protocol and enhanced with the AS5643 protocol group, connecting the devices to achieve device-to-device bus communication connection; the reflective memory network connects the reflective memory cards of the devices through a reflective memory switch, and achieves memory-to-memory memory communication connection between the devices; the Ethernet connects the 10 Gigabit network cards of the devices through a network switch, and achieves device-to-device network communication connection between the devices.

[0011] As a further solution, testing instruments are also provided; wherein, the testing instruments include a digital multimeter, an oscilloscope and a signal generator, and the disconnect box is also electrically connected to the digital multimeter, the oscilloscope and the signal generator respectively.

[0012] As a further solution, the VMC integrated test equipment includes a VMC integrated test equipment-PXI chassis, a cascade card, a first remote control card, a power SPST card group, a signal SPDT card group and a single-line matrix card group; wherein the first remote control card is electrically connected to the second remote control card of the VCM integrated test microservice computer, and the power SPST card group, the signal SPDT card group and the single-line matrix card group are electrically connected to the disconnect box respectively.

[0013] As a further solution, the bus network node simulates the PXI chassis and is provided with a PXI host card, a first CPCI bus simulation card group and a reflective memory card; wherein, the first CPCI bus simulation card group establishes a bus communication connection with each airborne finished product through a 1394 bus network, and the bus network node simulates the PXI chassis and establishes a memory communication connection with a reflective memory switch through the reflective memory card.

[0014] As a further solution, the bus data acquisition front-end PXI chassis is provided with a third remote control card, a second CPCI bus simulation card group, a 10 Gigabit network card and a reflective memory card; wherein the third remote control card is electrically connected to the fourth remote control card of the bus data acquisition front-end computer, and the second CPCI bus simulation card group establishes a bus communication connection with each airborne finished product through a 1394 bus network; the bus data acquisition front-end PXI chassis establishes a memory communication connection with a reflective memory switch through a reflective memory card, and establishes a network communication connection with a network switch through a 10 Gigabit network card.

[0015] As a further solution, a KVM switch is also provided and is electrically connected to the MFD simulation device, the VMC comprehensive test client computer, the bus network node simulation client computer and the MBT / GMP device respectively; wherein the bus network node simulation client computer is also provided as an automatic dual V test computer, and a PCI bus simulation card is provided in the MBT / GMP device, and bus communication connections are established with each airborne finished product through a 1394 bus network.

[0016] As a further solution, a verification environment cabinet, a verification environment finished product cabinet and a verification environment workbench are also set up, and each device is classified and set; among them,

[0017] The verification environment cabinet is provided with a programmable power supply, a digital multimeter, an oscilloscope, a signal generator, a disconnect box, a VMC integrated test equipment-PXI chassis, a PXI adapter, a KVM display, a VCM integrated test microservice computer, a VMC integrated test client computer, an MBT / GMP device and an automatic dual-V test computer;

[0018] The verification environment finished cabinet is provided with a network switch, a reflective memory switch, development and comprehensive test equipment, a bus data acquisition front-end PXI chassis and a bus repeater; the verification environment workbench is provided with a bus data acquisition client computer, a bus data acquisition front-end computer, an MFD simulation device, a server, a disk array and a reserved equipment position.

[0019] Compared with the prior art, the aircraft management computer software verification environment system provided by the present invention has the following advantages:

[0020] The present invention comprises VMC comprehensive test equipment, bus network node simulation equipment, bus data acquisition and analysis equipment and development and comprehensive test equipment, and constructs Ethernet, reflective memory network and bus network for internal use in the system; wherein Ethernet, reflective memory network and bus network are used internally in the system for data interaction and equipment control, and the operation of each test equipment is integrated and fixed through a verification environment cabinet, a verification environment finished product cabinet and a verification environment workbench, so that the staff can select the test equipment position to be used in the corresponding functional area for operation without sorting out the current environment architecture; the present invention meets the demand for simultaneous aircraft management software verification of multiple airborne finished products, realizes a standard fixed paradigm for aircraft management software verification, and provides a system joint debugging and joint testing verification environment for airborne finished products. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the system architecture of an aircraft management computer software verification environment provided by the present invention;

[0022] Figure 2 A schematic diagram of the network connection of the system provided by the present invention;

[0023] Figure 3 A schematic diagram of a reflective memory network ring topology provided by the present invention;

[0024] Figure 4 A schematic diagram of the relationship between the various layers of the 1394 protocol provided by the present invention;

[0025] Figure 5 A schematic diagram of a basic network architecture provided by the present invention;

[0026] Figure 6 A schematic diagram of the architecture of the three-row 1394 bus provided by the present invention;

[0027] Figure 7 A schematic diagram of a typical asynchronous stream data packet structure provided by the present invention;

[0028] Figure 8 A schematic diagram of the STOF data packet structure provided by the present invention;

[0029] Fig. 9 A schematic diagram of the verification environment cabinet structure provided by the present invention;

[0030] Fig.10 A schematic diagram of the structure of a finished product cabinet for the verification environment provided by the present invention;

[0031] Fig.11 This is a schematic diagram of the verification environment workbench structure provided by the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0033] See also Figure 1 In order to meet the flight management computer software verification requirements of the flight management and flight control integrated navigation system, this embodiment provides an aircraft management computer software verification environment system, which is used to coordinate multiple airborne finished products to simultaneously conduct linkage comprehensive experiments and provide a software verification environment, including VMC comprehensive test equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and comprehensive test equipment, and construct Ethernet, reflective memory network and bus network for internal use of the system; wherein,

[0034] The VMC integrated test equipment includes a programmable power supply, a VCM integrated test microservice computer, a test subsystem PXI device, a disconnect box, a VMC integrated test client computer, an MFD simulation device and an MBT / GMP device; wherein the programmable power supply is electrically connected to each airborne finished product, the VCM integrated test microservice computer is electrically connected to the test subsystem PXI device, and is respectively connected to Ethernet and a reflective memory network; the test subsystem PXI device is also electrically connected to the disconnect box, the disconnect box is respectively electrically connected to each airborne finished product, the VMC integrated test client computer is connected to the Ethernet, the MFD simulation device is connected to the reflective memory network, the MBT / GMP device is connected to the Ethernet, and is communicatively connected to each airborne component through a bus network;

[0035] The bus network node simulation device comprises a bus network node simulation client computer and a bus network node simulation PXI chassis; wherein the bus network node simulation client computer is respectively connected to the Ethernet and the reflective memory network, and the bus network node simulation PXI chassis is connected to each airborne finished product through the bus network, and is respectively connected to the Ethernet and the reflective memory network;

[0036] The bus data acquisition and analysis equipment includes a disk array, a server, a bus data acquisition client computer, a bus data acquisition front-end computer and a bus data acquisition front-end PXI chassis; wherein the disk array, the server, the bus data acquisition client computer, the bus data acquisition front-end computer and the bus data acquisition front-end PXI chassis are respectively connected to the Ethernet, the bus data acquisition front-end PXI chassis is connected to the reflective memory network, and is communicatively connected to each airborne finished product through the bus network; the development and comprehensive test equipment is set up through the VMC debugging computer, and is electrically connected to each airborne finished product respectively; the airborne finished products are also communicatively connected to the bus repeater through the bus network.

[0037] It should be noted that: this embodiment implements two test modes of the aircraft management computer software verification environment, namely, an independent test mode and a multi-subsystem joint debugging; wherein, the independent test mode: the aircraft management computer software verification environment exists independently and can be tested separately. It is connected to the test environment through the 1394 bus and low-frequency cables to complete the collection and analysis of bus data and low-frequency signals to achieve data detection and collection of VMC airborne finished products to support software development and system dynamics dual-V testing. Instructions are sent through reflective memory optical fiber or Ethernet to control hardware resources to achieve automatic dual-V testing. Multi-subsystem joint debugging: The aircraft management computer software verification environment is connected to the subsystem bus network through the 1394 bus derived from the bus network node simulation system, so as to be associated with the subsystem cluster and complete the joint test and debugging of multiple systems.

[0038] Test principle: In the aircraft management computer software verification environment, the VMC integrated test equipment mainly detects the low-frequency electrical signals of the airborne finished product VMC, the bus network node simulation equipment and the bus data acquisition and analysis equipment complete the acquisition and analysis of the bus data and low-frequency signals, the development and integrated test equipment is responsible for the software debugging of the airborne finished product, and the information equipment in each subsystem is equipped with relevant signal function cards to realize the signal acquisition and processing functions.

[0039] like Figure 2 As shown in the figure, each subsystem is connected through the test Ethernet, 1394 bus, reflective memory network and low-frequency cable. The test Ethernet transmits the test control instructions and the feedback status information of the measurement and control equipment to realize the test status management, measurement and control equipment control and file transfer, etc. The 1394 bus network transmits the data packets of the VMC airborne finished products on the aircraft management bus network and the airborne finished product data packets on other subsystems for joint testing; the reflective memory network is mainly used for transmitting the data interacting with the flight simulation system during the pilot in-the-loop test; the low-frequency cable is mainly used for the transmission and conduction of low-frequency electrical signals.

[0040] The following is a detailed description of Ethernet, 1394 bus network and reflective memory network:

[0041] Reflective memory is a technology that provides efficient data transfer between interconnected computers over a local area network, and has been increasingly adopted by designers of hard real-time networks. The concept of a reflective memory real-time local area network is very simple, which is to design a network memory board that enables memory-to-memory communication in a distributed system without software overhead.

[0042] The reflective memory network is mainly composed of reflective memory cards linked by transmission media such as optical fiber. Each computer on the network is inserted with a reflective memory card to form each node, and the memory on the reflective memory card of each node contains a copy of the shared data of other nodes on the reflective memory network.

[0043] The reflective memory card supports high-speed local read operations. When the reflective memory is written locally, the write data is not only stored in the local DDR, but also transmitted to all other nodes through the reflective memory network. The transmission process is transparent to the software, does not require CPU calculations, and has no additional IO overhead.

[0044] The reflective memory network is a ring topology, such as Figure 3 As shown in the figure, the network packet passes through each node in turn and finally returns to the sending node. Each node will resend the received network packet to the next node, unless the node is the original sender of the packet or there is an error in the packet.

[0045] An interrupt packet is a special network packet that includes a command, a sender node number, a receiver node number, and 4 bytes of data. When the receiver receives an interrupt whose target is itself, it stores the sender node number and 4 bytes of data into the corresponding FIFO according to the command.

[0046] Reflective memory cards support four levels of interrupts, each of which can be customized by the user. Interrupts can be initiated by any node, and the target can be either a single node in the network or all nodes in the network. Initiating an interrupt only requires a single write operation to the register. Interrupts can be used to synchronize multiple nodes, or they can follow data as handshake signals.

[0047] There are 4 interrupt FIFOs, corresponding to 4 levels of interrupts, and the depth of each FIFO is 127. If the local interrupt is enabled, the reflective memory card will send an interrupt to the CPU. The software can obtain the relevant information of the interrupt by reading the register and process it.

[0048] The Reflective Memory series products have two independent DMA channels, which are enabled through the configuration register. After the DMA operation is enabled, the Reflective Memory series products will automatically complete the data transfer without CPU intervention. After the data transfer is completed, the Reflective Memory card sends an interrupt to the CPU.

[0049] Network transmission errors can be found through 8B / 10B encoding and CRC encoding contained in network packets. Once the reflective memory card captures a network transmission error, the erroneous network packet will be discarded and an interrupt will be generated.

[0050] Data storage in DDR is protected by ECC, which can correct 1-bit errors in 1 byte and detect 2-bit errors in 1 byte. When an unrecoverable error is detected, the reflective memory card generates an interrupt.

[0051] Redundancy mode can further reduce the bit error rate and improve system reliability. The Reflective Memory series products support two redundancy modes: single-port redundancy and dual-port redundancy.

[0052] The single-port redundant mode can be enabled by setting it in the hardware. In the single-port redundant mode, each network packet to be sent will be sent twice. When the receiving end receives the redundant network packet, it first detects the first network packet. If there is no error, the first network packet is used and the second network packet is discarded; if the first network packet contains an error and the second network packet is correct, the second network packet is used; if both packets contain errors, both packets are discarded. In the single-port redundant mode, the effective data bandwidth is reduced to half of the normal mode.

[0053] The 10 Gigabit NIC is based on Intel's 82599ES Ethernet controller, which integrates multiple GbE links into a 10 Gigabit network to reduce cost and complexity, and multi-core servers with higher bandwidth and network storage to support dynamic data centers.

[0054] The 82599 is targeted at system configurations such as rack-mount or pedestal servers, where it can function as an add-on NIC or LAN on motherboard (LOM). Another system configuration is a blade server, where the 82599 can be used on a LOM or mezzanine card.

[0055] The 1394 bus simulation card is used to simulate the CC, RN and BM node functions in the 1394 bus. It supports bus topology viewing, data recording, error injection and other functions. It can build a 1394 bus network and realize data transmission in the 1394 bus network. The 1394 bus is modified and constrained on the basis of the IEEE-1394 protocol, and the AS5643 protocol is proposed. This protocol realizes the functional requirements of airborne electronic systems such as transmission real-time, reliability and determinism through key technologies such as data transmission, bus synchronization and fault tolerance. The core functions of the 1394 series simulation card are implemented based on FPGA. This design can well complete the analysis of the 1394B bus standard AS5643 protocol. This design has the characteristics of fast FPGA logic function startup, strong protocol processing capability, small size and light weight, which meets the product testing requirements in the laboratory environment.

[0056] The 1394 protocol can be divided into four sub-protocol layers: physical layer, link layer, transaction layer and bus management layer. Each layer defines a set of related services to support bus configuration, bus management and communication between the application and the 1394 protocol layer. The relationship between the sub-protocol layers in a single node is as follows: Figure 4 shown.

[0057] The main functions of each layer are:

[0058] aBus management layer

[0059] The Serial Bus Management layer is used to manage and control the physical layer, link layer, and transaction layer, including power management of bus-connected devices, optimizing timing mechanisms, allocating synchronization channel IDs, speed matching management, topology management, bus optimization based on topology structure, and handling basic error prompts.

[0060] bTransaction Layer

[0061] The transaction layer defines a request-response protocol that supports the CSR (control and status register) architecture. The transaction layer is based on the communication between the requesting node and the responding node, only handles asynchronous data packets, and is implemented by firmware; for isochronous transmission, the upper layer application directly operates the link layer without going through the transaction layer. For data transmission between nodes, the transaction layer provides three operations:

[0062] 1) Read transaction (read): The process of transferring data at a specific address from the responder to the data requester.

[0063] 2) Write transaction: The process of transferring data from a requester to one or more responders.

[0064] 3) Lock transaction (lock): The process in which data goes from the requester to the responder, is then processed at a certain address within the responder, and is returned to the requester.

[0065] c Link Layer

[0066] The link layer provides packet confirmation, addressing, data verification, and data framing in isochronous and asynchronous modes, executes actions on the bus through physical layer services, and provides interface services between the link layer and higher layers to transmit changes in status within the link layer or on the bus to the node controller.

[0067] For asynchronous transactions, the link layer provides an interface for data exchange between the transaction layer and the physical layer, and provides transaction layer-oriented addressing, data verification, frame encapsulation, and decoding and unpacking services for asynchronous data packets. For isochronous transactions, the link layer provides an interface between the bus management layer and the physical layer, and provides services directly to the application layer for isochronous data transmission.

[0068] The main functions of the link layer are:

[0069] 1) Communication with the physical layer;

[0070] 2) Realize the sending and receiving of asynchronous packets and isochronous packets;

[0071] 3) Send confirmation signal for the received asynchronous data packet;

[0072] 4) Loop controller.

[0073] d) Physical layer

[0074] The physical layer mainly provides electrical and mechanical connections between devices and cables, handles data transmission and reception, and ensures that all devices can access the bus. The physical layer provides the conversion of logical signals to physical electrical signals, realizes automatic bus initialization, and interconnects devices in a peer-to-peer manner.

[0075] SAE AS5643 is a set of enhancements to the IEEE-1394b standard. They include the use of asynchronous stream packets, no need for asynchronous or isochronous packets, a fixed frame rate synchronized with the start of the frame packet, the addition of even vertical parity, statically assigned channel numbers, pre-allocated bandwidth, the use of anonymous user messaging, and static assignment of the root node. The root node is also known as the Control Computer (CC). The CC will be the cycle master and bus manager for each data bus.

[0076] Figure 5A basic network architecture is provided, which uses a CC and a loop is created, which is created by connecting port 0 back to port 1 of the CC. Loops are not allowed in IEEE-1394, IEEE-1394b PHYs automatically detect and break loops. The exact location of the loop is unknown until the new architecture tree is configured. After the PHYs break the loop, there will be two branches, one at the left port 0 and the other at port 1. If the cable is damaged, or the PHY layer of the node on the port should now fail, then the bus will automatically reconfigure the failed node on the "end" of one branch, with the other nodes still enabled, this provides the first redundancy; Figure 6 The architecture of a representative three-line 1394 bus is demonstrated. The three technologies are connected across channels, providing another level of redundancy.

[0077] Digital data may be transmitted in any supported format. All data on the bus should be quarter-aligned (32-bit words). All floating point numbers should conform to the IEEE-754 floating point format. Data packets should also be quarter-aligned (32-bit words) and must end with a quarter-aligned (32-bit word).

[0078] All data (bytes and bits) transmitted on a 1394 network has big block order format. In big block order format, bit 0 is the most significant bit (msb) and bit 31 is the least significant bit (lsb).

[0079] Support for S100 (200Mbps), S200 (200Mbps), S400 (400Mbps), S800 (800Mbps), S800 (800mbps), S3200 (3200Mbps) is allowed, and the maximum packet size of the asynchronous streaming transmission bit rate should be consistent with that specified in the IEEE-1394 specification.

[0080] Asynchronous stream packets are isochronous data packets that are usually sent at asynchronous time intervals. Figure 7 Figure 1 shows a typical asynchronous streaming packet seen on the bus. The packets defined in this specification include the 1394 header inserted by hardware, the anonymous user message header inserted by hardware, the payload data area, the packet carriage, and the 1394 cyclic redundancy check.

[0081] The CC node is the root node, cycle master, and acts as the bus manager for each data bus. If isochronous transactions are used, cycle start packets can be sent over the CC; however, they are not necessarily synchronized with the STOF of the packet. For this reason, it is not acceptable to base transmit, receive, or data pump offload on many cycle start packets under STOF packet traces.

[0082] The CC shall transmit the start of frame packet (STOF) at a fixed frame rate (e.g. 10 ms, 12.5 ms, etc.). The STOF packet (e.g. Figure 8 The data packet should be an asynchronous stream data packet transmitted on channel 31, and there is no header or STOF packet in a packet.

[0083] The Test Mode Memory Read command provides the ability to continuously read selected memory addresses. The Memory Read Address specifies the address of the memory to be read. Num_Quads specifies how many 32-bit quadlets in each address to read and should be set to 1. Num_set specifies how many different addresses are requested in the command packet. The Read Response packet should have a pass-through type response and respond to the Num_Quads and num_set fields present in the Read command. In the Memory Read Address field, the data to be read from the memory for each corresponding address should be entered.

[0084] The Test Mode Memory Read command provides the ability to continuously read selected memory addresses. The Memory Read Address specifies the address of the memory to be read. Num_Quads specifies how many 32-bit quadlets in each address to read and should be set to 1. Num_set specifies how many different addresses are requested in the command packet. The Read Response packet should have a pass-through type response and respond to the Num_Quads and num_set fields present in the Read command. In the Memory Read Address field, the data to be read from the memory for each corresponding address should be entered.

[0085] The Test Mode Memory Write command provides the ability to write to selected memory locations in the RAM memory. The Transfer Type should be set to Memory Write, the Num_Quads field specifies how many sequential 32-bit writes are performed in each Memory Write Start Address, and num_set specifies how many Memory Write Start Addresses are required.

[0086] The 5A power supply SPST card is a 24-channel single-pole single-throw power switch module, which collects the discontinuous signals of the 5A power supply and realizes the output of the switching quantity through the internal relay; the 1A signal SPDT card is a 66-channel single-pole single-throw data switch module, which collects the discontinuous signals of the 1A signal and realizes the output of the switching quantity through the internal relay; the 1A signal SPST card is a 100-channel single-pole single-throw data switch module, which collects the discontinuous signals of the 1A power supply and realizes the output of the switching quantity through the internal relay.

[0087] When a CC branch needs to support multiple 1394 buses and each CC branch needs to support continuous or simultaneous operation of the buses, it is important to ensure that each 1394 interface operates in a fully autonomous manner. To support autonomous operation, it is recommended that each 1394 bus (node) store local memory to store transmit and receive descriptors and packet payload data (such as Figure 5 ), this local memory ensures that the 1394 Link Layer Controller (LLC) transmit and receive buffers are not overwritten and data is not received because the LLC's buffers are full. Local memory can be used to hold static or dynamic transmit descriptor chains that can automatically pull message payloads from local memory and transmit messages on the 1394 bus. The LLC can also direct incoming message contents from the receive buffer directly into local memory where the host control or processing elements of the CC can access the data. The use of dedicated local memory per bus / node eliminates the need for multiple 1394 interfaces to gain access to a single bus or memory device (such as Figure 6 as shown), and eliminates stalling of host control or processing elements for handshaking with the 1394 interfaces to store / retrieve data from system memory.

[0088] The data signal connection of this solution uses PXI bus communication. PXI is a modular instrument platform tailored for industrial data acquisition and automation applications. Its specification is an extension of the CPCI specification. PXIe is the addition of PCIe to the PXI specification. It has the same relationship as PXI and PCI, and includes various extended features required in the test and measurement field. PCIe can establish multiple channels at the same time to increase the data transmission rate to achieve serial bus connection. Each connection only carries data between devices at both ends of the line. The data connection rate depends on the chassis, slots and modules. All signal flows must enter and exit the root complex. The actual rate also depends on the PCIe interface and controller processing capabilities.

[0089] In addition, in order to realize the integrated operation of each test equipment, a standard fixed paradigm is provided so that the staff can operate at the location of the test equipment to be used in the corresponding functional area without sorting out the current environment architecture. Among them, the functional area includes the verification environment cabinet, the verification environment finished cabinet and the verification environment workbench, and each device is classified and set;

[0090] like Fig. 9 As shown, the verification environment cabinet is provided with a programmable power supply, a digital multimeter, an oscilloscope, a signal generator, a disconnect box, a VMC integrated test equipment-PXI chassis, a PXI adapter, a KVM display, a VCM integrated test microservice computer, a VMC integrated test client computer, an MBT / GMP device and an automatic dual V test computer;

[0091] like Fig.10 As shown, the verification environment finished cabinet is provided with a network switch, a reflective memory switch, development and comprehensive test equipment, a bus data acquisition front-end PXI chassis and a bus repeater; Fig.11 As shown, the verification environment workbench is provided with a bus data acquisition client computer, a bus data acquisition front-end computer, an MFD simulation device, a server, a disk array and a reserved device position.

[0092] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. An aircraft management computer software verification environment system, used to coordinate multiple airborne finished products to simultaneously conduct linkage comprehensive experiments and provide a software verification environment, characterized in that: It includes VMC comprehensive test equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and comprehensive test equipment, and builds Ethernet, reflective memory network and bus network for internal use in the system; among them, The VMC integrated test equipment includes a programmable power supply, a VCM integrated test microservice computer, a test subsystem PXI device, a disconnect box, a VMC integrated test client computer, an MFD simulation device and an MBT / GMP device; wherein the programmable power supply is electrically connected to each airborne finished product, the VCM integrated test microservice computer is electrically connected to the test subsystem PXI device, and is respectively connected to Ethernet and a reflective memory network; the test subsystem PXI device is also electrically connected to the disconnect box, the disconnect box is respectively electrically connected to each airborne finished product, the VMC integrated test client computer is connected to the Ethernet, the MFD simulation device is connected to the reflective memory network, the MBT / GMP device is connected to the Ethernet, and is communicatively connected to each airborne component through a bus network; The bus network node simulation device comprises a bus network node simulation client computer and a bus network node simulation PXI chassis; wherein the bus network node simulation client computer is respectively connected to the Ethernet and the reflective memory network, and the bus network node simulation PXI chassis is connected to each airborne finished product through the bus network, and is respectively connected to the Ethernet and the reflective memory network; The bus data acquisition and analysis equipment includes a disk array, a server, a bus data acquisition client computer, a bus data acquisition front-end computer and a bus data acquisition front-end PXI chassis; wherein the disk array, the server, the bus data acquisition client computer, the bus data acquisition front-end computer and the bus data acquisition front-end PXI chassis are respectively connected to the Ethernet, the bus data acquisition front-end PXI chassis is connected to the reflective memory network, and is communicatively connected to each airborne finished product through the bus network; the development and comprehensive test equipment is set up through the VMC debugging computer, and is electrically connected to each airborne finished product respectively; the airborne finished products are also communicatively connected to the bus repeater through the bus network.

2. The aircraft management computer software verification environment system according to claim 1, characterized in that: The bus network is a 1394 bus network set based on the 1394 protocol and enhanced with the AS5643 protocol group, connecting various devices to realize device-to-device bus communication connection; the reflective memory network connects the reflective memory cards of various devices through a reflective memory switch, and realizes memory-to-memory memory communication connection between various devices; The Ethernet is connected to the 10 Gigabit network cards of each device through a network switch, and implements device-to-device network communication connection between the connected devices.

3. The aircraft management computer software verification environment system according to claim 1, characterized in that: Testing instruments and equipment are also provided; wherein, the testing instruments and equipment include a digital multimeter, an oscilloscope and a signal generator, and the disconnect box is also electrically connected to the digital multimeter, the oscilloscope and the signal generator respectively.

4. The aircraft management computer software verification environment system according to claim 1, characterized in that: The VMC integrated test equipment includes a VMC integrated test equipment-PXI chassis, a cascade card, a first remote control card, a power SPST card group, a signal SPDT card group and a single-line matrix card group; wherein the first remote control card is electrically connected to the second remote control card of the VCM integrated test microservice computer, and the power SPST card group, the signal SPDT card group and the single-line matrix card group are electrically connected to the disconnect box respectively.

5. The aircraft management computer software verification environment system according to claim 2, characterized in that: The bus network node simulates the PXI chassis and is provided with a PXI host card, a first CPCI bus simulation card group and a reflective memory card; wherein the first CPCI bus simulation card group respectively establishes a bus communication connection with each airborne finished product through a 1394 bus network, and the bus network node simulates the PXI chassis and establishes a memory communication connection with a reflective memory switch through the reflective memory card.

6. The aircraft management computer software verification environment system according to claim 2, characterized in that: The bus data acquisition front-end PXI chassis is provided with a third remote control card, a second CPCI bus simulation card group, a 10 Gigabit network card and a reflective memory card; wherein the third remote control card is electrically connected to a fourth remote control card of the bus data acquisition front-end computer, and the second CPCI bus simulation card group respectively establishes a bus communication connection with each airborne finished product through a 1394 bus network; the bus data acquisition front-end PXI chassis establishes a memory communication connection with a reflective memory switch through a reflective memory card, and establishes a network communication connection with a network switch through a 10 Gigabit network card.

7. The aircraft management computer software verification environment system according to claim 2, characterized in that: A KVM switch is also provided and is electrically connected to the MFD simulation device, the VMC comprehensive test client computer, the bus network node simulation client computer and the MBT / GMP device respectively; wherein the bus network node simulation client computer is also provided as an automatic dual V test computer, and a PCI bus simulation card is provided in the MBT / GMP device, and bus communication connections are established with each airborne finished product through a 1394 bus network.

8. An aircraft management computer software verification environment system according to any one of claims 1 to 7, characterized in that: There are also verification environment cabinets, verification environment finished product cabinets and verification environment workbenches, and each device is classified and set up; among them, The verification environment cabinet is provided with a programmable power supply, a digital multimeter, an oscilloscope, a signal generator, a disconnect box, a VMC integrated test equipment-PXI chassis, a PXI adapter, a KVM display, a VCM integrated test microservice computer, a VMC integrated test client computer, an MBT / GMP device and an automatic dual-V test computer; The verification environment finished cabinet is provided with a network switch, a reflective memory switch, development and comprehensive test equipment, a bus data acquisition front-end PXI chassis and a bus repeater; the verification environment workbench is provided with a bus data acquisition client computer, a bus data acquisition front-end computer, an MFD simulation device, a server, a disk array and a reserved equipment position.

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