Simulation test method, system and equipment and storage medium

Abstract

The embodiment of the invention provides a simulation test method, system and device and a storage medium. The simulation test method comprises the steps that a simulation test tool on bus simulation development software is obtained; the simulation test tool comprises a test message to be sent, the bus simulation development software is in communication connection with a tested controller through a board card, and the board card comprises a first processor core and a second processor core; the simulation test tool is sent to the first processor core; the first processor core is used for calling the second processor core according to the simulation test tool, and the second processor core is used for sending the test message in the simulation test tool to the tested controller; receiving a response message returned by the tested controller in response to the test message; and taking the test message and the response message as simulation test data and displaying the simulation test data. According to the method, the real-time performance of the simulation test can be ensured, and the simulation test efficiency and effectiveness are improved.

Description

Technical Field

[0001] The present application relates to the field of vehicle testing technology, and in particular to a simulation testing method and system, an electronic device and a storage medium. Background Art

[0002] The vehicle bus simulation test system is a set of tools specifically used for the development, testing and verification of automotive electronic systems. It can simulate the communication and behavior between the electronic control units (ECUs) inside the vehicle, monitor the bus data such as CAN, LIN, FlexRay in real time, and ensure the stability and reliability of vehicle communication. Through virtual simulation technology, it simulates various driving scenarios and fault conditions to verify the performance of the vehicle control system.

[0003] However, in the related art, vehicle bus simulation test systems are usually developed using C language or C++ language, which places too high demands on the tester's ability to write code. At the same time, the system software or test scripts do not fully consider the real-time requirements of the test, and the real-time performance of the test cannot be ensured when controlling the hardware. This may cause inaccurate or delayed simulation results, affecting the efficiency and effectiveness of the test.

[0004] Therefore, how to complete vehicle bus simulation testing in real time and efficiently has become an urgent problem to be solved. Summary of the invention

[0005] The embodiment of the present application provides a simulation test method to solve the problem in the prior art that the real-time performance of the vehicle bus simulation test cannot be ensured, resulting in reduced test efficiency and effectiveness.

[0006] Correspondingly, an embodiment of the present application also provides a simulation test system, an electronic device and a storage medium to ensure the implementation and application of the above method.

[0007] In order to solve the above problems, the present application discloses a simulation test method, which includes:

[0008] Obtain a simulation test tool on the bus simulation development software; the simulation test tool includes a test message to be sent, the bus simulation development software is connected to the controller under test through a board, and the board includes a first processor core and a second processor core;

[0009] Sending a simulation test tool to a first processor core; the first processor core is used to call a second processor core according to the simulation test tool, and the second processor core is used to send a test message in the simulation test tool to the controller under test;

[0010] Receive a response message returned by the controller under test in response to the test message;

[0011] The test message and response message are used as simulation test data and displayed.

[0012] Optionally, after sending the simulation test tool to the first processor core, the method further includes:

[0013] The first processor core is used for acquiring a test message by running a simulation test tool.

[0014] Optionally, after sending the simulation test tool to the first processor core, the method further includes:

[0015] Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of a test message;

[0016] Synchronizing the first data to a second signal database of the first processor core to obtain corresponding second data;

[0017] The first processor core is controlled to run a simulation test tool, and a test message is obtained according to the second data analysis.

[0018] Optionally, after sending the simulation test tool to the first processor core, the method further includes:

[0019] Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of a test message;

[0020] A test message sending period is defined in the first signal database; the sending period is used to control the frequency of the first processor core calling the second processor core;

[0021] Synchronize the first data and the sending cycle to a third signal database of the first processor core to obtain third data;

[0022] The first processor core is controlled to run a simulation test tool, and a test message is obtained according to the third data analysis.

[0023] Optionally, the simulation test method further includes:

[0024] Controlling the first processor core to generate a control command for calling the second processor core according to the simulation test tool;

[0025] After controlling the second processor core to receive the control command and test message sent by the first processor core, it responds to the control command and sends the test message to the controller under test through the programmable logic device on the board; the programmable logic device is used to add a timestamp to the test message when sending the test message.

[0026] Optionally, the test message and the response message are used as simulation test data and displayed, and also include:

[0027] Directly display test messages and response messages;

[0028] Or, according to the message structure and signal name stored in the first signal database, parse the test message and the response message to generate parsing data;

[0029] Display parsed data.

[0030] Optionally, the simulation test method further includes:

[0031] receiving a timing request from a first processor core;

[0032] In the case of a single board, respond to the timing request and send the clock to the board;

[0033] When there are multiple boards, one of them is selected as the master node board, and the boards other than the master node board are used as slave node boards. The clock is sent to the master node board in response to the timing request; the master node board is used to synchronize the clock to the slave node board.

[0034] The present application also discloses a simulation test system, which includes:

[0035] A simulation test tool acquisition module is used to acquire a simulation test tool on a bus simulation development software; the simulation test tool includes a test message to be sent, the bus simulation development software is connected to the controller under test through a board, and the board includes a first processor core and a second processor core;

[0036] A sending module, used to send the simulation test tool to the first processor core; the first processor core is used to call the second processor core according to the simulation test tool, and the second processor core is used to send the test message in the simulation test tool to the controller under test;

[0037] A receiving module, used for receiving a response message returned by the controller under test in response to the test message;

[0038] The display module is used to display the test message and the response message as simulation test data.

[0039] An embodiment of the present application also discloses an electronic device, including: a processor; and a memory, on which executable code is stored. When the executable code is executed, the processor executes one or more simulation test methods in the embodiments of the present application.

[0040] The embodiment of the present application also discloses a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, one or more simulation test methods in the embodiment of the present application are implemented.

[0041] Compared with the prior art, the embodiments of the present application have the following advantages:

[0042] In an embodiment of the present application, a simulation test tool on a bus simulation development software is obtained, the simulation test tool includes a test message to be sent, the bus simulation development software is connected to the controller under test through a board, and the board includes a first processor core and a second processor core. The simulation test tool is sent to the first processor core, and the first processor core is used to call the second processor core according to the simulation test tool to send the test message in the simulation test tool to the controller under test. The hardware control command can be directly called to ensure the real-time performance of the simulation test process and improve the test efficiency. The response message returned by the controller under test in response to the test message is received, and the test message and the response message are used as simulation test data and displayed, so that the simulation test data of the controller can be obtained accurately and efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 It is a schematic diagram of the logic architecture of a simulation test system embodiment of the present application;

[0045] Figure 2 It is a technical architecture diagram of a simulation test system embodiment of the present application;

[0046] Figure 3 is a flowchart of the steps of a simulation test method embodiment of the present application;

[0047] Figure 4 It is a structural block diagram of a simulation test system embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0049] In order to reduce the difficulty of code writing for testers, and fully consider the real-time requirements of simulation testing to ensure the effectiveness and efficiency of testing. A bus simulation development platform can be developed, which includes the development of bus simulation development software, and the design and development of boards. Bus simulation development software mainly involves C#, Python, unstructured database, structured database, file storage, signal definition and analysis (signal database), Ethernet (TCP) transmission, USB3.1Gen2 and above, PCIe3.0 and above. The design and development of boards include chip selection, communication interface selection (Ethernet / USB / PCIe), Linux system, real-time operating system, C++, Python, shared memory solution (inter-core communication), driver development, FPGA (Field-Programmable Gate Array, programmable logic device) programming, TSN (Time-Sensitive Networking, time-sensitive network) time synchronization, etc.

[0050] Reference Figure 1 , is a schematic diagram of the logical architecture of a simulation test system embodiment of the present application.

[0051] The application provides a kind of simulation test system logical architecture which may include bus simulation development software, HIL bench (Hardware-in-the-Loop Simulation, hardware in the loop simulation) and controller. The bus simulation development software may include configuration and editing modules and execution and display modules. The configuration and editing module may include a device configuration submodule and an auxiliary tool submodule, and the execution and display module may include a simulation model submodule, a test platform submodule, a data transmission submodule, a diagnosis submodule, a system interface submodule, and a data analysis submodule. Various functional submodules on the execution and display module may be configured and edited by the configuration and editing module. The HIL bench may include a board integration module and a power supply and control module. The board integration module may include a digital IO acquisition back injection fault injection submodule, an analog IO acquisition back injection fault injection submodule, a CAN (FD) acquisition back injection fault injection submodule, a LIN acquisition back injection fault injection submodule, an Ethernet acquisition back injection fault injection submodule and a repeater. The power supply and control module may include an external power supply and a program-controlled power supply to provide power for board integration. The execution and display modules in the bus simulation development software and the board integration in the HIL bench can transfer data to each other. The controller can contain a variety of communication network interfaces, including CAN, LIN, Ethernet, DIDO and AIAO. The controller can transfer data to and from the board integration in the HIL bench.

[0052] Reference Figure 2 , is a technical architecture diagram of a simulation test system embodiment of the present application.

[0053] A simulation test system technical architecture provided by the present application may include bus simulation development software and HIL bench. Among them, the bus simulation development software may include simulation and functional logic control module, data processing module, device configuration module, signal database, Python library and data storage module. The simulation and functional logic control module may include simulation model submodule, test platform submodule, diagnosis submodule and data transmission submodule. The data processing module may include data analysis submodule and data export submodule. The device configuration module may include device configuration submodule and system interface. Among them, the system interface may be an editable system interface, through which an external program or system can access or control the simulation node or controller in the bus simulation development platform. The signal database may include signal data corresponding to multiple communication protocols, and exemplary ones may be CAN protocol, LIN protocol, Ethernet protocol, DIDO private protocol and AIAO private protocol. The Python library can be divided into CAN library, LIN library, Ethernet library, DIDO library and AIAO library according to the corresponding communication protocols. The data storage module may include structured database, unstructured database and file storage system. The HIL bench may include multiple boards. The board may include an A core, an R core, a shared memory, an FPGA, and a PIN interface. The A core may include an acquisition and re-injection fault injection configuration module, an acquisition and re-injection fault injection script module, a time timing module, a Python library, an inter-core communication module, a data storage module, a signal database, and a driver module. The R core may include a CAN transceiver module, a LIN transceiver module, an Ethernet transceiver module, a DIDO transceiver module, an AIAO transceiver module, and a driver module. The FPGA may include a timestamp module, a clock synchronization module, a message transceiver module, and an inter-core communication module. The PIN interface may include CAN, LIN, and Ethernet PIN interfaces. Moreover, the simulation and functional logic control module and the data storage module in the bus simulation development software are connected to the board in the HIL bench through Ethernet / USB / PCIe communication.

[0054] Reference Figure 3 , is a flowchart of a simulation test method embodiment of the present application, comprising the following steps:

[0055] Step 301, obtaining a simulation test tool on bus simulation development software;

[0056] The simulation test tool includes a test message to be sent, and the bus simulation development software is connected to the controller under test through a board card, and the board card includes a first processor core and a second processor core.

[0057] The bus simulation development software is based on Windows system and developed in C#. It can be used to provide software tools for configuration and writing of simulation and functional logic control processes, data processing, and automotive general protocol testing. The simulation test tool includes simulation nodes and test scripts. A simulation node is a virtual entity that can simulate the behavior of actual devices by receiving input, processing data, and generating output. In vehicle bus simulation testing, a simulation node can be a virtual node that simulates the behavior of a real ECU and can simulate the communication process in an actual vehicle. A test script is an automated test software script that can write and execute test cases. In vehicle bus simulation testing, it can simulate and verify the communication and data exchange between various components of the vehicle. The test message is included in the test script of the simulation test tool, which can simulate the message data received and sent in actual vehicle communication, helping to detect and diagnose potential problems in the vehicle system. A board can be a hardware device used for acquisition, back injection, fault injection, and power support for the controller. It can also provide a certain number of circuit channels to communicate with the controller. If the circuit channels provided by a board do not meet the needs of the controller under test, multiple boards can be used in combination. The first processor core can be the A core located on the board. The A core uses an ARM architecture SoC chip and the system is Linux. The software in the A core is developed based on C++ and is mainly used for communication and functional interaction with the bus simulation development software on the Windows side. The second processor core can be the R core located on the board. The R core uses an ARM architecture SoC chip and the system is FreeRTOS. The software in the R core is developed based on C and is mainly used for communication and functional interaction with the A core and FPGA. The communication and functional interaction between the first processor core and the second processor core are realized through the inter-core communication module. For example, refer to Figure 2 , the inter-core communication between the first processor core and the second processor core can be realized by using the openamp framework and adopting a shared memory manner.

[0058] Step 302: Send the simulation test tool to the first processor core;

[0059] The first processor core is used to call the second processor core according to the simulation test tool, and the second processor core is used to send the test message in the simulation test tool to the controller under test. The controller under test can be an electronic control unit for managing and adjusting the functions of various parts of the vehicle.

[0060] Step 303: receiving a response message returned by the controller under test in response to the test message;

[0061] The response message is a message returned by the controller under test after receiving the test message and performing corresponding processing according to the test message. The response message may include information confirming successful reception of the test message, test result information or other relevant information.

[0062] Step 304: Use the test message and the response message as simulation test data and display them.

[0063] In order to realize real-time and efficient vehicle bus simulation test, the simulation test tool on the bus simulation development software can be obtained first, including simulation nodes and test scripts. Exemplarily, the simulation nodes and test scripts can be written in Python language. Using Python language as the simulation test code editing language can reduce the ability requirements for testers to write simulation nodes, test scenarios, and test script codes, and improve the writing efficiency of simulation test tools. The test script contains test messages to be sent. The bus simulation development software is connected to the board in communication, and the board is connected to the controller under test in communication. The board contains a first processor core and a second processor core, that is, an A core and an R core. Therefore, the bus simulation development software can send the simulation test tool to the A core on the board through a high-bandwidth interface. After receiving the simulation test tool, the A core directly calls the R core according to the simulation nodes and test scripts therein to send the test message in the test script to the controller under test, thereby ensuring the real-time performance of the simulation test. Among them, the high-bandwidth interface can be a high-bandwidth Ethernet, USB or PCIe interface, such as an Ethernet interface of 1Gb / s interface and above, a USB interface of USB3.1Gen2 and above, or a PCIe interface of PCIe3.0 and above. After receiving the test message, the controller under test responds to the test message and returns a corresponding response message. Receive the response message returned by the controller under test in response to the test message, and then use the test message and the response message as simulation test data and display them. Through the above steps, a convenient editing tool can be provided for testers to facilitate users to edit simulation nodes and test scenarios, ensure the real-time nature of the simulation test process, improve test efficiency, and accurately and efficiently obtain simulation test data for the controller.

[0064] For example, Figure 2 As shown, a simulation test method provided by the present application can be used to perform HiL hardware-in-the-loop testing on a controller. The bus simulation development software provides the ability to create simulation nodes and test steps, and simulates itself as one or more simulation nodes, or even a simulation controller, by calling various boards in the HIL test bench, and then communicates with the controller under test in real time, and finally determines whether the communication data between each other is correct through the verification conditions established in the bus simulation development software.

[0065] Optionally, in an embodiment of the present application, after sending the simulation test tool to the first processor core, the method further includes:

[0066] Control the first processor core to obtain the test message by running the simulation test tool.

[0067] For example, the simulation test tool written in Python can be sent to the first processor core, that is, the A core on the board. The A core software directly runs the simulation nodes and test scripts in the simulation test tool, and obtains the test messages in the test script according to the Python functions therein. To support the use of Python as a language for writing simulation nodes and test scripts, relevant Python libraries can be provided in the bus simulation development software and the board A core software. Figure 2 In the bus simulation development software, the code in the Python library can be set through the simulator function logic control module, and the names of the functions, interfaces, etc. of the Python library are provided. The actual content of the function is empty, which can be used to find and pass the static code check when the user writes the simulation node and test script. The Python library of the A core of the board card can provide the contents of all function interfaces corresponding to the Python library in the bus simulation development software. When the A core on the board card receives the simulation nodes and test scripts written in Python sent by the bus simulation development software, these Python scripts can be run normally. Among them, the Python library can provide the underlying functions for simulation and functional logic control, and the Python code calls the hardware control function in the A core to realize the acquisition and transmission of CAN, LIN, Ethernet, DIDO, AIAO, etc.

[0068] Optionally, in an embodiment of the present application, after sending the simulation test tool to the first processor core, the method further includes:

[0069] Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message;

[0070] The first signal database may include files that define message structures and signal names, etc. The corresponding files for CAN (Controller Area Network) network may be DBC (Database for CAN) files, the corresponding files for LIN bus may be LDF (LIN Description File) files, the corresponding files for Ethernet may be ARXML files, and DIDO or AIAO may be JSON files.

[0071] Synchronizing the first data to a second signal database of the first processor core to obtain corresponding second data;

[0072] The first processor core is controlled to run the simulation test tool, and the test message is obtained according to the second data analysis.

[0073] In some embodiments of the present application, reference Figure 2 , a variety of message structures and signal names can be defined in the first signal database through the simulation machine function logic control module on the bus simulation development software, and the predefined messages and signals in the first signal database can be used when writing the simulation nodes or test scripts in the simulation test tool. The bus simulation development software can synchronize the contents of the first signal database to the second signal database in the first processor core through Ethernet, USB or PCIe protocol. The contents of the first signal database, that is, the predefined message structure and signal name, are stored in the second signal database as the second data. The first processor core runs the simulation test tool, and uses the Python function in the simulation node and the test script to parse the signal according to the message structure in the second data to obtain the test message to be sent.

[0074] Optionally, in an embodiment of the present application, after sending the simulation test tool to the first processor core, the method further includes:

[0075] Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message;

[0076] A sending period of the test message is defined in the first signal database; the sending period is used to control the frequency of the first processor core calling the second processor core;

[0077] Synchronize the first data and the sending cycle to a third signal database of the first processor core to obtain third data;

[0078] The first processor core is controlled to run the simulation test tool, and the test message is obtained according to the third data analysis.

[0079] In some embodiments of the present application, a variety of message structures and signal names can be defined in the first signal database on the bus simulation development software, and the predefined messages and signals in the first signal database are used when writing the simulation node or test script in the simulation test tool. The sending cycle of the test message can also be defined in the first signal database. The bus simulation development software can synchronize the content of the first signal database to the second signal database in the first processor core through Ethernet, USB or PCIe protocol. The content of the first signal database, that is, the predefined message structure and signal name and the sending cycle of the test signal, is stored in the third signal database as the third data. The first processor core is controlled to run the simulation test tool, and the Python function in the simulation node and the test script is used to parse the signal according to the message structure in the second data to obtain the test message to be sent. In addition, when sending the test message, the second processor core can be called to send according to the test signal sending cycle in the third data.

[0080] Optionally, in an embodiment of the present application, the method further includes:

[0081] Controlling the first processor core to generate a control command for calling the second processor core according to the simulation test tool;

[0082] After controlling the second processor core to receive the control command and test message sent by the first processor core, respond to the control command to send the test message to the controller under test through the programmable logic device on the board; the programmable logic device is used to add a timestamp to the test message when sending the test message.

[0083] The programmable logic device (Field-Programmable Gate Array, FPGA) is respectively connected to the second processor core and the controller under test for completing the final test message transmission and the reception of the response message returned by the controller under test. Figure 2, the first processor core contains a collection back-injection fault injection configuration module and a collection back-injection fault injection script module. After receiving the simulation test tool sent by the bus simulation development software, the collection back-injection fault injection script directly executes the Python code in the simulation node and the test script. The function in the Python code directly generates a control command to call the second processor core, and controls the second processor core to send the test message parsed by the first processor core. The second processor core responds to the control command and test message sent by the first processor core, and calls the FPGA to send the test message to the controller under test. When sending the test message, the FPGA will add a timestamp to the sent message, and accordingly, when receiving the response message returned by the controller under test, it will also add a timestamp to the received message. By generating control commands that can directly call the hardware, the real-time performance of the simulation test process can be guaranteed and the test efficiency can be improved.

[0084] Because the implementation systems corresponding to the first processor core, the second processor core and the FPGA are different. Exemplarily, after receiving the message sending configuration information, that is, the test message whose information format is a code script, the acquisition and injection fault injection configuration module on the first processor core can first convert the message sending configuration information of the test message into configuration information, and then send the test message converted into configuration information to the second processor core. The configuration information is the driver configuration that can be recognized by the second processor core. There are multiple transceiver modules on the second processor, including CAN, LIN, Ethernet, DIDO, and AIAO transceivers. Correspondingly, the controller under test can also be a controller that uses CAN, LIN, Ethernet, DIDO, and AIAO as communication protocols. After the second processor core receives the test message and control command in the transceiver module, it can convert the configuration information corresponding to the test message and the control command into configuration and then send it to the FPGA. Configuration refers to the message code recognizable by the FPGA. The communication and functional interaction between the second processor core and the FPGA are realized through inter-core communication. Exemplarily, refer to Figure 2 , the inter-core communication between the second processor core and the FPGA can be realized by using DMA (Direct Memory Access) and FIFO (First In, First Out) data structure. Similarly, after the signal database on the first processor core receives the synchronization information of the first signal database of the bus simulation development software, it can also convert the corresponding message sending configuration information into configuration information and send it to the second processor core.

[0085] Optionally, in an embodiment of the present application, the method further includes:

[0086] Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message;

[0087] Generate message sending configuration information by configuring the test message to be sent;

[0088] Sending the message sending configuration information to the first processor core;

[0089] Synchronizing the first data and the sending cycle to a fourth signal database of the first processor core to obtain fourth data;

[0090] Controlling the first processor core to send configuration information and the fourth data according to the message, and parsing to obtain the test message;

[0091] Controlling the first processor core to generate a control command to call the second processor core;

[0092] After receiving the control command and test message sent by the first processor core, the second processor core is controlled to respond to the control command and send the test message to the controller under test through the programmable logic device on the board; the programmable logic device is used to add a timestamp to the test message when sending the test message.

[0093] In some embodiments of the present application, the message structure and signal name of the test message can be defined in the first signal database on the bus simulation development software, and then the message in the first signal database is configured to be sent in the bus simulation development software to obtain the message sending configuration information. Exemplarily, the first signal database in the bus simulation development software can be selected by the user, and the user can select the message in the library as the test message to be sent by clicking the corresponding button. The bus simulation development software sends the message sending configuration information to the first processor core through Ethernet, USB or PCIe protocol, and synchronizes the content of the first signal database to the fourth signal database in the first processor core through Ethernet, USB or PCIe protocol to obtain the corresponding fourth data. The first processor core parses and obtains the test message according to the message sending configuration information and the fourth signal database, and then generates a control command to call the second processor core, and controls the second processor core to send the test message to the controller under test through the programmable logic device on the board. When sending the test message, the programmable logic device will add a timestamp to the sent message, and accordingly, when receiving the response message returned by the controller under test, it will also add a timestamp to the received message.

[0094] Optionally, in an embodiment of the present application, the method further includes:

[0095] Generate test message sending configuration information by configuring the test message to be sent;

[0096] Generate diagnostic message sending configuration information by configuring the diagnostic message to be sent;

[0097] Sending the test message sending configuration information and the diagnostic message sending configuration information to the first processor core;

[0098] Controlling the first processor core to parse and obtain the corresponding test message or diagnostic message according to the test message sending configuration information or the diagnostic message sending configuration information;

[0099] Controlling the first processor core to generate a control command to call the second processor core;

[0100] After receiving the test message or diagnostic message sent by the first processor core, the second processor core is controlled to respond to the control command to send the test message or diagnostic message to the controller under test through the programmable logic device on the board; the programmable logic device is used to add a timestamp to the test message or diagnostic message when sending the test message.

[0101] In some embodiments of the present application, the message content of the test message or the diagnostic message can be configured in the bus simulation development software to generate the test message sending configuration information or the diagnostic message sending configuration information. Figure 2 , a local information database can be set in the bus simulation development software for users to select messages according to test requirements. Users can select messages in the library as test messages to be sent by clicking the corresponding button. The local information database can be generated by the bus simulation development software according to the various protocols corresponding to the files in the first signal database to obtain message data, and then storing the parsed message data in the structured database of the local data storage module. The local information database can be used by users to write simulation nodes, write test scripts, and analyze data. The device configuration module on the bus simulation development software can ensure the correct transmission of data. The bus simulation development software can send test message sending configuration information or diagnostic message sending configuration information to the first processor core through Ethernet, USB or PCIe protocol. The first processor core parses the test message or diagnostic message according to the test message sending configuration information or the diagnostic message sending configuration information, and then generates a control command to call the second processor core, and controls the second processor core to send the test message or diagnostic message to the controller under test through the programmable logic device on the board. When the programmable logic device sends a test message or a diagnostic message, it will add a timestamp to the sent message. Correspondingly, when receiving a response message returned by the controller under test, it will also add a timestamp to the received message.

[0102] Optionally, in an embodiment of the present application, the taking the test message and the response message as simulation test data and displaying them further includes:

[0103] Directly display the test message and the response message;

[0104] or, according to the message structure and signal name stored in the first signal database, parsing the test message and the response message to generate parsing data;

[0105] The parsed data is displayed.

[0106] In some embodiments of the present application, reference Figure 2 After the communication between the trigger board and the controller under test is triggered, the messages sent and received by the board during this period will be added with corresponding sight stamps when the FPGA sends and receives the messages, and then the messages are transmitted to the first processor core through the second processor core and stored in the data storage of the first processor core. Among them, the data storage of the first processor core can be a time series database that maps files into memory through mmap (memory map). The use of mmap can improve the access speed and processing efficiency of data. The first processor core can send the message content in the data storage to the bus simulation development software in real time, and the bus simulation development software stores these sent and received messages in a local unstructured database. Among them, the local unstructured database can use Mangodb, which is a document-oriented, distributed database that can be used to store and manage a large amount of structured and unstructured data. When the simulation test data reading instruction is obtained, the data processing module in the bus simulation development software can read the messages stored in the local unstructured database in real time, and then display these messages to the user. When the simulation test data export instruction is obtained, the data processing module in the bus simulation development software can export the message the user wants from the unstructured database according to the data type and duration contained in the instruction. When the simulation test data analysis instruction is obtained, the data processing module in the bus simulation development software parses the message stored in the local unstructured database according to the structure definition and signal name definition of the message in the first information database, and displays the parsed data information to the user. In addition, the tester can also view, filter, count and perform other operations on all messages stored in the local unstructured database through data analysis according to actual needs. Accurate and efficient simulation test data for the controller is achieved.

[0107] Optionally, in an embodiment of the present application, the method further includes:

[0108] receiving a timing request from the first processor core;

[0109] Among them, the timing request is a message sent to other devices or systems to request the provision of time information, which can be used to ensure the time synchronization of various devices or systems, thereby meeting the requirements for time accuracy in various application scenarios.

[0110] In the case of a single board, sending a clock to the board in response to the timing request;

[0111] When there are multiple boards, one of the boards is selected as the master node board, and the boards other than the master node board are used as slave node boards. The clock is sent to the master node board in response to the timing request; the master node board is used to synchronize the clock to the slave node board.

[0112] In some embodiments of the present application, the first processor core may request its system time from the bus simulation development software. After receiving the timing request from the first processor core, the bus simulation development software may send a clock to the first processor core that sent the request. In the case where only a single board is used independently, the bus simulation development software responds to the timing request and directly sends a clock to the first processor core on this board. In the case where there are multiple boards used in conjunction in the system, the bus simulation development software responds to the timing request and may first select one of the multiple boards used in conjunction as the master node board, and use the remaining boards except the master node board as slave node boards, and then send a clock to the first processor core on the master node board. After receiving the clock synchronization system time, the first processor core on the master node board synchronizes the clock to each slave node board via Ethernet. For example, refer to Figure 2 , TSN architecture can be used to achieve clock synchronization. The FPGA on the board can obtain timing through the first processor core on the same board, or through an external GPS. Through the above steps, the PXI or PCI architecture can be separated, so that the clock synchronization between boards can be achieved through Ethernet TSN, and each board can be used independently. When multiple boards are used, all communication data in the system can also maintain clock synchronization. While overcoming the cost problem of PXI / PCI benches in traditional test systems, it can also ensure the real-time performance of simulation tests.

[0113] It should be noted that, for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the described order of actions, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0114] On the basis of the above embodiments, this embodiment further provides a simulation test system, which is applied to electronic devices such as terminal devices and servers.

[0115] Reference Figure 4 , shows a structural block diagram of a simulation test system embodiment of the present application, which may specifically include the following modules:

[0116] The simulation test tool acquisition module 401 is used to acquire the simulation test tool on the bus simulation development software; the simulation test tool includes a test message to be sent, the bus simulation development software is connected to the controller under test through a board, and the board includes a first processor core and a second processor core;

[0117] The sending module 402 is used to send the simulation test tool to the first processor core; the first processor core is used to call the second processor core according to the simulation test tool, and the second processor core is used to send the test message in the simulation test tool to the controller under test;

[0118] The receiving module 403 is used to receive a response message returned by the controller under test in response to the test message;

[0119] The display module 404 is used to display the test message and the response message as simulation test data.

[0120] Optionally, the simulation test system further includes:

[0121] The first test message acquisition module is used to control the first processor core to acquire the test message by running the simulation test tool.

[0122] Optionally, the simulation test system further includes:

[0123] A first database acquisition module, used for acquiring a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message;

[0124] A first synchronization module, used for synchronizing the first data to a second signal database of the first processor core to obtain corresponding second data;

[0125] The second test message acquisition module is used to control the first processor core to run the simulation test tool and obtain the test message according to the second data analysis.

[0126] Optionally, the simulation test system further includes:

[0127] A second database acquisition module is used to acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message;

[0128] A sending cycle definition module, used to define a sending cycle of the test message in the first signal database; the sending cycle is used to control the frequency of the first processor core calling the second processor core;

[0129] A second synchronization module, used for synchronizing the first data and the sending cycle to a third signal database of the first processor core to obtain third data;

[0130] The third test message acquisition module is used to control the first processor core to run the simulation test tool and obtain the test message according to the third data analysis.

[0131] Optionally, the simulation test system further includes:

[0132] A control command generating module, used for controlling the first processor core to generate a control command for calling the second processor core according to the simulation test tool;

[0133] A control command response module is used to control the second processor core to receive the control command and test message sent by the first processor core, and then respond to the control command to send the test message to the controller under test through the programmable logic device on the board; the programmable logic device is used to add a timestamp to the test message when sending the test message.

[0134] Optionally, the display module further includes:

[0135] A message display submodule, used to directly display the test message and the response message;

[0136] A parsing submodule, configured to parse the test message and the response message according to the message structure and signal name stored in the first signal database to generate parsing data;

[0137] The parsed data display submodule is used to display the parsed data.

[0138] Optionally, the simulation test system further includes:

[0139] A timing request receiving module, used for receiving a timing request from the first processor core;

[0140] The timing module is used to respond to the timing request and send a clock to the board in the case of a single board; in the case of multiple boards, select one of the boards as the master node board, and use the boards other than the master node board as slave node boards, and respond to the timing request and send a clock to the master node board; the master node board is used to synchronize the clock to the slave node board.

[0141] A simulation test system provided by an embodiment of the present application can obtain a simulation test tool on a bus simulation development software, wherein the simulation test tool contains a test message to be sent, and the bus simulation development software is connected to a controller under test through a board, and the board contains a first processor core and a second processor core. The simulation test tool is sent to the first processor core, and the first processor core is used to call the second processor core according to the simulation test tool to send the test message in the simulation test tool to the controller under test. The hardware control command can be directly called to ensure the real-time performance of the simulation test process and improve the test efficiency. The response message returned by the controller under test in response to the test message is received, and the test message and the response message are used as simulation test data and displayed, so that the simulation test data of the controller can be accurately and efficiently obtained.

[0142] As for the above-mentioned system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0143] The embodiment of the present application also provides a non-volatile readable storage medium, which stores one or more modules (programs). When the one or more modules are applied to a device, the device can execute instructions (instructions) of each method step in the embodiment of the present application.

[0144] The present application embodiment provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, one or more simulation test methods in the above embodiments are implemented. In the present application embodiment, the electronic device includes various types of devices such as terminal devices and servers (clusters).

[0145] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0146] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable simulation test terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable simulation test terminal device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory that can guide a computer or other programmable simulation test terminal device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable simulation test terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0150] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0151] The above is a detailed introduction to a simulation test method and device, an electronic device and a storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A simulation test method, characterized in that: The method comprises: Obtain a simulation test tool on bus simulation development software; the simulation test tool includes a test message to be sent, the bus simulation development software is connected to the controller under test through a board, and the board includes a first processor core and a second processor core; Sending the simulation test tool to the first processor core; the first processor core is used to call the second processor core according to the simulation test tool, and the second processor core is used to send the test message in the simulation test tool to the controller under test; Receiving a response message returned by the controller under test in response to the test message; The test message and the response message are used as simulation test data and displayed.

2. The method according to claim 1, characterized in that After sending the simulation test tool to the first processor core, the method further includes: Control the first processor core to obtain the test message by running the simulation test tool.

3. The method according to claim 1, characterized in that After sending the simulation test tool to the first processor core, the method further includes: Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message; Synchronizing the first data to a second signal database of the first processor core to obtain corresponding second data; The first processor core is used to run the simulation test tool and obtain the test message according to the second data analysis.

4. The method according to claim 1, characterized in that: After sending the simulation test tool to the first processor core, the method further includes: Acquire a first signal database on the bus simulation development software, wherein the first data in the first signal database includes a message structure and a signal name of the test message; A sending period of the test message is defined in the first signal database; the sending period is used to control the frequency of the first processor core calling the second processor core; Synchronize the first data and the sending cycle to a third signal database of the first processor core to obtain third data; The first processor core is controlled to run the simulation test tool, and the test message is obtained according to the third data analysis.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: Controlling the first processor core to generate a control command for calling the second processor core according to the simulation test tool; After controlling the second processor core to receive the control command and test message sent by the first processor core, respond to the control command to send the test message to the controller under test through the programmable logic device on the board; the programmable logic device is used to add a timestamp to the test message when sending the test message.

6. The method according to claim 3, characterized in that The method of using the test message and the response message as simulation test data and displaying them further includes: Directly display the test message and the response message; or, according to the message structure and signal name stored in the first signal database, parsing the test message and the response message to generate parsing data; The parsed data is displayed.

7. The method according to claim 1, characterized in that The method further comprises: receiving a timing request from the first processor core; In the case of a single board, sending a clock to the board in response to the timing request; When there are multiple boards, one of the boards is selected as the master node board, and the boards other than the master node board are used as slave node boards. The clock is sent to the master node board in response to the timing request; the master node board is used to synchronize the clock to the slave node board.

8. A simulation test system, characterized in that: The system comprises: A simulation test tool acquisition module is used to acquire a simulation test tool on a bus simulation development software; the simulation test tool includes a test message to be sent, the bus simulation development software is connected to the controller under test through a board, and the board includes a first processor core and a second processor core; A sending module, used for sending the simulation test tool to the first processor core; the first processor core is used for calling the second processor core according to the simulation test tool, and the second processor core is used for sending the test message in the simulation test tool to the controller under test; A receiving module, used for receiving a response message returned by the controller under test in response to the test message; The display module is used to display the test message and the response message as simulation test data.

9. An electronic device, characterized in that: include: processor; and A memory having executable codes stored thereon, which, when executed, enables the processor to execute the simulation test method as described in one or more of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the simulation test method according to one or more of claims 1-7 is implemented.

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