Interrupt signal control circuit and electronic equipment

Abstract

The embodiment of the invention provides an interrupt signal control circuit and electronic equipment, the circuit comprises a first register, a second register, a third register, a multiplexer and an exclusive-OR gate, a fifth input end and a sixth input end of the exclusive-OR gate are respectively connected with a first output end of the first register and a third positive output end of the third register; when the signals of the fifth input end and the sixth input end are the same, the output interrupt signal is a first numerical value and represents interrupt clearing, and when the signals of the fifth input end and the sixth input end are different, the output interrupt signal is a second numerical value and represents interrupt generation, so that only three cascaded registers, one multiplexer and one exclusive-OR gate are used; and the generation and clearing of the interrupt signal are controlled, so that the interrupt signal is reliably and stably generated and cleared under the condition of low hardware overhead.

Description

Technical Field

[0001] The present invention relates to the technical field of control circuits, and in particular to a control circuit and electronic equipment for interrupt signals. Background Art

[0002] In digital circuit design, the interrupt signals of each module of the chip in the system are important windows for the interaction between hardware and software. The hardware circuit generates reliable and stable interrupt signals to correctly access the CPU (Central Processing Unit); after executing the relevant scheduling scheme, the CPU clears the interrupt signal. The reliable and stable generation and correct clearing of interrupt signals are crucial steps in system operation. For chip production, the smaller the area, the lower the cost. However, it is currently difficult to reliably and stably generate and clear interrupt signals under low hardware overhead conditions. There are problems such as interrupt signal generation errors, incorrect effects on the CPU, and inability to correctly respond to CPU clear operations. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide an interrupt signal control circuit and electronic device that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problem, an embodiment of the present invention discloses a control circuit of an interrupt signal, characterized in that the circuit comprises: a first register, a second register, a third register, a multiplexer and an XOR gate;

[0005] The first register includes a first input terminal and a first output terminal;

[0006] The second register comprises a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal and is used to receive a first output signal of the first register;

[0007] The third register comprises a third input terminal, a third positive output terminal and a third negative output terminal; the third input terminal is connected to the second output terminal, and is used to receive the second output signal of the second register;

[0008] The multiplexer includes a fourth positive input terminal, a fourth negative input terminal and a fourth output terminal; the fourth positive input terminal is connected to the third positive output terminal; the fourth negative input terminal is connected to the third negative output terminal; the fourth output terminal is connected to the first input terminal; the fourth output terminal is configured to output based on an input signal of the fourth positive input terminal or an input signal of the fourth negative input terminal;

[0009] The XOR gate includes a fifth input terminal, a sixth input terminal and a fifth output terminal; the fifth input terminal is connected to the first output terminal; the sixth input terminal is connected to the third positive output terminal; the XOR gate is used to output an interrupt signal of a first value when the signals at the fifth input terminal and the sixth input terminal are the same, indicating that the interrupt is cleared; and output the interrupt signal of a second value when the signals at the fifth input terminal and the sixth input terminal are different, indicating that an interrupt is generated.

[0010] Optionally, the multiplexer includes a control end; the control end is used to receive a selection signal and control the fourth output end to output based on an input signal of the fourth positive input end or an input signal of the fourth negative input end according to the selection signal.

[0011] Optionally, when the selection signal is the first numerical value, the control end is used to control the fourth output end to output based on the input signal of the fourth positive input end; when the selection signal is the second numerical value, the control end is used to control the fourth output end to output based on the input signal of the fourth negative input end.

[0012] Optionally, the second register includes a second trigger enable terminal for receiving an interrupt clear signal; the third register includes a third trigger enable terminal for receiving a reverse signal of the interrupt clear signal;

[0013] When the interrupt clear signal is the first value, the output signal of the second output terminal maintains the current output signal; when the inverse signal of the interrupt clear signal is the second value, the output signal of the third positive output terminal is updated to the output signal of the second output terminal;

[0014] When the interrupt clear signal is the second value, the output signal of the second output terminal is updated to the input signal of the second input terminal; the inverse signal of the interrupt clear signal is the first value, and the output signal of the third positive output terminal maintains the current output signal.

[0015] Optionally, the first register further includes a first clock terminal, a first reset terminal and a first trigger enable terminal, and the first trigger enable terminal is used to receive an enable signal; the second register further includes a second clock terminal and a second reset terminal; the third register further includes a third clock terminal and a third reset terminal; the multiplexer includes a fourth trigger enable terminal for receiving the enable signal;

[0016] During initialization, the first clock terminal, the second clock terminal and the third clock terminal are respectively used to receive clock signals; the first reset terminal, the second reset terminal and the third reset terminal are respectively used to receive reset signals; the interrupt clear signal is configured as the first value, the selection signal is configured as the first value, and the enable signal is configured as the first value; so that the first output terminal outputs the first value, the second output terminal outputs the first value, the third positive output terminal outputs the first value, and the interrupt signal is the first value.

[0017] Optionally, after the initialization, when the first preset condition is met, the selection signal and the enable signal are configured to be a second value; when the selection signal and the enable signal are configured to be the second value, the input end of the multiplexer is the fourth negative input end, and the fourth output end outputs the second value, so that the first input end outputs the second value; after one clock cycle, the first output end outputs the second value; the second output end outputs the first value; the third positive output end outputs the first value; so that the fifth output end outputs an interrupt signal with the second value, indicating that an interrupt has occurred.

[0018] Optionally, when the interrupt signal outputted from the fifth output terminal is a second value and the interrupt clear signal is configured as the second value, the second output terminal outputs the second value; the third positive output terminal outputs the first value; after one clock cycle, the interrupt clear signal is configured as the first value; the third positive output terminal outputs the second value; so that the interrupt signal outputted from the fifth output terminal is the first value, indicating that the interrupt is cleared.

[0019] Optionally, after the fifth output terminal outputs an interrupt signal as the second value, the selection signal is configured as the first value when a second preset condition is met; when the selection signal is configured as the first value, the input terminal of the multiplexer is the fourth positive input terminal, and the fourth output terminal outputs the first value, so that the first input terminal outputs the first value; after one clock cycle, the first output terminal outputs the first value; the second output terminal outputs the first value; the third positive output terminal outputs the first value; so that the fifth output terminal outputs an interrupt signal as the first value, indicating that the interrupt is cleared.

[0020] Optionally, the first preset condition is detection of an interrupt event; and the second preset condition is detection of an interrupt clearing event.

[0021] Accordingly, an embodiment of the present invention discloses an electronic device, including the interrupt signal control circuit as described above.

[0022] The embodiments of the present invention include the following advantages:

[0023] A control circuit for an interrupt signal according to an embodiment of the present invention comprises a first register, a second register, a third register, a multiplexer and an XOR gate, wherein the first register comprises a first input terminal and a first output terminal; the second register comprises a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal and is used to receive a first output signal of the first register; the third register comprises a third input terminal, a third positive output terminal and a third negative output terminal; the third input terminal is connected to the second output terminal and is used to receive a second output signal of the second register; the multiplexer comprises a fourth positive input terminal, a fourth negative input terminal and a fourth output terminal; the fourth positive input terminal is connected to the first output terminal and is used to receive a second output signal of the second register; The third positive output terminal is connected; the fourth negative input terminal is connected to the third negative output terminal; the fourth output terminal is connected to the first input terminal; the fourth output terminal is configured to output based on the input signal of the fourth positive input terminal or the input signal of the fourth negative input terminal; the XOR gate includes a fifth input terminal, a sixth input terminal and a fifth output terminal; the fifth input terminal is connected to the first output terminal; the sixth input terminal is connected to the third positive output terminal; the XOR gate is used to output an interrupt signal of a first value when the signals of the fifth input terminal and the sixth input terminal are the same, indicating that the interrupt is cleared; when the signals of the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that an interrupt has occurred. The first output of the first register and the third positive output of the third register are connected respectively through the fifth input terminal and the sixth input terminal of the XOR gate. When the signals at the fifth input terminal and the sixth input terminal are the same, the output interrupt signal is a first value, indicating that the interrupt is cleared. When the signals at the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that the interrupt is generated. Therefore, only three cascaded registers, a multiplexer and an XOR gate are used to control the generation and clearing of interrupt signals, thereby realizing reliable and stable generation and clearing of interrupt signals under low hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of a control circuit of an interrupt signal according to an embodiment of the present invention;

[0025] Figure 2 It is a schematic diagram of the structure of another interrupt signal control circuit according to an embodiment of the present invention.

[0026] Figure numerals: first register 10, first input terminal 11, first output terminal 12, first clock terminal 13, first reset terminal 14, first trigger enable terminal 15, second register 20, second input terminal 21, second output terminal 22, second trigger enable terminal 23, second clock terminal 24, second reset terminal 25, third register 30, third input terminal 31, third positive output terminal 32, third negative output terminal 33, third trigger enable terminal 34, third clock terminal 35, third reset terminal 36, multiplexer 40, fourth positive input terminal 41, fourth negative input terminal 42, fourth output terminal 43, control terminal 44, fourth trigger enable terminal 45, XOR gate 50, fifth input terminal 51, sixth input terminal 52, fifth output terminal 53. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] In digital circuit design, the interrupt signals of various modules of the chip in the system are important windows for the interaction between hardware and software. The hardware circuit generates reliable and stable interrupt signals to correctly access the CPU; after the CPU executes the relevant scheduling scheme, it clears the interrupt signal. The reliable and stable generation and correct clearing of interrupt signals are crucial steps in system operation. For chip production, the smaller the area, the lower the cost. However, under the condition of low hardware overhead, it is difficult to reliably and stably generate and clear interrupt signals. There are problems such as interrupt signal generation errors, incorrect effects on the CPU, and inability to correctly respond to CPU clear operations.

[0029] One of the core concepts of the embodiment of the present invention is that the first output terminal of the first register and the third positive output terminal of the third register are connected respectively through the fifth input terminal and the sixth input terminal of the XOR gate. When the signals at the fifth input terminal and the sixth input terminal are the same, the output interrupt signal is a first value, indicating that the interrupt is cleared. When the signals at the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that the interrupt is generated. Therefore, only three cascaded registers, a multiplexer and an XOR gate are used to control the generation and clearing of interrupt signals, thereby achieving reliable and stable generation and clearing of interrupt signals under low hardware overhead.

[0030] Reference Figure 1 , shows a schematic structural diagram of an interrupt signal control circuit according to an embodiment of the present invention, which may specifically include: a first register 10, a second register 20, a third register 30, a multiplexer 40 and an XOR gate 50.

[0031] Registers are an important component of computer hardware and are used to temporarily store data and instructions. They are located inside the central processing unit (CPU) and are the fastest storage units that the CPU can directly access. The main function of registers is to speed up the processing and operation of data because they are faster than main memory.

[0032] The first register 10 includes a first input terminal 11 and a first output terminal 12 , and INT_1 is the output of the first register 10 .

[0033] The port of a register usually refers to the interface between the register and an external device or internal component. These ports are used for data input and output, as well as the transmission of control signals. The input port is used to load data from an external device or internal component into the register, and the output port is used to send data in the register to an external device or internal component.

[0034] The second register 20 includes a second input terminal 21 and a second output terminal 22 . The second input terminal 21 is connected to the first output terminal 12 and is used to receive the first output signal of the first register 10 . INT_2 is the output of the second register 20 .

[0035] The third register 30 includes a third input terminal 31 , a third positive output terminal 32 and a third negative output terminal 33 . The third input terminal 31 is connected to the second output terminal 22 for receiving the second output signal of the second register 20 .

[0036] The third register 30 has two output terminals, namely a third positive output terminal 32 and a third negative output terminal 33, wherein the third positive output terminal 32 represents the value currently stored in the register, and the third negative output terminal 33 represents the inversion (i.e., negation) of the current value. INT_3 is the output of the third positive output terminal 32 of the third register 30, and ~INT_3 is the output of the third negative output terminal 33 of the third register 30.

[0037] The first register 10, the second register 20 and the third register 30 are three cascaded registers. The cascaded register refers to connecting multiple registers in series to form a longer shift register or storage unit. The cascaded register is usually used to implement applications such as shift operations, data delays, and pipeline processing. Each register has its own input and output ports and works synchronously through a clock signal.

[0038] The multiplexer 40 includes a fourth positive input terminal 41, a fourth negative input terminal 42 and a fourth output terminal 43. The fourth positive input terminal 41 is connected to the third positive output terminal 32, the fourth negative input terminal 42 is connected to the third negative output terminal 33, the fourth output terminal 43 is connected to the first input terminal 11, and the fourth output terminal 43 is configured to output based on the input signal of the fourth positive input terminal 41 or the input signal of the fourth negative input terminal 42.

[0039] Multiplexers are used to select one signal from multiple input signals and pass it to the output. Multiplexers are often used in applications such as data selection, signal routing, and data bus control. The basic structure of a multiplexer includes: input port, multiple input signals; selection port, control signal for selecting input signals; output port: single output signal. The working principle of a multiplexer is to select an input signal through the selection port (control signal) and pass it to the output. The value of the selection port determines which input signal is selected.

[0040] The multiplexer 40 has two input terminals, namely a fourth positive input terminal 41 and a fourth negative input terminal 42. The fourth positive input terminal 41 is connected to the third positive output terminal 32 of the third register 30, for receiving the output signal of the third positive output terminal 32; the fourth negative input terminal 42 is connected to the third negative output terminal 33 of the third register 30, for receiving the output signal of the third negative output terminal 33; the fourth output terminal 43 is configured to output based on the input signal of the fourth positive input terminal 41 or the input signal of the fourth negative input terminal 42.

[0041] The XOR gate 50 includes a fifth input terminal 51, a sixth input terminal 52 and a fifth output terminal 53. The fifth input terminal 51 is connected to the first output terminal 12, and the sixth input terminal 52 is connected to the third positive output terminal 32. The XOR gate is used to output an interrupt signal of a first value when the signals of the fifth input terminal 51 and the sixth input terminal 52 are the same, indicating that the interrupt is cleared; when the signals of the fifth input terminal 51 and the sixth input terminal 52 are different, the interrupt signal is output as a second value, indicating that an interrupt is generated. INT is the output of the XOR gate 50.

[0042] XOR gate is a basic logic gate used to implement XOR logic operation. The output of XOR gate is high level (1) if and only if one and only one of its inputs is high level (1). The logic expression of XOR gate is: Y = A ⊕ B, where A and B are input signals and Y is output signal.

[0043] The XOR gate 50 includes two input terminals, namely a fifth input terminal 51 and a sixth input terminal 52. The fifth input terminal 51 is connected to the first output terminal 12 of the first register 10 for receiving the output signal of the first register 10; the sixth input terminal 52 is connected to the third positive output terminal 32 of the third register 30 for receiving the output signal of the third register 30.

[0044] The fifth output terminal 53 of the XOR gate 50 performs an XOR output according to the input signals of the fifth input terminal 51 and the sixth input terminal 52. When the signals of the fifth input terminal 51 and the sixth input terminal 52 are the same, the output interrupt signal is a first value, indicating that the interrupt is cleared. Exemplarily, the first value is 0, indicating a low level. That is, when the output signal of the first register 10 is the same as the output signal of the third register 30, the XOR gate 50 outputs an interrupt signal of a low level, indicating that the interrupt is cleared.

[0045] When the signals at the fifth input terminal 51 and the sixth input terminal 52 are different, the output interrupt signal is a second value, indicating that an interrupt has occurred. Exemplarily, the second value is 1, indicating a high level. That is, when the output signal of the first register 10 is different from the output signal of the third register 30, the XOR gate 50 outputs an interrupt signal of a high level, indicating that an interrupt has occurred.

[0046] A control circuit for an interrupt signal according to an embodiment of the present invention comprises a first register, a second register, a third register, a multiplexer and an XOR gate, wherein the first register comprises a first input terminal and a first output terminal; the second register comprises a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal and is used to receive a first output signal of the first register; the third register comprises a third input terminal, a third positive output terminal and a third negative output terminal; the third input terminal is connected to the second output terminal and is used to receive a second output signal of the second register; the multiplexer comprises a fourth positive input terminal, a fourth negative input terminal and a fourth output terminal; the fourth positive input terminal is connected to the first output terminal and is used to receive a second output signal of the second register; The third positive output terminal is connected; the fourth negative input terminal is connected to the third negative output terminal; the fourth output terminal is connected to the first input terminal; the fourth output terminal is configured to output based on the input signal of the fourth positive input terminal or the input signal of the fourth negative input terminal; the XOR gate includes a fifth input terminal, a sixth input terminal and a fifth output terminal; the fifth input terminal is connected to the first output terminal; the sixth input terminal is connected to the third positive output terminal; the XOR gate is used to output an interrupt signal of a first value when the signals of the fifth input terminal and the sixth input terminal are the same, indicating that the interrupt is cleared; when the signals of the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that an interrupt has occurred. The first output of the first register and the third positive output of the third register are connected respectively through the fifth input terminal and the sixth input terminal of the XOR gate. When the signals at the fifth input terminal and the sixth input terminal are the same, the output interrupt signal is a first value, indicating that the interrupt is cleared. When the signals at the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that the interrupt is generated. Therefore, only three cascaded registers, a multiplexer and an XOR gate are used to control the generation and clearing of interrupt signals, thereby realizing reliable and stable generation and clearing of interrupt signals under low hardware overhead.

[0047] Reference Figure 2, shows a structural schematic diagram of another interrupt signal control circuit of an embodiment of the present invention, the multiplexer includes a control terminal 44, the control terminal 44 is used to receive a selection signal, and control the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41 or the input signal of the fourth negative input terminal 42 according to the selection signal.

[0048] The control terminal 44 receives the SEL selection signal, and controls the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41 or based on the input signal of the fourth negative input terminal 42 according to the SEL selection signal.

[0049] In an embodiment of the present invention, when the selection signal is a first value, the control terminal 44 is used to control the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41; when the selection signal is a second value, the control terminal 44 is used to control the fourth output terminal 43 to output based on the input signal of the fourth negative input terminal 42.

[0050] Exemplarily, the first value is 0, and when the control terminal 44 receives a selection signal of 0, it controls the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41, that is, based on the output signal of the third positive output terminal 32 of the third register 30.

[0051] Exemplarily, the second value is 1, and when the control terminal 44 receives a selection signal of 1, it controls the fourth output terminal 43 to output based on the input signal of the fourth negative input terminal 42, that is, based on the output signal of the third negative output terminal 33 of the third register 30.

[0052] In the embodiment of the present invention, the second register 20 includes a second trigger enable terminal 23 for receiving an interrupt clear signal; the third register 30 includes a third trigger enable terminal 34 for receiving an inverse signal of the interrupt clear signal.

[0053] The enable terminal of a register is a control signal used to control the write operation of the register. When the enable signal is valid, the register can receive input data and store it internally. When the enable signal is invalid, the register maintains its current value and does not receive new input data. The enable terminal of a register is usually used in conjunction with a clock signal (Clock). At the rising or falling edge of the clock signal, if the enable signal is valid, the register will receive input data and update its internally stored value. If the enable signal is invalid, the register will maintain its current value and will not perform a write operation. The enable terminal as a port means that it is an input port for receiving external control signals. This control signal can come from other circuit modules or external control logic. Through this port, external signals can control the behavior of the register. The enable terminal as a control signal means that it is used to control the write operation of the register. When the enable signal is valid, the register can receive input data and update its internally stored value; when the enable signal is invalid, the register maintains its current value and does not perform a write operation.

[0054] The second trigger enable terminal 23 is used to receive an interrupt clear signal (INT_CLR). When the interrupt clear signal is valid and at the rising edge or falling edge of the clock signal, the second register 20 will receive input data and update its internally stored value. At this time, the second register 20 outputs the updated value; the third trigger enable terminal 34 is used to receive the reverse signal of the interrupt clear signal (~INT_CLR). When the reverse signal of the interrupt clear signal is valid and at the rising edge or falling edge of the clock signal, the third register 30 will receive input data and update its internally stored value.

[0055] That is to say, when the interrupt clear signal is valid and at the rising edge or falling edge of the clock signal, the second register 20 will receive input data and update its internally stored value, output the updated value, and the third register 30 will maintain its current value, no write operation will be performed, and the output will still be the current value; when the interrupt clear signal is invalid, the second register 20 will maintain its current value, no write operation will be performed, the output will still be the current value, and at the rising edge or falling edge of the clock signal, the third register 30 will receive input data and update its internally stored value, and output the updated value.

[0056] The interrupt clear signal (INT_CLR) indicates the CPU interrupt clear signal. When the hardware circuit detects that the CPU needs to intervene during operation, it will set a signal, that is, the output signal of XOR gate 50 (INT, the interrupt signal of the module). This signal is directly transmitted to the CPU to tell the CPU that the CPU needs to control. After the CPU executes the corresponding interrupt processing according to the scheduling plan, the CPU will set an interrupt clear signal to tell the hardware that the CPU has completed the processing of the interrupt.

[0057] When the interrupt clear signal is the first value, the output signal of the second output terminal 22 maintains the current output signal; the inverse signal of the interrupt clear signal is the second value, and the output signal of the third positive output terminal 32 is updated to the output signal of the second output terminal 22.

[0058] Exemplarily, the first value is 0, indicating a low level. When the interrupt clear signal is 0 low level, the output signal of the second output terminal 21 of the second register 20 maintains the current output signal and does not update the value. The reverse signal of the interrupt clear signal 0 is 1 high level, and the output signal of the third positive output terminal 32 of the third register 30 is updated to the output signal of the second output terminal 21 of the second register 20, and the value is updated. That is to say, when the interrupt clear signal is 0 low level, the output signal of the second register 20 maintains the current output signal and does not update the value, and the output signal of the third register 30 is updated to the output signal of the second register 20.

[0059] When the interrupt clear signal is the second value, the output signal of the second output terminal 22 is updated to the input signal of the second input terminal 22; the reverse signal of the interrupt clear signal is the first value, and the output signal of the third positive output terminal 32 maintains the current output signal.

[0060] Exemplarily, the second numerical value is 1, indicating a high level. When the interrupt clear signal is 1 high level, the output signal of the second output terminal 21 of the second register 20 is updated to the input signal of the second input terminal 22, the reverse signal of the interrupt clear signal 1 is 0 low level, and the output signal of the third positive output terminal 32 of the third register 30 maintains the current output signal without updating the value.

[0061] In an embodiment of the present invention, the first register 10 also includes a first clock terminal 13, a first reset terminal 14 and a first trigger enable terminal 15, and the first trigger enable terminal 15 is used to receive an enable signal (ENABLE); the second register 20 also includes a second clock terminal 24 and a second reset terminal 25; the third register 30 also includes a third clock terminal 35 and a third reset terminal 36; the multiplexer 40 includes a fourth trigger enable terminal 45, which is used to receive the enable signal (ENABLE).

[0062] The clock terminal (CLK) is an important control signal of the register, which is used to synchronize the operation of the register. The clock signal is usually a periodic square wave signal, whose rising or falling edge is used to trigger the write operation of the register, and the reset terminal (RSTJ) is used to initialize the register to a predefined state. The reset signal is usually asynchronous, that is, it is not affected by the clock signal.

[0063] During initialization, the first clock terminal 13, the second clock terminal 24 and the third clock terminal 35 are respectively used to receive clock signals, and the received clock signals are the same clock signal. After the clock is turned on, the first reset terminal 14, the second reset terminal 25 and the third reset terminal 36 are respectively used to receive reset signals; the interrupt clear signal is configured as the first value (0), the selection signal is configured as the first value (0), and the enable signal is configured as the first value (0). Due to the reset, the first output terminal 12 outputs the first value (0), INT_1 is the output of the first register 10, which is 0; the second output terminal 22 outputs the first value (0), INT_2 is the output of the second register 20, which is 0; the third positive output terminal 32 outputs the first value (0), INT_3 is the output of the third positive output terminal 32 of the third register 30, which is 0, and ~INT_3 is the output of the third negative output terminal 33 of the third register 30, which is 1; at this time, the output signal of the first output terminal 12 is the same as the output signal of the third positive output terminal 32, both of which are 0, and the interrupt signal is the first value (0).

[0064] In an embodiment of the present invention, after the initialization, when the first preset condition is met, the selection signal and the enable signal are configured to be a second value; when the selection signal and the enable signal are configured to be the second value, the input end of the multiplexer is the fourth negative input end 42, and the fourth output end 43 outputs the second value, so that the first input end 11 outputs the second value; after one clock cycle, the first output end 12 outputs the second value; the second output end 12 outputs the first value; the third positive output end 32 outputs the first value; so that the fifth output end 53 outputs an interrupt signal with a second value, indicating that an interrupt has occurred.

[0065] Specifically, after the module is initialized, the module starts to run, and no interruption is detected. When the module detects an interruption during operation, the selection signal and the enable signal are set, and both the selection signal and the enable signal are set to 1. At this time, the trigger enable of the multiplexer 40, the first register 10 and the third register 30 are turned on, and the trigger enable of the second register 20 is turned on and off. Since the selection signal is 1, the multiplexer 40 selects ~INT_3 and passes it to its fourth output terminal 43. At this time, ~INT_3 is 1, then the output of the fourth output terminal 43 of the multiplexer 40 is 1. Since the fourth output terminal 43 is connected to the first input terminal 11 of the first register 10, the first input terminal 11 of the first register 10 is 1 at this time. Since the enable signal of the first register 10 is 1, after one clock cycle, the first output terminal 12 of the first register 10 updates the output value from 0 to 1. Since there is only one clock cycle A rising edge, so it can be said that it changes once a cycle, the first register 10 will update the value when the enable signal is valid and at a rising edge; since INT_CLR is 0 at this time, the trigger enable of the second register 20 is turned off, and the value is not updated, and the output of the second output terminal 22 of the second register 20 is still the current value 0; since ~INT_CLR is 1, the trigger enable of the third register 30 is turned on, and the third positive output terminal 32 of the third register 30 is updated to the value of the third input terminal 31. Since the third input terminal 31 is the value of the second output terminal 22 0, the third register 30 is still 0 after the update; at this time, the first output terminal 12 is 1, the second output terminal 22 is 0, the third positive output terminal 32 is 0, the fifth input terminal 51 of the XOR gate 50 is 1, and the sixth input terminal 52 is 0, the two are XORed, and the fifth output terminal 53 outputs an interrupt signal (INT) of 1, indicating that an interrupt has occurred and the interrupt is set.

[0066] The first preset condition is the detection of an interrupt event. For example, the module is an image data receiver. After receiving a frame of image, the hardware circuit will set an interrupt signal (this signal is generally called a receive interrupt) (telling the CPU that the hardware has received a frame of image). Detecting an interrupt, for the above example, means that the hardware detects that a frame of image has been received. At this time, if the circuit of this work is used to generate an interrupt signal, the selection signal and the enable signal need to be set.

[0067] In an embodiment of the present invention, when the interrupt signal outputted from the fifth output terminal 53 is a second value and the interrupt clear signal is configured as the second value, the second output terminal 22 outputs the second value; the third positive output terminal 32 outputs the first value; after one clock cycle, the interrupt clear signal is configured as the first value; the third positive output terminal 32 outputs the second value; so that the interrupt signal outputted from the fifth output terminal 53 is the first value, indicating that the interrupt is cleared.

[0068] Specifically, the fifth output terminal 53 outputs an interrupt signal of the second value, that is, the INT signal is 1, indicating that an interrupt has occurred. The INT signal will be directly transmitted to the CPU, telling the CPU that the CPU needs to perform control. After the CPU executes the corresponding interrupt processing according to the scheduling plan, the CPU will set an interrupt clear signal (INT_CLR), that is, after the CPU executes the interrupt processing, it will set INT_CLR from 0 to 1, telling the hardware that the CPU has completed processing the interrupt. When the hardware detects that INT_CLR is 1, it will pull down INT, that is, set INT from 1 to 0, and the interrupt processing is completed.

[0069] Exemplarily, the fifth output terminal 53 outputs an interrupt signal of 1, indicating that an interrupt has occurred. After the CPU executes the interrupt processing, it sets INT_CLR from 0 to 1, that is, the interrupt clear signal is configured as the second value. At this time, INT_CLR is 1, the trigger enable of the second register 20 is turned on, and the second output terminal 22 updates the value to the value of the second input terminal 21. The value of the second input terminal 21 is the first output terminal 12. Since the first output terminal 12 has been updated to 1 during the interrupt generation process, the value of the second input terminal 21 is also 1, and the second output terminal 22 updates the value from 0 to 1; after one clock cycle, the interrupt clear signal It is configured to 0, informing the hardware that the interrupt has been processed and the interrupt response is completed. At this time, the reverse signal of the interrupt clear signal is 1, the trigger enable of the third register 30 is turned on, and the third positive output terminal 32 updates the value to the value of the third input terminal 31. The value of the third input terminal 31 is the value of the second output terminal 22. Since the second output terminal 22 is 1, the third positive output terminal 32 is also 1. At this time, the first output terminal 12 is 1, the second output terminal 22 is 1, and the third positive output terminal 32 is 1. The fifth input terminal 51 of the XOR gate 50 is 1, the sixth input terminal 52 is 1, and the fifth output terminal 53 outputs the interrupt signal (INT) of 0, indicating that the interrupt is cleared.

[0070] In an embodiment of the present invention, after the fifth output terminal 53 outputs an interrupt signal as the second value, the selection signal is configured as the first value when the second preset condition is met; when the selection signal is configured as the first value, the input terminal of the multiplexer 40 is the fourth positive input terminal 41, and the fourth output terminal 43 outputs the first value, so that the first input terminal 11 outputs the first value; after one clock cycle, the first output terminal 12 outputs the first value; the second output terminal 22 outputs the first value; the third positive output terminal 32 outputs the first value; so that the fifth output terminal 53 outputs an interrupt signal as the first value, indicating that the interrupt is cleared.

[0071] Specifically, after the fifth output terminal 53 outputs the interrupt signal as the second value, that is, INT is 1, after the interrupt is generated, the hardware circuit detects the interrupt clearing condition and pulls down the SEL selection signal, and the selection signal is configured to 0. When the selection signal is configured to 0, the input terminal of the multiplexer 40 is the fourth positive input terminal 41. Since the fourth positive input terminal 41 is 0 at this time, the fourth output terminal 43 outputs 0, so that the first input terminal 11 outputs 0. Since the enable signal is 1, after one clock cycle, at the rising edge of the clock, the value of the first output terminal 12 is updated to the value of the first input terminal 11, that is, the value of the first output terminal 12 is updated from 1 to 0. Since the second output terminal 22 outputs 0; the third positive output terminal 32 outputs 0, so that the fifth output terminal 53 outputs the interrupt signal as 0, indicating that the interrupt is cleared.

[0072] The second preset condition is to detect an interrupt clearing event. From initialization to the hardware circuit detecting the interrupt, an additional part of the hardware interrupt clearing condition detection circuit can be added. When the condition is triggered, the SEL selection signal is pulled down and the enable signal is set. Next, take the module as an image data receiver as an example. After receiving a frame of image, the hardware circuit will set an interrupt signal (this signal is generally called a receive interrupt) (telling the CPU that the hardware has received a frame of image), but before waiting for the CPU to respond to the interrupt clearing signal, due to other interference factors (such as errors when continuing to receive image data), it is necessary to clear the received data (including the previous correct image). At this time, the hardware can be cleared and INT can be set to 0 (telling the CPU that CPU intervention is no longer required).

[0073] The entire interrupt handling process is as follows:

[0074] An interrupt request means that when the hardware circuit detects that the CPU needs to intervene during operation, it will set a signal (INT, IP interrupt signal). This signal is directly transmitted to the CPU, telling the CPU that the CPU needs to control it. After the CPU executes the corresponding interrupt processing according to the scheduling plan, the CPU will set an interrupt clear signal (INT_CLR) to tell the hardware that the CPU has completed processing the interrupt. When the hardware detects that INT_CLR is 1, it will pull down INT and the interrupt processing ends.

[0075] For the interrupt signal of a digital module, only three registers, one multiplexer and one XOR gate are used to build the circuit, and a ship lock model is formed by opening and closing the trigger enable of the second and third level registers. It effectively avoids burr competition and ensures high reliability. At the same time, the structure is concise, area is saved, there is no cumbersome control logic circuit, and the application is simple. It can be used on interrupt signals that do not require special processing to ensure that hardware and software can interact correctly through interrupt signals.

[0076] A control circuit for an interrupt signal according to an embodiment of the present invention comprises a first register, a second register, a third register, a multiplexer and an XOR gate, wherein the first register comprises a first input terminal and a first output terminal; the second register comprises a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal and is used to receive a first output signal of the first register; the third register comprises a third input terminal, a third positive output terminal and a third negative output terminal; the third input terminal is connected to the second output terminal and is used to receive a second output signal of the second register; the multiplexer comprises a fourth positive input terminal, a fourth negative input terminal and a fourth output terminal; the fourth positive input terminal is connected to the first output terminal and is used to receive a second output signal of the second register; The third positive output terminal is connected; the fourth negative input terminal is connected to the third negative output terminal; the fourth output terminal is connected to the first input terminal; the fourth output terminal is configured to output based on the input signal of the fourth positive input terminal or the input signal of the fourth negative input terminal; the XOR gate includes a fifth input terminal, a sixth input terminal and a fifth output terminal; the fifth input terminal is connected to the first output terminal; the sixth input terminal is connected to the third positive output terminal; the XOR gate is used to output an interrupt signal of a first value when the signals of the fifth input terminal and the sixth input terminal are the same, indicating that the interrupt is cleared; when the signals of the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that an interrupt has occurred. The first output of the first register and the third positive output of the third register are connected respectively through the fifth input terminal and the sixth input terminal of the XOR gate. When the signals at the fifth input terminal and the sixth input terminal are the same, the output interrupt signal is a first value, indicating that the interrupt is cleared. When the signals at the fifth input terminal and the sixth input terminal are different, the output interrupt signal is a second value, indicating that the interrupt is generated. Therefore, only three cascaded registers, a multiplexer and an XOR gate are used to control the generation and clearing of interrupt signals, thereby realizing reliable and stable generation and clearing of interrupt signals under low hardware overhead.

[0077] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0078] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0079] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0080] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0084] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0085] The above is a detailed introduction to an interrupt signal control circuit and an electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A control circuit for an interrupt signal, characterized in that: The circuit comprises: a first register, a second register, a third register, a multiplexer and an XOR gate; The first register includes a first input terminal and a first output terminal; The second register comprises a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal and is used to receive a first output signal of the first register; The third register comprises a third input terminal, a third positive output terminal and a third negative output terminal; the third input terminal is connected to the second output terminal, and is used to receive the second output signal of the second register; The multiplexer includes a fourth positive input terminal, a fourth negative input terminal and a fourth output terminal; the fourth positive input terminal is connected to the third positive output terminal; the fourth negative input terminal is connected to the third negative output terminal; the fourth output terminal is connected to the first input terminal; the fourth output terminal is configured to output based on an input signal of the fourth positive input terminal or an input signal of the fourth negative input terminal; The XOR gate includes a fifth input terminal, a sixth input terminal and a fifth output terminal; the fifth input terminal is connected to the first output terminal; the sixth input terminal is connected to the third positive output terminal; the XOR gate is used to output an interrupt signal of a first value when the signals at the fifth input terminal and the sixth input terminal are the same, indicating that the interrupt is cleared; and output the interrupt signal of a second value when the signals at the fifth input terminal and the sixth input terminal are different, indicating that an interrupt is generated.

2. The control circuit according to claim 1, characterized in that: The multiplexer includes a control terminal; the control terminal is used to receive a selection signal and control the fourth output terminal to output based on an input signal of the fourth positive input terminal or an input signal of the fourth negative input terminal according to the selection signal.

3. The control circuit according to claim 2, characterized in that: When the selection signal is the first value, the control end is used to control the fourth output end to output based on the input signal of the fourth positive input end; when the selection signal is the second value, the control end is used to control the fourth output end to output based on the input signal of the fourth negative input end.

4. The control circuit according to claim 3, characterized in that: The second register includes a second trigger enable terminal for receiving an interrupt clear signal; the third register includes a third trigger enable terminal for receiving an inverse signal of the interrupt clear signal; When the interrupt clear signal is the first value, the output signal of the second output terminal maintains the current output signal; when the inverse signal of the interrupt clear signal is the second value, the output signal of the third positive output terminal is updated to the output signal of the second output terminal; When the interrupt clear signal is the second value, the output signal of the second output terminal is updated to the input signal of the second input terminal; the inverse signal of the interrupt clear signal is the first value, and the output signal of the third positive output terminal maintains the current output signal.

5. The control circuit according to claim 4, characterized in that: The first register further includes a first clock terminal, a first reset terminal and a first trigger enable terminal, wherein the first trigger enable terminal is used to receive an enable signal; the second register further includes a second clock terminal and a second reset terminal; the third register further includes a third clock terminal and a third reset terminal; the multiplexer includes a fourth trigger enable terminal for receiving the enable signal; During initialization, the first clock terminal, the second clock terminal and the third clock terminal are respectively used to receive clock signals; the first reset terminal, the second reset terminal and the third reset terminal are respectively used to receive reset signals; The interrupt clear signal is configured as the first value, the selection signal is configured as the first value, and the enable signal is configured as the first value; so that the first output terminal outputs the first value, the second output terminal outputs the first value, the third positive output terminal outputs the first value, and the interrupt signal is the first value.

6. The control circuit according to claim 5, characterized in that: After the initialization, when the first preset condition is met, the selection signal and the enable signal are configured to be a second value; when the selection signal and the enable signal are configured to be the second value, the input end of the multiplexer is the fourth negative input end, and the fourth output end outputs the second value, so that the first input end outputs the second value; after one clock cycle, the first output end outputs the second value; the second output end outputs the first value; the third positive output end outputs the first value; so that the fifth output end outputs an interrupt signal with a second value, indicating that an interrupt has occurred.

7. The control circuit according to claim 6, characterized in that: When the interrupt signal output at the fifth output terminal is a second value and the interrupt clear signal is configured as the second value, the second output terminal outputs the second value; the third positive output terminal outputs the first value; after one clock cycle, the interrupt clear signal is configured as the first value; the third positive output terminal outputs the second value; so that the interrupt signal output at the fifth output terminal is the first value, indicating that the interrupt is cleared.

8. The control circuit according to claim 6, characterized in that: After the fifth output terminal outputs the interrupt signal as the second value, the selection signal is configured as the first value when the second preset condition is met; when the selection signal is configured as the first value, the input terminal of the multiplexer is the fourth positive input terminal, and the fourth output terminal outputs the first value, so that the first input terminal outputs the first value; after one clock cycle, the first output terminal outputs the first value; The second output terminal outputs the first value; the third positive output terminal outputs the first value; so that the fifth output terminal outputs an interrupt signal with the first value, indicating that the interrupt is cleared.

9. The control circuit according to claim 8, characterized in that: The first preset condition is that an interrupt event is detected; and the second preset condition is that an interrupt clearing event is detected.

10. An electronic device, characterized in that: A control circuit comprising an interrupt signal as claimed in any one of claims 1 to 9.

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