Ethernet 10GBASE-R PCS Gearbox Module

Abstract

The present invention relates to chip design, and in particular to a Gearbox module for Ethernet 10GBASE-R PCS. The module comprises a write depth pointer generation component, a write width pointer generation component, a write data control component, and a data FIFO component located in a write clock domain, and a read depth pointer generation component, a read width pointer generation component, and a read data control component located in a read clock domain. The write depth pointer generation component is used to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component; and the write width pointer generation component is used to generate a write width pointer pointing to a transverse bit position where write data is written in the data FIFO component. The technical solution provided by the present invention can effectively overcome the defect in the prior art that it is difficult to achieve seamless connection between an internal data bus of Ethernet 10GBASE-R PCS and a data interface of a physical medium attachment sublayer (PMA) through the Gearbox module.

Description

Technical Field

[0001] The present invention relates to chip design, in particular to a Gearbox module of Ethernet 10GBASE-RPCS. Background Art

[0002] According to the definition in Chapter 49 of the IEEE 802.3 protocol, the physical coding sublayer 10GBASE-RPCS (Physical Coding Sublayer) is located between the coordination sublayer Reconciliation and the physical medium attachment sublayer PMA (Physical Medium Attachment). The physical coding sublayer 10GBASE-RPCS is interconnected with the upper coordination sublayer Reconciliation through the XGMII (10Gigabit Media Independent Interface) interface, and is also interconnected with the lower physical medium attachment sublayer PMA through the XSBI (10Gigabit SixteenBit Interface) interface. Figure 4 shown.

[0003] The typical hardware structure of the physical coding sublayer 10GBASE-RPCS data transmission is as follows: Figure 5 As shown, the 64B / 66B encoding module, the scrambling module, and the gearbox module are primarily comprised of the 64B / 66B encoding module. The 64B / 66B encoding module converts 32-bit data received via the XGMII interface into 66-bit blocks. After scrambling by the scrambling module, the data is sent to the gearbox module. The gearbox module converts the 66-bit data into 16-bit data (xsbi_tx_data[15:0]), which is then sent to the physical media attachment sublayer (PMA) via the XSBI interface. The two clocks used for data transmission, rpcs_tx_clk and xsbi_tx_clk, are both provided by the PMA and share the same source. For standard 32-bit XGMII and 16-bit XSBI interfaces, the rpcs_tx_clk and xsbi_tx_clk frequencies are 312.5 MHz and 644.53125 MHz, respectively.

[0004] In actual designs, the data bus at the XGMII interface is designed in the standard 32-bit x 312.5MHz mode, or in the 64-bit x 156.25MHz mode, with a transmission rate of 10Gbps. After passing through the 64B / 66B encoding module, the transmission rate becomes 10.3125Gbps. To facilitate data processing, the internal data bus of the 10GBASE-RPCS physical coding sublayer is generally designed in either the 33-bit x 312.5MHz or 66-bit x 156.25MHz mode. In general, the data interface of the physical medium attachment sublayer (PMA) uses the standard XSBI mode (16-bit x 644.53125MHz) or the 20-bit x 515.625MHz mode, also with a transmission rate of 10.3125Gbps.

[0005] Therefore, it is very important to design a flexible and universal Gearbox module to achieve seamless connection between the internal data bus of Ethernet 10GBASE-RPCS and the data interface of the physical medium attachment sublayer PMA. Summary of the Invention

[0006] (1) Technical problems solved

[0007] In response to the above-mentioned shortcomings of the prior art, the present invention provides a Gearbox module for Ethernet 10GBASE-RPCS, which can effectively overcome the defect in the prior art that it is difficult to achieve seamless connection between the internal data bus of Ethernet 10GBASE-RPCS and the data interface of the physical medium attachment sublayer (PMA) through the Gearbox module.

[0008] (2) Technical solution

[0009] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0010] The Gearbox module of Ethernet 10GBASE-RPCS includes a write depth pointer generation component, a write width pointer generation component, a write data control component, and a data FIFO component located in the write clock domain, and a read depth pointer generation component, a read width pointer generation component, and a read data control component located in the read clock domain;

[0011] A write depth pointer generating component, configured to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component;

[0012] A write width pointer generating component, configured to generate a write width pointer pointing to a horizontal bit position where write data is written in the data FIFO component;

[0013] The write data control component writes the write data into the data FIFO component according to the write start bit position pointed to by the write depth pointer and the write width pointer;

[0014] Data FIFO component, used to store data;

[0015] A read depth pointer generating component, used for generating a read depth pointer pointing to a longitudinal position of read data read from the data FIFO component;

[0016] a read width pointer generating component, for generating a read width pointer pointing to a horizontal bit position of read data read from the data FIFO component;

[0017] The read data control component reads and stores the read data from the data FIFO component according to the read start bit position pointed to by the read depth pointer and the read width pointer;

[0018] Among them, the write clock domain and the read clock domain have the same origin.

[0019] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data writing process of the Gearbox module includes:

[0020] In the initial state, the write start bit position is Cycle0 (0, 0), the write depth pointer and the write width pointer are both 0, and the data FIFO component is empty;

[0021] Cycle1(1,3) is the write start bit position after the first group of 33 bits of write data is written to the data FIFO component. At this time, the write depth pointer is updated to 1 after incrementing by 1, and the write width pointer is updated to 3 after incrementing by 3.

[0022] Cycle2(2,6) is the write start bit position after the second group of 33 bits of write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 2, and the write width pointer is incremented by 3 and updated to 6.

[0023] After the ninth group of 33-bit write data is written into the data FIFO component, Cycle9(3,27) is the write start bit position of the tenth group of 33-bit write data into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 3, and the write width pointer is incremented by 3 and updated to 27.

[0024] Cycle10(5,0) is the write start bit position after the tenth group of 33-bit write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 2 and updated to 5, and the write width pointer is incremented by 3 and updated to 0.

[0025] Cycle11(0,3) is the write start bit position after the eleventh group of 33-bit write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 0, and the write width pointer is incremented by 3 and updated to 3.

[0026] After the above process is repeated, we get:

[0027] After every ten groups of 33-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all in steps of 1. After counting to 5, it loops back to 0, that is, modulo 6 addition. The write width pointer is incremented by 3. After counting to 27, it loops back to 0, that is, modulo 30 addition.

[0028] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data reading process of the Gearbox module includes:

[0029] In the initial state, the read start bit position is Cycle0 (0, 0), the read depth pointer and the write width pointer are both 0, and the data FIFO component stores data;

[0030] Cycle1(0,20) is the read start bit position after the first group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer remains unchanged and remains at 0. The read width pointer is updated to 20 after adding 20.

[0031] Cycle2(1,10) is the read start bit position after the second group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 1 after incrementing by 1, and the read width pointer is updated to 10 after incrementing by 20.

[0032] Cycle3(2,0) is the read start bit position after the third group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 2 after incrementing by 1, and the read width pointer is updated to 0 after incrementing by 20.

[0033] After the above process is repeated, we get:

[0034] After every 30 bits of read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 20, and after counting to 10, it loops back to 0, that is, modulo 30 addition.

[0035] Preferably, the write data bit width of the Gearbox module is 33 bits, the write clock frequency is 312.5 MHz, the read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625 MHz;

[0036] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0037] To facilitate read operations, the width of the data FIFO component is set to 30 bits.

[0038] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode:

[0039] 1) During the data writing process of the Gearbox module:

[0040] After every 32 groups of 33-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all 1 in step, and after counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer is also incremented by 1 in step, and after counting to 31, it loops back to 0, i.e., modulo 32 addition.

[0041] 2) During the data reading process of the Gearbox module:

[0042] After every two groups of 16-bit read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16, and after counting to 16, it loops back to 0, that is, modulo 32 addition.

[0043] Preferably, the write data bit width of the Gearbox module is 33 bits, the write clock frequency is 312.5 MHz, the read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125 MHz;

[0044] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0045] To facilitate read operations, the width of the data FIFO component is set to 32 bits.

[0046] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode:

[0047] 1) During the data writing process of the Gearbox module:

[0048] After every ten groups of 66-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all in steps of 1. After counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer is also incremented by 6. After counting to 54, it loops back to 0, i.e., modulo 60 addition.

[0049] 2) During the data reading process of the Gearbox module:

[0050] After every three groups of 20-bit read data are read from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented by 20, and after counting to 40, it loops back to 0, that is, modulo 60 addition.

[0051] Preferably, the write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25 MHz, the read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625 MHz;

[0052] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0053] To facilitate read operations, the width of the data FIFO component is set to 60 bits.

[0054] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode:

[0055] 1) During the data writing process of the Gearbox module:

[0056] After every 32 groups of 66-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all in steps of 1. After counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer is also incremented by 2. After counting to 62, it loops back to 0, i.e., modulo 64 addition.

[0057] 2) During the data reading process of the Gearbox module:

[0058] After every four groups of 16-bit read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 16, and after counting to 48, it loops back to 0, that is, modulo 64 addition.

[0059] Preferably, the write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25 MHz, the read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125 MHz;

[0060] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0061] To facilitate read operations, the width of the data FIFO component is set to 64 bits.

[0062] (3) Beneficial effects

[0063] Compared with the existing technology, the Ethernet 10GBASE-R PCS Gearbox module provided by the present invention is a flexible and universal Gearbox module designed based on a FIFO structure with two-dimensional read and write pointers. It supports converting 33 bits × 312.5MHz or 66 bits × 156.25MHz mode to 16 bits × 644.53125MHz or 20 bits × 515.625MHz mode, and realizes seamless connection between the internal data bus of the Ethernet 10GBASE-R PCS and the data interface of the physical medium attachment sublayer (PMA). BRIEF DESCRIPTION OF THE DRAWINGS

[0064] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0065] Figure 1 Schematic diagram of the hardware structure of the present invention;

[0066] Figure 2 This is a schematic diagram of the data writing process of the Gearbox module when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode;

[0067] Figure 3 This is a schematic diagram of the data reading process of the Gearbox module when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode;

[0068] Figure 4 This is a schematic diagram of the architecture location of the existing physical coding sublayer 10GBASE-RPCS;

[0069] Figure 5 This figure shows the hardware structure of the existing physical coding sublayer 10GBASE-R PCS data transmission. DETAILED DESCRIPTION

[0070] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0071] Ethernet 10GBASE-R PCS Gearbox module, such as Figure 1 As shown, it includes a write depth pointer generation component, a write width pointer generation component, a write data control component and a data FIFO component located in the write clock domain, and a read depth pointer generation component, a read width pointer generation component and a read data control component located in the read clock domain;

[0072] A write depth pointer generating component, configured to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component;

[0073] A write width pointer generating component, configured to generate a write width pointer pointing to a horizontal bit position where write data is written in the data FIFO component;

[0074] The write data control component writes the write data into the data FIFO component according to the write start bit position pointed to by the write depth pointer and the write width pointer;

[0075] Data FIFO component, used to store data;

[0076] A read depth pointer generating component, used for generating a read depth pointer pointing to a longitudinal position of read data read from the data FIFO component;

[0077] a read width pointer generating component, for generating a read width pointer pointing to a horizontal bit position of read data read from the data FIFO component;

[0078] The read data control component reads and stores the read data from the data FIFO component according to the read start bit position pointed to by the read depth pointer and the read width pointer;

[0079] Among them, the write clock domain and the read clock domain have the same origin.

[0080] ①33bits×312.5MHz mode converted to 20bits×515.625MHz mode

[0081] like Figure 2 As shown in the figure, when the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data writing process of the gearbox module includes:

[0082] In the initial state, the write start bit position is Cycle0 (0, 0), the write depth pointer and the write width pointer are both 0, and the data FIFO component is empty;

[0083] Cycle1(1,3) is the write start bit position after the first group of 33 bits of write data is written to the data FIFO component. At this time, the write depth pointer is updated to 1 after incrementing by 1, and the write width pointer is updated to 3 after incrementing by 3.

[0084] Cycle2(2,6) is the write start bit position after the second group of 33 bits of write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 2, and the write width pointer is incremented by 3 and updated to 6.

[0085] After the ninth group of 33-bit write data is written into the data FIFO component, Cycle9(3,27) is the write start bit position of the tenth group of 33-bit write data into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 3, and the write width pointer is incremented by 3 and updated to 27.

[0086] Cycle10(5,0) is the write start bit position after the tenth group of 33-bit write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 2 and updated to 5, and the write width pointer is incremented by 3 and updated to 0.

[0087] Cycle11(0,3) is the write start bit position after the eleventh group of 33-bit write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 0, and the write width pointer is incremented by 3 and updated to 3.

[0088] After the above process is repeated, we get:

[0089] After every ten groups of 33-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1. After counting to 5, it loops back to 0, that is, modulo 6 addition, (5+1)mod6=0; the write width pointer is incremented by 3, and after counting to 27, it loops back to 0, that is, modulo 30 addition, (27+3)mod30=0.

[0090] like Figure 3 As shown in the figure, when the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data reading process of the gearbox module includes:

[0091] In the initial state, the read start bit position is Cycle0 (0, 0), the read depth pointer and the write width pointer are both 0, and the data FIFO component stores data;

[0092] Cycle1(0,20) is the read start bit position after the first group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer remains unchanged and remains at 0. The read width pointer is updated to 20 after adding 20.

[0093] Cycle2(1,10) is the read start bit position after the second group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 1 after incrementing by 1, and the read width pointer is updated to 10 after incrementing by 20.

[0094] Cycle3(2,0) is the read start bit position after the third group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 2 after incrementing by 1, and the read width pointer is updated to 0 after incrementing by 20.

[0095] After the above process is repeated, we get:

[0096] After every 30 bits of read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition, (5+1)mod6=0; the read width pointer is incremented in steps of 20, and after counting to 10, it loops back to 0, that is, modulo 30 addition, (10+20)mod30=0.

[0097] The write data bit width of the Gearbox module is 33 bits, the write clock frequency is 312.5 MHz, and the read data bit width of the Gearbox module is 20 bits, the read clock frequency is 515.625 MHz.

[0098] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0099] To facilitate read operations, the width of the data FIFO component is set to 30 bits.

[0100] ②33bits×312.5MHz mode converted to 16bits×644.53125MHz mode

[0101] When the internal data bus of the 10GBASE-R PCS physical coding sublayer is in 33 bits × 312.5 MHz mode and the data interface of the PMA physical medium attachment sublayer is in 16 bits × 644.53125 MHz mode:

[0102] 1) During the data writing process of the Gearbox module:

[0103] After every 32 groups of 33-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all 1 in step, and after counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer is also incremented by 1 in step, and after counting to 31, it loops back to 0, i.e., modulo 32 addition.

[0104] 2) During the data reading process of the Gearbox module:

[0105] After every two groups of 16-bit read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16, and after counting to 16, it loops back to 0, that is, modulo 32 addition.

[0106] The write data bit width of the Gearbox module is 33 bits, the write clock frequency is 312.5 MHz, and the read data bit width of the Gearbox module is 16 bits, the read clock frequency is 644.53125 MHz.

[0107] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0108] To facilitate read operations, the width of the data FIFO component is set to 32 bits.

[0109] ③66bits×156.25MHz mode converted to 20bits×515.625MHz mode

[0110] When the internal data bus of the 10GBASE-R PCS physical coding sublayer is in 66-bit × 156.25 MHz mode and the data interface of the PMA physical medium attachment sublayer is in 20-bit × 515.625 MHz mode:

[0111] 1) During the data writing process of the Gearbox module:

[0112] After every ten groups of 66-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all in steps of 1. After counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer is also incremented by 6. After counting to 54, it loops back to 0, i.e., modulo 60 addition.

[0113] 2) During the data reading process of the Gearbox module:

[0114] After every three groups of 20-bit read data are read from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented by 20, and after counting to 40, it loops back to 0, that is, modulo 60 addition.

[0115] The write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25 MHz, and the read data bit width of the Gearbox module is 20 bits, the read clock frequency is 515.625 MHz.

[0116] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0117] To facilitate read operations, the width of the data FIFO component is set to 60 bits.

[0118] ④66bits×156.25MHz mode converted to 16bits×644.53125MHz mode

[0119] When the internal data bus of the 10GBASE-R PCS physical coding sublayer is in 66-bit × 156.25 MHz mode and the data interface of the PMA physical medium attachment sublayer is in 16-bit × 644.53125 MHz mode:

[0120] 1) During the data writing process of the Gearbox module:

[0121] After every 32 groups of 66-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all in steps of 1. After counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer is also incremented by 2. After counting to 62, it loops back to 0, i.e., modulo 64 addition.

[0122] 2) During the data reading process of the Gearbox module:

[0123] After every four groups of 16-bit read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 16, and after counting to 48, it loops back to 0, that is, modulo 64 addition.

[0124] The write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25 MHz, and the read data bit width of the Gearbox module is 16 bits, the read clock frequency is 644.53125 MHz.

[0125] To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6.

[0126] To facilitate read operations, the width of the data FIFO component is set to 64 bits.

[0127] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. Ethernet 10GBASE-RPCS Gearbox module, featuring: It includes a write depth pointer generation component, a write width pointer generation component, a write data control component and a data FIFO component located in the write clock domain, and a read depth pointer generation component, a read width pointer generation component and a read data control component located in the read clock domain; A write depth pointer generating component, configured to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component; A write width pointer generating component, configured to generate a write width pointer pointing to a horizontal bit position where write data is written in the data FIFO component; The write data control component writes the write data into the data FIFO component according to the write start bit position pointed to by the write depth pointer and the write width pointer; Data FIFO component, used to store data; A read depth pointer generating component, used for generating a read depth pointer pointing to a longitudinal position of read data read from the data FIFO component; a read width pointer generating component, for generating a read width pointer pointing to a horizontal bit position of read data read from the data FIFO component; The read data control component reads and stores the read data from the data FIFO component according to the read start bit position pointed to by the read depth pointer and the read width pointer; Among them, the write clock domain and the read clock domain have the same origin.

2. The Ethernet 10GBASE-RPCS Gearbox module according to claim 1, wherein: When the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data writing process of the gearbox module includes: In the initial state, the write start bit position is Cycle0 (0, 0), the write depth pointer and the write width pointer are both 0, and the data FIFO component is empty; Cycle1(1,3) is the write start bit position after the first group of 33 bits of write data is written to the data FIFO component. At this time, the write depth pointer is updated to 1 after incrementing by 1, and the write width pointer is updated to 3 after incrementing by 3. Cycle2(2,6) is the write start bit position after the second group of 33 bits of write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 2, and the write width pointer is incremented by 3 and updated to 6. After the ninth group of 33-bit write data is written into the data FIFO component, Cycle9(3,27) is the write start bit position of the tenth group of 33-bit write data into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 3, and the write width pointer is incremented by 3 and updated to 27. Cycle10(5,0) is the write start bit position after the tenth group of 33-bit write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 2 and updated to 5, and the write width pointer is incremented by 3 and updated to 0. Cycle11(0,3) is the write start bit position after the eleventh group of 33-bit write data is written to the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 0, and the write width pointer is incremented by 3 and updated to 3. After the above process is repeated, we get: After every ten groups of 33-bit write data are written to the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all in steps of 1. After counting to 5, it loops back to 0, that is, modulo 6 addition. The write width pointer is incremented by 3. After counting to 27, it loops back to 0, that is, modulo 30 addition.

3. The Ethernet 10GBASE-RPCS Gearbox module according to claim 2, wherein: When the internal data bus of the 10GBASE-RPCS physical coding sublayer operates in 33 bits × 312.5 MHz mode and the data interface of the PMA physical medium attachment sublayer operates in 20 bits × 515.625 MHz mode, the Gearbox module's data reading process includes the following: In the initial state, the read start bit position is Cycle0 (0, 0), the read depth pointer and the write width pointer are both 0, and the data FIFO component stores data; Cycle1(0,20) is the read start bit position after the first group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer remains unchanged and remains at 0. The read width pointer is updated to 20 after adding 20. Cycle2(1,10) is the read start bit position after the second group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 1 after incrementing by 1, and the read width pointer is updated to 10 after incrementing by 20. Cycle3(2,0) is the read start bit position after the third group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 2 after incrementing by 1, and the read width pointer is updated to 0 after incrementing by 20. After the above process is repeated, we get: After every 30 bits of read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 20, and after counting to 10, it loops back to 0, that is, modulo 30 addition.

4. The Ethernet 10GBASE-RPCS Gearbox module according to claim 3, wherein: The write data bit width of the Gearbox module is 33 bits, and the write clock frequency is 312.5 MHz. The read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625 MHz. To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 30 bits.

5. The Ethernet 10GBASE-RPCS Gearbox module according to claim 3, wherein: When the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode: 1) During the data writing process of the Gearbox module: After every 32 groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2. The remaining increment steps are all 1, and after counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer increments by 1, and after counting to 31, it loops back to 0, i.e., modulo 32 addition. 2) During the data reading process of the Gearbox module: After every two groups of 16-bit read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16, and after counting to 16, it loops back to 0, that is, modulo 32 addition.

6. The Ethernet 10GBASE-R PCS Gearbox module according to claim 5, wherein: The write data bit width of the Gearbox module is 33 bits, and the write clock frequency is 312.5 MHz. The read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125 MHz. To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 32 bits.

7. The Ethernet 10GBASE-R PCS Gearbox module according to claim 3, wherein: When the internal data bus of the 10GBASE-R PCS physical coding sublayer is in 66-bit × 156.25 MHz mode and the data interface of the PMA physical medium attachment sublayer is in 20-bit × 515.625 MHz mode: 1) During the data writing process of the Gearbox module: After every ten groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2. The remaining increments are all incremented by 1. After counting to 5, it loops back to 0, i.e., modulo 6 addition. The increment step of the write width pointer is 6, and after counting to 54, it loops back to 0, i.e., modulo 60 addition; 2) During the data reading process of the Gearbox module: After every three groups of 20-bit read data are read from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented by 20, and after counting to 40, it loops back to 0, that is, modulo 60 addition.

8. The Ethernet 10GBASE-R PCS Gearbox module according to claim 7, wherein: The write data bit width of the Gearbox module is 66 bits, and the write clock frequency is 156.25 MHz. The read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625 MHz. To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 60 bits.

9. The Ethernet 10GBASE-R PCS Gearbox module according to claim 3, wherein: When the internal data bus of the 10GBASE-R PCS physical coding sublayer is in 66-bit × 156.25 MHz mode and the data interface of the PMA physical medium attachment sublayer is in 16-bit × 644.53125 MHz mode: 1) During the data writing process of the Gearbox module: After every 32 groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2. The remaining increment steps are all 1, and after counting to 5, it loops back to 0, i.e., modulo 6 addition. The write width pointer increments in steps of 2, and after counting to 62, it loops back to 0, i.e., modulo 64 addition. 2) During the data reading process of the Gearbox module: After every four groups of 16-bit read data are read out of the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 16, and after counting to 48, it loops back to 0, that is, modulo 64 addition.

10. The Ethernet 10GBASE-R PCS Gearbox module according to claim 9, wherein: The write data bit width of the Gearbox module is 66 bits, and the write clock frequency is 156.25 MHz. The read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125 MHz. To prevent overflow, the distance between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading begins, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 64 bits.

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