Partial differential equation solving accelerator and data processing method

Abstract

The invention discloses a partial differential equation solving accelerator and a data processing method, and belongs to the technical field of data processing. The decompressor obtains and decompresses the data blocks from the off-chip memory; the compressor compresses the processed data and stores the compressed data back to the off-chip memory; the on-chip SRAM works in a double-buffer mode and stores decoding data blocks of the data decompressor; the two-dimensional processing unit array comprises a fixed-point difference engine, a floating-point derivative processing unit and an addition unit, and is used for sequentially reading slice vectors in the blocks, processing data, calculating first-order and second-order derivatives, comparing vector values with previous values, and extracting related mantissa slices from the grid register; the data sensing controller controls the whole processing flow; the temporary value buffer area is used for storing the temporary calculation result, and all the processing unit arrays can completely access the stored content. According to the method, the efficiency, the flexibility and the resource utilization rate of PDE solving are improved, and powerful support is provided for scientific research and technical application in multiple fields.

Description

Technical Field

[0001] The invention proposes a partial differential equation solving accelerator and a data processing method, belonging to the technical field of data processing. Background Art

[0002] Finite difference method (FDM) is widely used to solve partial differential equations (PDEs), where both the spatial domain and the time interval are discretized. When running a PDE solver, the main bottleneck is processing and computing the large amount of high-precision data generated by the discretization. Existing scientific computing libraries usually store the discrete grid point data in DRAM by default in each iteration step. In each step, the PDE solver mainly performs template calculations with low computational density. Although compression algorithms can effectively reduce the volume of data storage and transmission, they bring too much additional overhead. Some software libraries or accelerators introduce mixed precision calculations to reduce overhead, but lack specialized optimization for PDE solver data flow. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention proposes a partial differential equation solving accelerator and a data processing method. The PDE solving accelerator of the present invention improves the efficiency, flexibility and resource utilization of PDE solving by optimizing hardware design, providing strong support for scientific research and technological applications in multiple fields.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: In a first aspect, the present invention provides a partial differential equation solving accelerator, comprising: A decompressor for obtaining and decompressing data blocks from an off-chip memory; A compressor, used to compress the processed data and store it back into the off-chip memory; On-chip SRAM memory for storing data blocks decoded by the data decompressor in double buffer mode; Two-dimensional processing unit array: including fixed-point differential engine, floating-point derivative processing unit and addition unit, used to sequentially read the slice vectors in the block, process the data and calculate the first and second order derivatives, compare the vector value with the previous value, extract the relevant mantissa slice from the grid register; vector sum calculation, and obtain the updated data block; A data-aware controller that extracts the relevant mantissa slices from the grid registers and controls the entire processing flow; Temporary value buffer, used to store temporary calculation results, all processing unit arrays can fully access its storage content.

[0005] As a further improvement of the present invention, it also includes: a shared cache, which is used to cache overlapping data during the calculation process.

[0006] As a further improvement of the present invention, the data decompressor, the compressor and the two-dimensional processing unit array are arranged in multiple groups to form a plurality of independent computing units for processing a plurality of block data simultaneously.

[0007] As a further improvement of the present invention, the decompressor and the compressor are connected to an off-chip memory via a bus system.

[0008] As a further improvement of the present invention, the data compression method of the compressor comprises: The original floating point data is decomposed into sign, exponent and mantissa parts; The 1-bit symbol data is grouped into a bit chain and shortened using fixed-length run-length coding; then all the index values ​​in the matrix are aggregated and Huffman coding is applied to generate the Huffman tree of the block and the encoded index string; For the mantissa, the decimal part in the vector is normalized with the first exponent as reference; the first mantissa is used as a reference number, and the incremental compression method is used to subtract each number at position i from the number at the previous position i-1.

[0009] As a further improvement of the present invention, the compressor includes a Huffman decoder, a run-length decoder and a mantissa adder, and processes off-chip data in blocks.

[0010] As a further improvement of the present invention, the decompressor is used to record and count the frequency of exponential values ​​in each input vector, and insert the frequency of exponential values ​​into a frequency table; an exponential symbol module caches the input exponent; after transmitting the block information, the encoder constructs a Huffman tree and outputs an exponential bit stream.

[0011] As a further improvement of the present invention, the two-dimensional processing unit array is specifically used for: Perform mantissa extraction and multiplication based on the grid point difference value; divide the mantissa data into multiple 8-bit slices; set up a unified base index eb within the block, and align the mantissa values ​​of other data according to the base index; First, the difference is extracted, and then these slices are multiplied by the differential constant in the equation in fixed-point form; then, the product results are added in fixed-point form to form the template difference component; The template differential components are multiplied by the physical constants and added to generate a complete floating point representation; the exponent portion of the floating point representation value is then compared with the original u value to determine the affected mantissa slice and whether to update the base exponent; The fixed-point differential engine consists of 8 columns, 4 rows and 3 channels of fixed-point processing units; each decompressed data block, once stored in the on-chip memory, is subdivided into 8 small blocks, each of which is further processed by 24 fixed-point processing units; Each processing unit contains two registers for storing differential coefficient constants along the x and y dimensions respectively; each processing unit has four 8-bit fixed-point inputs for selecting input values ​​for calculation; The processing unit is also used to receive a 16-bit mantissa slice from the previous channel and store it in Ox1 and 0y1. Two multipliers calculate the product of the grid point in the x and y dimensions with the equation constant in one cycle; then the two results are passed to the adder and added to the original summation result; the fixed-point calculation unit within the processing unit row consists of 8 columns and 3 units; the number of channels is set to 3, and the differences are divided into multiple groups, and the three coefficients are input separately.

[0012] In a second aspect, the present invention provides a data processing method based on the partial differential equation solving accelerator, comprising: a) Using a time-blocking strategy, a data block of size n is obtained from off-chip storage in each iteration; c) decomposing the floating point number into three parts: a sign, an exponent and a mantissa, and compressing the three parts respectively according to the characteristics of the data block; d) In the template calculation, the integer coefficients of the finite difference are processed separately from the floating-point coefficients in the physical equations, where an n-th order finite difference calculation along one dimension is converted into n fixed-point operations followed by a floating-point operation; e) during on-chip data extraction, the mantissa of the floating-point value is sliced, and by predicting the data flow during iterations, only those slices whose mantissa has changed are selected for calculation; b) After k iterations, storing the updated data block back to the off-chip storage.

[0013] As a further improvement of the present invention, the fixed-point operation comprises the following steps: The entire block is divided into multiple sub-blocks along its diagonal, and each row is responsible for processing the data of one sub-block; Mark the first element position of each input and output vector as 0, assuming that the i-th row is input in the 0th cycle, and the operation related to the i-th row is completed in the m-th cycle; the 0th cycle first calculates the product of ui and k3 to obtain the partial sum of u(i+1) in the x dimension, recorded as ux(i+1); in the 1st cycle, ui is passed to the w3 part in the processing unit of channel\#0 and the K2 part in the processing unit of channel\#1 to calculate uy(i+1) and ux(i); ux(i+1) is cached in the register Ox2 of the second channel, waiting for u(i+1) to be transferred to the second processing unit for recalculation in the second cycle; adjacent registers along the channel dimension store the grid points of the same row in the m-th cycle; the two-dimensional processing unit array of channel 0 simultaneously outputs the ux of the i-th row and the uy of the (i+1)-th row to the multipliers of the x-dimension and y-dimension, and multiplies them with the physical constants; Each output point needs to perform m-1 multiplication operations in the x dimension and m-1 addition operations in the y dimension; and one output point undergoes m cycles of data transmission processing in the two-dimensional processing unit array.

[0014] The beneficial effects of the present invention compared with the prior art are as follows: The partial differential equation (PDE) solving accelerator of the present invention is designed to efficiently handle the solving process of PDE through a series of optimized hardware components. A specially designed hardware accelerator to improve the efficiency of PDE solving. The decompressor takes the compressed data block from the off-chip memory (such as DDR or HBM) and decompresses it for subsequent processing. This helps to reduce the time and bandwidth required for data transmission. The data processed by the compressor is compressed and stored back to the off-chip memory to save storage space and improve data transmission efficiency. The on-chip SRAM memory (double buffer mode) is used to store the data blocks decoded from the decompressor. The double buffer mode allows the next data block to be preloaded while the current data block is being processed, thereby reducing waiting time. In the two-dimensional processing unit array, the fixed-point difference engine is used to calculate the first and second order derivatives of the data, which is a key step in PDE solving. The floating-point derivative processing unit processes the derivatives that need to be calculated with high precision. The addition unit performs calculations such as vector summation to update the data block. The array can sequentially read the slice vectors in the block, process the data, and compare the vector value with the previous value, extract the relevant mantissa slices from the grid register, and thus obtain the updated data block. The data-aware controller is responsible for extracting the relevant mantissa slices from the grid register and controlling the entire processing flow as needed. This ensures the correct processing of data and the efficient execution of the process. The temporary value buffer stores temporary calculation results, and all processing unit arrays can fully access its contents. This helps to avoid repeated calculations and improve processing efficiency. Through specially designed hardware components such as fixed-point difference engines and floating-point derivative processing units, the accelerator can efficiently process key calculation steps in PDE solving. The processing unit array can handle different types of data and computing tasks and is suitable for a variety of PDE solving scenarios. The data compression and decompression functions reduce the use of off-chip memory, while the double buffering mode of the on-chip SRAM reduces waiting time and improves resource utilization. The accelerator design allows expansion as needed to handle larger-scale data and more complex computing tasks. The PDE solving accelerator of the present invention improves the efficiency, flexibility and resource utilization of PDE solving by optimizing the hardware design, providing strong support for scientific research and technological applications in multiple fields.

[0015] The present invention proposes a new data compression method, which can effectively improve the compression rate of data by subdividing a data block into multiple small blocks and utilizing the redundant information between these small blocks. The effect of the present invention is particularly obvious for blocks containing a large amount of identical or similar data. In addition, the method of the present invention can also effectively process large-scale data, thereby reducing computational complexity and storage overhead. The method of the present invention can not only process integer data, but also floating-point data. Since the data compression method of the present invention is efficient and flexible, it can be applied to various different fields, such as image processing, audio processing, large data storage and transmission, etc. In addition, since the method of the present invention can be implemented in hardware and software, its application prospects are very broad. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is the overall computing architecture diagram of the present invention; Figure 2 It is a schematic diagram of the data handling compression algorithm of the present invention; Figure 3 It is a schematic diagram of the data compression and decompression module architecture of the present invention; Figure 4 is a mixed precision calculation flow chart of the present invention; Figure 5 It is a design diagram of a fixed-point arithmetic unit of the present invention; Figure 6 It is a schematic diagram of the operation data flow of the present invention. DETAILED DESCRIPTION

[0018] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0019] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0020] Explanation of relevant terms Off-chip HBM2 (High Bandwidth Memory 2nd Generation) refers to a memory solution that uses HBM2 technology outside the chip. HBM2 is a high-performance memory interface standard that achieves higher data transmission bandwidth and lower power consumption by 3D stacking DRAM (dynamic random access memory) chips.

[0021] DDR is the abbreviation of Double Data Rate, which means "double data rate". It is a memory technology used in the computer field. It is improved on the basis of the original synchronous dynamic random access memory (SDRAM).

[0022] HBM is the abbreviation of High Bandwidth Memory. It is a high-performance DRAM based on 3D stacking process and is suitable for applications with high memory bandwidth requirements.

[0023] SRAM is the abbreviation of Static Random Access Memory, which is static random access memory.

[0024] A partial differential equation (PDE) is an equation that describes the relationship between an unknown function that depends on multiple variables (such as space and time) and its partial derivatives.

[0025] Finite Difference Method (FDM) is an approximate method for finding numerical solutions to differential equations.

[0026] Floating-point numbers are composed of a mantissa and an exponent. By adjusting the exponent and mantissa, values ​​of different sizes and precisions can be represented. Floating-point decomposition usually refers to the process of decomposing a floating-point number into a mantissa and an exponent, which is a basic way to process floating-point numbers inside a computer.

[0027] Processing Element (PE) and FP Grid are two common terms in the field of computer science and engineering. They are explained below: A processing element (PE) is a basic computing unit in a computer system that is responsible for executing instructions, processing data, and performing various arithmetic and logical operations. When processing large-scale data and complex computing tasks, the processing unit plays a vital role.

[0028] FP grid usually refers to a grid structure that uses floating point (FP) numbers to represent data. In computer science, floating point numbers are a data type used to represent numerical values ​​with a decimal part.

[0029] In the field of modern computer science and signal processing, data compression technology has become an indispensable part. With the rise of big data and cloud computing, the storage and transmission of massive data have become increasingly important. Data compression technology can effectively reduce the storage space and transmission time of data and improve the efficiency of data processing. At the same time, in the field of signal processing, especially in image and audio processing, data compression technology also plays an important role. Existing data compression technologies mainly include lossy compression and lossless compression. Lossy compression technology reduces the size of data by discarding part of the data, which is suitable for application scenarios with low requirements on perceptual quality such as images and audio. Lossless compression technology reduces data redundancy through efficient encoding methods, which is suitable for application scenarios with high requirements on data quality. In lossless compression technology, Huffman coding is a commonly used method. It constructs a Huffman tree by counting the frequency of occurrence of each symbol in the statistics, and then uses the path length in the tree to represent the symbol, thereby achieving efficient encoding. In addition, there are many other lossless compression algorithms, such as Huffman coding, LZW coding, Bzip2 coding, etc. However, the existing data compression technology is not ideal when facing some specific data sets. For example, for some blocks containing a large amount of identical or similar data, existing compression algorithms cannot effectively utilize this redundant information, and thus cannot achieve a high compression rate. In addition, when existing compression algorithms process large-scale data, computational complexity and storage overhead also become a problem. In addition, existing data compression technologies also have some problems when processing floating-point data. Floating-point data is very common in scientific computing and engineering applications, but due to its complex format, existing compression algorithms often cannot achieve a low compression rate when processing floating-point data.

[0030] The present invention mainly adopts the following technical means: 1. Data block compression technology: The present invention uses Huffman coding, run-length coding and mantissa addition to effectively compress blocks containing a large amount of identical or similar data, thereby achieving a high compression rate. In specific implementation, the input data block can be first counted and analyzed to determine the distribution characteristics of the data, and then a Huffman tree is constructed based on these characteristics to generate a corresponding index bit stream, thereby achieving data compression.

[0031] 2. Floating-point data compression technology: The present invention uses bit slicing calculation method and fixed-point differential engine and other technologies to effectively compress floating-point data, thereby improving the compression rate. In specific implementation, the floating-point data can be first converted into fixed-point form, and then the fixed-point data can be sliced ​​to extract the mantissa value, and then the mantissa values ​​are fixed-point multiplication and addition operations are performed on these mantissa values ​​to generate compressed data.

[0032] 3. Data distortion control technology: The present invention adopts technologies such as benchmark index caching and index updating to reduce data distortion and ensure data quality during data compression. In specific implementation, a unified benchmark index can be set first, and then the benchmark index can be cached and updated according to the index value of the input data, thereby ensuring the accuracy of the data compression process.

[0033] 4. Data universality and flexibility technology: The present invention adopts technologies such as modular design and parameter configuration to improve the universality and flexibility of data compression technology to adapt to different types of data and application scenarios. In specific implementation, a universal compression module can be designed first, and then the corresponding parameters can be configured according to different data types and application requirements, so as to realize the flexible application of data compression technology.

[0034] 5. Technology for reducing computational complexity and storage overhead: The present invention adopts technologies such as data block processing and parallel computing to reduce computational complexity and storage overhead in large-scale data processing. In specific implementation, the input data block can be divided into multiple small blocks, and then parallel computing technology is used to process each small block independently, thereby improving the efficiency of data processing.

[0035] The present invention is described in detail below: The first object of the present invention is to provide a partial differential equation solving accelerator, comprising: A decompressor for obtaining and decompressing data blocks from an off-chip memory; A compressor, used to compress the processed data and store it back into the off-chip memory; On-chip SRAM memory for storing data blocks decoded by the data decompressor in double buffer mode; Two-dimensional processing unit array: including fixed-point differential engine, floating-point derivative processing unit and addition unit, used to sequentially read the slice vectors in the block, process the data and calculate the first and second order derivatives, compare the vector value with the previous value, extract the relevant mantissa slice from the grid register; vector sum calculation, and obtain the updated data block; A data-aware controller that extracts the relevant mantissa slices from the grid registers and controls the entire processing flow; Temporary value buffer, used to store temporary calculation results, all processing unit arrays can fully access its storage content.

[0036] The partial differential equation solving accelerator can be used to optimize floating-point grid data, mixed precision representation of constant terms, and bit-slice differential calculations, including the following steps and components: a. Floating-point grid data compression: Decompose the floating-point number into sign, exponent, and mantissa; compress the sign, exponent, and mantissa parts separately according to the characteristics of the data block; obtain a data block of size n from the off-chip memory in each iteration, and store the updated data after k iterations; adopt a time-blocking strategy to improve memory throughput without expanding the physical bandwidth.

[0037] b. Mixed precision representation of constant terms: In the template calculation, the integer coefficients of the finite difference are processed separately from the floating-point coefficients in the physical equations; the n-th order finite difference calculation along one dimension is converted into n fixed-point operations, followed by a floating-point processing.

[0038] c. Bit-slice differential computation: Slice the mantissa of the floating-point value; compute only those slices where the mantissa changes by predicting the flow of data during iterations; and input the mantissa of the floating-point data in a sliced ​​fashion during on-chip data extraction.

[0039] As an example, the accelerator is mainly composed of the following modules: data decompressor / compressor, on-chip SRAM memory, two-dimensional processing element (PE) array, data-aware controller, and temporary value buffer. These modules work together to improve the processing efficiency of floating-point grid data. The functions of the main components are as follows: a. Data decompressor / compressor, which is used to obtain and decompress compressed data blocks from off-chip memory, and compress and store the processed data back to off-chip memory; Data decompressor / compressor, which is responsible for obtaining compressed data blocks from off-chip memory (such as HBM2) and compressing the data back to off-chip memory after processing. Principle: The decompressor uses a specific compression algorithm to decode the data and restore it to the original format for subsequent processing. The compressor recompresses the data using the same or compatible compression algorithm after the data is updated to reduce storage requirements and improve transmission efficiency.

[0040] b. On-chip SRAM memory is used to work in double buffer mode to maximize the bandwidth of off-chip memory; on-chip SRAM memory is used as temporary storage space inside the accelerator to store the data blocks being processed. Principle: On-chip SRAM adopts double buffer mode, that is, it maintains two data blocks at the same time (one is currently being processed and the other is ready to be processed). This design can maximize the bandwidth of HBM2 and reduce waiting time.

[0041] c. A two-dimensional processing element (PE) array, including a fixed-point difference engine, a floating-point derivative processing unit, and a final result addition unit, is used to process data and calculate first-order and second-order derivatives; a two-dimensional processing element (PE) array performs core processing tasks such as finite difference calculations and floating-point result summation. Principle: The PE array consists of multiple dedicated PE units, each of which is responsible for processing a portion of the data block. The PE unit contains a fixed-point difference engine, a floating-point derivative processing unit, and a final result addition unit. They work together to first perform fixed-point operations (such as finite difference calculations) and then perform floating-point operations (such as derivative calculations and summation). In addition, the PE array uses a sliced ​​method to input the mantissa part of the floating-point data to further reduce the amount of calculation.

[0042] d. Data-aware controller, which is used to extract relevant mantissa slices from the grid register and control the entire processing flow; the data-aware controller is responsible for controlling the data flow and processing flow of the entire accelerator. Principle: The data-aware controller schedules the work of each module according to the characteristics and processing requirements of the data block. It is also responsible for extracting relevant mantissa slices from the grid register to support the slice input method of the PE array. In addition, the controller also monitors the data flow during the iteration process to ensure that only those slices with changed mantissa parts are calculated.

[0043] e. Temporary value buffer, used to store temporary calculation results, all processing unit (PE) arrays can fully access its storage content. Temporary value buffer, stores temporary calculation results during processing. Principle: Temporary value buffer provides storage space for intermediate results for PE arrays. Since all PE arrays can fully access the storage content of this buffer, data can be easily shared between different PE units. This helps speed up the processing process and reduce data transmission delays.

[0044] f. Shared cache, used to cache overlapping data during the computation process to prevent redundant off-chip reads. It can process multiple blocks of data simultaneously to improve computational efficiency.

[0045] Furthermore, the workflow of the above scheme is as follows: Read the compressed data block Ut from the off-chip HBM2 memory.

[0046] The data decompressor decodes the data blocks and stores them in the on-chip SRAM.

[0047] The data-aware controller fetches a matrix from the temporary value buffer and schedules the PE array to start processing the data.

[0048] The PE array sequentially reads the slice vectors in the block, computing the first and second order derivatives.

[0049] Comparing the vector value with the previous value, the data-aware controller extracts the relevant mantissa slice from the grid register.

[0050] The vector sum module performs the final calculation and obtains the updated data block.

[0051] The data compressor compresses the updated data block and stores it back in the off-chip HBM2 memory.

[0052] Through the collaborative work of the above modules, the accelerator can improve memory throughput without expanding physical bandwidth, and effectively support optimization technologies such as compression of floating-point grid data, mixed precision representation, and bit slice differential calculation. The present invention proposes three optimization technologies based on numerical similarity: floating-point grid data compression, mixed precision representation of constant terms, and bit slice differential calculation.

[0053] FP grid compression aims to improve memory throughput without expanding physical bandwidth. The present invention uses time blocking. In each iteration, a data block of size n is obtained from outside the chip, and the updated data is stored after k iterations. The present invention decomposes the floating point number into a sign, an exponent, and a mantissa, and compresses each part separately according to the characteristics of the data block. In the template calculation, the present invention processes the integer coefficients of the finite difference separately from the floating point coefficients in the physical equation. The n-order finite difference calculation along one dimension is converted into n fixed-point operations, followed by a floating-point processing. During the on-chip data extraction process, the present invention slices the mantissa part of the floating point value. By predicting the data flow during the iteration, only those slices whose mantissa part changes are involved in the calculation.

[0054] A second object of the present invention is to provide a data processing method based on the partial differential equation solving accelerator, comprising: a) Using a time-blocking strategy, a data block of size n is obtained from off-chip storage in each iteration; c) decomposing the floating point number into three parts: a sign, an exponent and a mantissa, and compressing the three parts respectively according to the characteristics of the data block; d) In the template calculation, the integer coefficients of the finite difference are processed separately from the floating-point coefficients in the physical equations, where an n-th order finite difference calculation along one dimension is converted into n fixed-point operations followed by a floating-point operation; e) during on-chip data extraction, the mantissa of the floating-point value is sliced, and by predicting the data flow during iterations, only those slices whose mantissa has changed are selected for calculation; b) after k iterations, storing the updated data block back to the off-chip storage; To this end, the present invention designs a numerical similarity-aware acceleration circuit for solving partial differential equations to support the above mechanism. First, the accelerator considers the block characteristics of one-dimensional and two-dimensional grid data and defines an on-chip compressed data storage format based on block units. On this basis, compressors and decompressors are deployed to improve the effective off-chip bandwidth. The processing unit (PE) array of the accelerator also uses dedicated PE units to perform fixed-point finite difference calculations and sum floating-point results. The entire PE array uses a slice method to input the mantissa part of the floating-point data, and the exponent acts as a control flow to affect the final rounding operation. Finally, in order to prevent redundant off-chip reads, VSAP designs a shared cache for caching overlapping data during the calculation process.

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] An overview of the accelerator is as follows Figure 1 As shown in the figure. It mainly includes the following modules: data decompressor / compressor, on-chip SRAM memory, two-dimensional processing element (PE) array, data-aware controller, and temporary value buffer. Except for the temporary value buffer, each module is replicated to form 32 independent computing units, so that the accelerator can process multiple block data at the same time. The off-chip HBM2 memory is connected to the decompressor and compressor through a bus system. All processing element (PE) arrays can fully access the storage content of the temporary value buffer.

[0057] A single HBM2 read can update the numerical solution from t to t+k. First, the decompression module fetches and decompresses the compressed block Ut from off-chip memory. The on-chip SRAM operates in double-buffered mode to maximize the bandwidth of HBM2. At the same time, the controller fetches a matrix from the temporary value buffer. At the same time, the two-dimensional PE array, including a fixed-point difference engine, floating-point derivative processing unit, and final result addition unit, begins processing the data. The array sequentially reads the slice vectors in the block and calculates the first and second order derivatives. The vector numerical value is then compared with the previous value, and the data-aware controller extracts the relevant mantissa slice from the grid register. The vector summation module performs the final calculation, and after k iterations, the result is compressed and stored in the off-chip memory.

[0058] Figure 2The data compression method of the accelerator is presented. The present invention uses a block matrix operation of size M*N, which is called a compression block. The specific method includes: First, the original floating point data is decomposed into sign, exponent and mantissa parts. The 1-bit sign data is grouped into a bit chain and shortened using fixed-length run-length coding with an interval length of up to 16 bits. After that, all the exponent values ​​in the matrix are aggregated and Huffman coding is applied to generate the Huffman tree of the block and the encoded exponent string.

[0059] This allows for high compression rates under the assumption that the exponents are similar. For example, a block containing only two different exponent values ​​can be encoded as a simple bit stream of "0"s and "1". For the mantissa, the fractional part of the vector is normalized with respect to the first exponent. The first mantissa is used as a reference number. A delta compression approach is used where each number at position i is subtracted from the number at the previous position i-1, effectively compressing numerically similar mantissa values ​​and reducing the overall entropy.

[0060] Figure 3 (a) and Figure 3 (b) The corresponding compression module and decompression module design. The compressor includes a Huffman decoder, run-length decoder and mantissa adder to process off-chip data in blocks. The decompressor records and counts the frequency of exponent values ​​in each input vector and inserts these into the frequency table. An exponent sign module caches the input exponent. After transmitting the block information, the encoder builds the Huffman tree and outputs the exponent bit stream.

[0061] Figure 4 The flowchart of mixed precision operation using bit slice calculation method is shown. The method is also applicable to approximate calculation of double precision type. The present invention performs mantissa extraction and multiplication based on grid point difference value. The 23-bit mantissa data can be divided into three 8-bit slices. Within the block, a unified base index eb is established, which is usually set to the maximum exponent value. The mantissa values ​​of other data are aligned according to the base index.

[0062] The present invention first extracts the difference value, and then performs fixed-point multiplication operations on these slices and the differential constants in the equation. Next, the present invention adds the product results in fixed-point form to form the template difference component. This component sumx and sumy are further multiplied and added with the physical constant to generate a complete floating-point representation. The exponential part of this value is then compared with the original u value to determine the affected mantissa slice and decide whether to update the base index. The task of the entire fixed-point difference engine is to obtain three-dimensional difference values. The engine consists of 8 columns, 4 rows and 3 channels of fixed-point processing units (FP-PEs). Once each decompressed data block is stored in the on-chip memory, it is subdivided into 8 small blocks, each of which is further processed by 24 FP-PE units.

[0063] Figure 5 Three adjacent FP-PEs are shown. Each PE contains two registers Wh and Wk for storing differential coefficient constants along the x and y dimensions. Each PE has four 8-bit fixed-point inputs, and the correct value needs to be selected for calculation. The PE also receives a 16-bit slice of the mantissa from the previous channel and stores it in Ox1 and 0y1. Two multipliers within the PE calculate the product of the grid point in the x and y dimensions with the equation constant in one cycle. The two results are then passed to the adder and added to the original sum. The fixed-point calculation unit within the row consists of 8 columns of 3 units. The number of channels is set to 3 because the second-order partial derivatives are usually estimated by the first-order approximation of the three coefficients. If higher-order approximations are considered, the differences can be divided into multiple groups, with the three coefficients input separately.

[0064] Figure 6 The data flow of fixed-point operations is shown. The entire block is divided into multiple sub-blocks along its diagonal, and each row is responsible for processing the data of one sub-block. Due to the special blocking method, there are two cases for the number of input vectors inside the prismatic block: 8 or 7. The present invention marks the first element position of each input and output vector as 0. Assume that the i-th row is input in the 0th cycle, and the operation related to the i-th row is completed in the 4th cycle. The 0th cycle first calculates the product of ui and k3 to obtain the partial sum of u(i+1) in the x dimension, recorded as ux(i+1). In the 1st cycle, ui is passed to the w3 part in the PE of channel\#0 and the K2 part in the PE of channel\#1 to calculate uy(i+1) and ux(i). At this time, ux(i+1) is cached in the register Ox2 of the second channel, waiting for u(i+1) to be transferred to PE 2 for recalculation in the 2nd cycle. Adjacent registers along the channel dimension store grid points of the same row in the 4th cycle. The PE array of channel 0 simultaneously outputs the ux of the i-th row and the uy of the (i+1)-th row to the multipliers of the x-dimension and y-dimension, where they are multiplied by the physical constant. Each output point requires 3 multiplication operations in the x-dimension and 3 addition operations in the y-dimension. One output point undergoes 4 cycles of data transfer processing in the PE array.

[0065] Of course, the above method is only an example. As an extension, this embodiment can also be: each output point needs to perform m-1 multiplication operations in the x dimension and m-1 addition operations in the y dimension; and one output point undergoes m cycles of data transmission processing in the two-dimensional processing unit array.

[0066] This architecture can be used for solving partial differential equations based on the finite difference method, and improves the task processing speed while minimizing the loss of accuracy. The present invention selects three most advanced hardware: Intel Xeon 8260 CPU, NVIDIA A100 GPU and FDMAX PDE accelerator for comparison. When the CPU, GPU and FDMAX do not use the time-blocking optimization algorithm, the accelerator achieves an average acceleration of 23.2 times, 7.9 times and 3.2 times compared with the CPU, GPU and ASIC in four well-known PDE problems. When running the code using the time-blocking optimization algorithm, the accelerator still surpasses the GPU with similar memory bandwidth with an acceleration performance of 3.2 times.

[0067] The present invention can be widely used in application fields such as data processing, signal processing and computer science. First, in the field of data processing, the present invention can effectively solve the problems of computational complexity and storage overhead of existing data compression technology when processing large-scale data. By performing post-compression processing and block storage on the data, the storage space and transmission time of the data can be greatly reduced, and the efficiency of data processing can be improved. In addition, since the present invention can effectively utilize the redundant information in the data, a higher compression rate can be achieved, which is of great significance for fields that require high-precision data processing, such as medical imaging, financial data, etc. Secondly, in the field of signal processing, the present invention can effectively solve the problem that the existing data compression technology cannot achieve a lower compression rate when processing floating-point data. By performing post-compression processing and block storage on the floating-point data, the redundancy of the data can be effectively reduced, thereby achieving a higher compression rate. This has important application value for fields that require efficient storage and transmission of signal data, such as audio processing, video processing, etc. Finally, in the field of computer science, the present invention can provide an efficient data processing method, which has important practical value for researchers and developers who need to process large amounts of data. In addition, since the implementation of the present invention relies on hardware acceleration, the efficiency of data processing can be greatly improved, which has important application prospects for researchers and developers who need to process data in real time.

[0068] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0069] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A partial differential equation solving accelerator, characterized in that: include: A decompressor for obtaining and decompressing data blocks from an off-chip memory; A compressor, used to compress the processed data and store it back into the off-chip memory; On-chip SRAM memory for storing data blocks decoded by the data decompressor in double buffer mode; A two-dimensional processing unit array, including a fixed-point differential engine, a floating-point derivative processing unit, and an addition unit, for sequentially reading the slice vectors in the block, processing the data and calculating first-order and second-order derivatives, comparing the vector values ​​with previous values, extracting the relevant mantissa slices from the grid register; vector summation calculation, and obtaining an updated data block; A data-aware controller that extracts the relevant mantissa slices from the grid registers and controls the entire processing flow; Temporary value buffer, used to store temporary calculation results, all processing unit arrays can fully access its storage content.

2. The partial differential equation solving accelerator according to claim 1, characterized in that: Also includes: A shared cache is used to cache overlapping data during computation.

3. The partial differential equation solving accelerator according to claim 1, characterized in that: The data decompressors, compressors and two-dimensional processing unit arrays are arranged in multiple groups to form multiple independent computing units for processing multiple block data simultaneously.

4. The partial differential equation solving accelerator according to claim 1, characterized in that: The decompressor and the compressor are connected to the off-chip memory via a bus system.

5. The partial differential equation solving accelerator according to claim 1, characterized in that: The data compression method of the compressor comprises: The original floating point data is decomposed into sign, exponent and mantissa parts; The 1-bit symbol data is grouped into a bit chain and shortened using fixed-length run-length coding; then all the index values ​​in the matrix are aggregated and Huffman coding is applied to generate the Huffman tree of the block and the encoded index string; For the mantissa, the decimal part in the vector is normalized with the first exponent as reference; the first mantissa is used as a reference number, and the incremental compression method is used to subtract each number at position i from the number at the previous position i-1.

6. The partial differential equation solving accelerator according to claim 1, characterized in that: The compressor includes a Huffman decoder, a run-length decoder and a mantissa adder, and processes off-chip data in blocks.

7. The partial differential equation solving accelerator according to claim 1, characterized in that: The decompressor is used to record and count the frequency of exponential values ​​in each input vector and insert the exponential value frequency into a frequency table; an exponential sign module caches the input exponent; after transmitting the block information, the encoder constructs a Huffman tree and outputs an exponential bit stream.

8. The partial differential equation solving accelerator according to claim 1, characterized in that: The two-dimensional processing unit array is specifically used for: Perform mantissa extraction and multiplication based on the grid point difference value; divide the mantissa data into multiple 8-bit slices; set up a unified base index eb within the block, and align the mantissa values ​​of other data according to the base index; First, the difference is extracted, and then these slices are multiplied by the differential constant in the equation in fixed-point form; then, the product results are added in fixed-point form to form the template difference component; The template differential components are multiplied by the physical constants and added to generate a complete floating point representation; the exponent portion of the floating point representation value is then compared with the original u value to determine the affected mantissa slice and whether to update the base exponent; The fixed-point differential engine consists of 8 columns, 4 rows and 3 channels of fixed-point processing units; each decompressed data block, once stored in the on-chip memory, is subdivided into 8 small blocks, each of which is further processed by 24 fixed-point processing units; Each processing unit contains two registers for storing differential coefficient constants along the x and y dimensions respectively; each processing unit has four 8-bit fixed-point inputs for selecting input values ​​for calculation; The processing unit is also used to receive a 16-bit mantissa slice from the previous channel and store it in Ox1 and 0y1. Two multipliers calculate the product of the grid point in the x and y dimensions with the equation constant in one cycle; then the two results are passed to the adder and added to the original summation result; the fixed-point calculation unit within the processing unit row consists of 8 columns and 3 units; the number of channels is set to 3, and the differences are divided into multiple groups, and the three coefficients are input separately.

9. A data processing method, based on the partial differential equation solving accelerator according to claim 1, characterized in that: include: a) Using a time-blocking strategy, a data block of size n is obtained from off-chip storage in each iteration; c) decomposing the floating point number into three parts: a sign, an exponent and a mantissa, and compressing the three parts respectively according to the characteristics of the data block; d) In the template calculation, the integer coefficients of the finite difference are processed separately from the floating-point coefficients in the physical equations, where an n-th order finite difference calculation along one dimension is converted into n fixed-point operations followed by a floating-point operation; e) during on-chip data extraction, the mantissa of the floating-point value is sliced, and by predicting the data flow during iterations, only those slices whose mantissa has changed are selected for calculation; b) After k iterations, storing the updated data block back to the off-chip storage.

10. A data processing method according to claim 9, characterized in that: The fixed-point operation comprises the following steps: The entire block is divided into multiple sub-blocks along its diagonal, and each row is responsible for processing the data of one sub-block; Mark the first element position of each input and output vector as 0, assuming that the i-th row is input in the 0th cycle, and the operation related to the i-th row is completed in the m-th cycle; the 0th cycle first calculates the product of ui and k3 to obtain the partial sum of u(i+1) in the x dimension, recorded as ux(i+1); in the 1st cycle, ui is passed to the w3 part in the processing unit of channel\#0 and the K2 part in the processing unit of channel\#1 to calculate uy(i+1) and ux(i); ux(i+1) is cached in the register Ox2 of the second channel, waiting for u(i+1) to be transferred to the second processing unit for recalculation in the second cycle; adjacent registers along the channel dimension store the grid points of the same row in the m-th cycle; the two-dimensional processing unit array of channel 0 simultaneously outputs the ux of the i-th row and the uy of the (i+1)-th row to the multipliers of the x-dimension and y-dimension, and multiplies them with the physical constants; Each output point needs to perform m-1 multiplication operations in the x dimension and m-1 addition operations in the y dimension; and one output point undergoes m cycles of data transmission processing in the two-dimensional processing unit array.

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