Early-stage multiple process corner time sequence prediction method based on deep learning, electronic equipment and storage medium

Abstract

The invention discloses an early-stage process corner time sequence prediction method based on deep learning, an electronic device and a storage medium, and aims to capture an interaction relationship between units in a path, an early-stage time sequence prediction process is established based on a bidirectional long-short-term memory network. The time sequence and the physical information of each level of unit in the path are represented as a sequence, and the information in the sequence is transmitted and represented through the BLSTM to learn the mutual influence between the units in the path, so that the path delay after layout is accurately predicted. On the basis, the influence of the global feature of the path on the path time sequence after layout is learned by using the multi-layer perceptron network, so that the prediction precision is improved, and meanwhile, an early time sequence prediction framework is adapted to a scene of various process corners. Based on the prediction result, the iteration of the design is reduced, and the time cost of the chip design is reduced.

Description

Technical Field

[0001] The present invention relates to an early multi-process corner timing prediction method based on deep learning, an electronic device and a storage medium, and belongs to the technical field of electronic design automation. Background Art

[0002] Static Timing Analysis (STA) can fully and exhaustively verify the timing requirements of digital integrated circuit design, and plays an important role in the integrated circuit design process. Static timing analysis is required in both logic synthesis and physical design to ensure the convergence of the chip at each stage of the design process. However, due to the unpredictable challenges in integrated circuit design, the results of static timing analysis may lack reliability, resulting in design iterations.

[0003] With the development of integrated circuits and the advancement of process nodes, the unpredictability of timing has become one of the major challenges facing integrated circuit design. This unpredictability may come from the differences between different timing analysis tools. For example, tools specifically used for timing analysis can perform more accurate path-based timing analysis (PBA), while some layout and routing tools that integrate timing analysis engines can also perform timing analysis, but due to factors such as time, they only perform graph-based timing analysis (GBA). The unpredictability in timing analysis may also come from inaccurate timing estimates of downstream design stages in the current design stage. For example, the logic synthesis stage only contains information on the logic level of the design, and the information on the physical level of the design is unknown. The lack of physical information will lead to inaccurate timing estimates in the early stages of the design, resulting in large differences in the timing results of the path after logic synthesis and after layout.

[0004] The timing results of the path after logic synthesis and after layout are very different. On the one hand, such poor timing predictions for the downstream design stage in the early stage of the design may cause timing violations to be discovered only in the later stage of the design. In severe cases, it may cause the design to return to the front-end process, resulting in design iterations and increasing the chip design cycle. On the other hand, logic synthesis converts the register transfer level (RTL) design into a gate-level netlist. Different logic synthesis schemes bring different power consumption, performance, and area (Power-Performance-Area, PPA). Inaccurate timing estimates in the early stage cannot guide the synthesis tool to generate high-quality netlists, and more design iterations are still required to achieve a more ideal quality of results (Quality of Results, QoR).

[0005] The lack of physical information makes timing prediction in the early stages of design challenging. In the digital integrated circuit design process, the following two methods are usually used to alleviate the problem of inaccurate timing estimation caused by the lack of physical information in the early stages of design. The first method is to introduce a wire load model to estimate the wire length. This method simply estimates the wire length based on the number of fan-outs of the cells in the path. Although it supplements the physical information to a certain extent, it still cannot improve the predictability of the logic synthesis stage due to the lack of accuracy in the estimation of the wire length. The second method is to perform physically-aware logic synthesis. This method integrates the layout engine in the physical design tool into the logic synthesis tool, and obtains physical location information by performing simple layout during the logic synthesis process, thereby achieving a close correlation with the quality of the subsequent physical design stage. However, directly calling the layout engine during the synthesis process is very time-consuming and costly.

[0006] Most of the time spent on static timing analysis is spent on timing analysis of multiple process corners under different process, voltage, and temperature (PVT) conditions. With the advancement of process nodes and the complexity of design scenarios, the number of process corners that need to be accepted for integrated circuits is also increasing rapidly, consuming a lot of computing resources and running time.

[0007] Therefore, the timing acceleration problem in the scenario of multiple process corners has also been widely studied. The machine learning model is trained using the timing information in some process corners, working modes, timing analysis modes and other scenarios to predict the timing information in other scenarios, so that the timing results in all scenarios can be obtained. Compared with the time cost of timing analysis, the prediction time of the machine learning model is greatly reduced, thereby achieving the purpose of accelerating timing analysis. At present, most of the timing prediction work across process corners focuses on the same design stage, working mode and timing analysis mode. This type of research accelerates the timing analysis under multiple process corners by reducing the number of process corners that need to be simulated. In addition, there are a few studies that have conducted timing prediction for multiple process corners under different timing analysis modes and different working modes. This type of research makes the timing prediction work across timing analysis modes and working modes adapt to the working scenarios of multiple process corners, avoiding the establishment of a separate timing prediction model for each process corner, thereby accelerating the time problem caused by the timing analysis requirements of multiple process corners under the corresponding timing prediction problem.

[0008] However, there are still some shortcomings in the existing research work:

[0009] (1) Existing methods perform timing prediction at the unit level or circuit level. The former method of accumulating the overall timing of the path leads to the accumulation of errors and ignores the influence of the interaction between the units in the path. The latter cannot provide more detailed information for repairing timing violations or optimizing circuits.

[0010] (2) Existing methods do not comprehensively consider the factors that affect the timing of the downstream design stage and are unable to characterize the effective information of the path as completely as possible.

[0011] (3) In almost all existing studies across design stages, there is no discussion on how to adapt the proposed work to the scenario requirements of multiple process corners, and it is obviously unrealistic to establish a separate prediction model for each process corner.

[0012] Therefore, in order to improve the predictability of the early stage of design and reduce the design time under the requirements of multi-process corner timing analysis, an efficient and accurate early timing estimation method that can adapt to the requirements of multi-process corner scenarios is needed. Summary of the invention

[0013] Purpose: In order to overcome the shortcomings of the prior art, the present invention provides an early multi-process corner timing prediction method based on deep learning, an electronic device and a storage medium, which can provide designers with path delay values ​​under multi-process corners after layout in the logic synthesis stage. Based on the prediction results, the present invention implements an optimization process to guide designers or tools to optimize, reduce design iterations, and reduce the time cost of chip design.

[0014] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0015] In the first aspect, an early multi-process corner timing prediction method based on deep learning specifically includes:

[0016] Step S1: Obtain a circuit netlist after logic synthesis and a circuit netlist after layout, perform static timing analysis on the circuit netlist after logic synthesis and the circuit netlist after layout respectively, obtain a static timing report of the circuit after logic synthesis and a static timing report of the circuit after layout, extract the timing, physical information and path delay value of each level of units in the path of the circuit after logic synthesis from the static timing report of the circuit after logic synthesis, extract the path delay value information of the circuit after layout from the static timing report of the circuit after layout, and use the difference between the path delay value after layout and the path delay value after logic synthesis as a label.

[0017] Step S2: preprocessing is performed based on the timing and physical information of each level of units in the path of the circuit after logic synthesis to obtain the sequence characteristics and global characteristics of the path.

[0018] Step S3: Input the sequence features and global features into the extreme gradient boosting model for process corner selection to obtain optimized sequence features and global features.

[0019] Step S4: Input the optimized sequence features into the bidirectional long short-term memory network for learning to obtain the sequence feature representation vector of the path, and input the optimized global features into the multi-layer perceptron network for learning to obtain the global feature representation vector of the path.

[0020] Step S5: merge the sequence feature representation vector of the path with the global feature representation vector of the path, use the merged representation vector and the label as training samples, and use the training samples to train the time series prediction model to obtain the trained time series prediction model.

[0021] Step S6: Input the circuit netlist to be predicted after logic synthesis into the trained timing prediction model to obtain the path delay prediction value after layout.

[0022] As a preferred solution, the method further includes: Step S7: obtaining an optimized circuit netlist using a logic synthesis tool according to the predicted path delay values ​​after layout.

[0023] As a preferred solution, the step S2 specifically includes:

[0024] For discrete non-numeric variables of the unit type of the path, a tokenizer is used to create a numeric variable that is mapped one-to-one with the unit type variable.

[0025] For the continuous numerical variables of the path unit delay, input conversion time, output load capacitance, and half-period, the variables are mapped to different bins for discretization through binning operations, and discrete numerical variables are obtained whose relative size relationship remains unchanged before and after the numerical conversion.

[0026] A discrete numeric variable that gets the cell fanout of the path.

[0027] The above numerical variables are combined into the sequence characteristics of the path.

[0028] The process features in the PVT features of the path are mapped one by one to the values, and merged with the values ​​in the PVT features into PVT numerical variables. The sequence features are spliced ​​with the PVT numerical variables and the path delay values ​​after logic synthesis to obtain the global features of the path.

[0029] As a preferred solution, the dimensions of the sequence features and global features of each path are the same, and the insufficient sequence features are filled with zeros.

[0030] As a preferred solution, step S3 specifically includes:

[0031] The sequence features and global features of the path are input into the extreme gradient boosting model for representation learning to obtain the delay values ​​of the path under different process corner types.

[0032] The sequence features and global features of the path under a certain process angle are iteratively deleted according to the delay values ​​of the paths under different process angle types.

[0033] The sequence characteristics and global characteristics of the path with a balanced number of process corner types are obtained as the optimized sequence characteristics and global characteristics.

[0034] As a preferred solution, the bidirectional long short-term memory network includes: two opposite unidirectional LSTM layers, the input sequence {x 1 ,x 2 ,…,x k} is input into the forward LSTM layer to obtain the forward output f of each level k , input into the reverse LSTM layer to obtain the reverse output b of each level k , the final output of each level of the BLSTM layer is composed of the forward output f k and reverse output b k For multiple BLSTM layers, the output vectors of each level after concatenation form a new sequence as the input of the next BLSTM layer. For the last BLSTM layer, the output vector f of the last level of the forward LSTM layer k and the output vector b of the last level of the reverse LSTM layer 1 The concatenation of is used as the representation vector of the entire sequence.

[0035] As a preferred solution, the multilayer perceptron network consists of two fully connected layers and one dropout layer. The fully connected layer learns potential information by performing dimensional transformation on the initial global features, and the dropout layer randomly deletes some neurons in the fully connected layer to obtain a global feature representation vector.

[0036] As a preferred solution, the time series prediction model adopts an artificial neural network.

[0037] As a preferred solution, the step S7 specifically includes:

[0038] According to the path delay prediction value after layout, the path whose path delay prediction value is greater than the threshold is regarded as a critical path, and a timing constraint command corresponding to the logic synthesis tool is generated for the critical path;

[0039] According to the timing constraint commands corresponding to the logic synthesis tool, the logic synthesis tool is used to perform incremental optimization to obtain an optimized circuit netlist.

[0040] In a second aspect, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements an early multi-process corner timing prediction method based on deep learning as described in any one of the first aspects.

[0041] According to a third aspect, a computer device includes:

[0042] Memory, used to store instructions.

[0043] A processor is used to execute the instructions so that the computer device performs the operations of an early multi-process corner timing prediction method based on deep learning as described in any one of the first aspects.

[0044] Beneficial effects: The present invention provides an early multi-process corner timing prediction method based on deep learning, an electronic device and a storage medium. In order to capture the interaction relationship between units in the path, the early timing prediction process of the present invention is built based on a bidirectional long short-term memory network (Bi-directional Long Short-Term Memory, BLSTM), and the timing and physical information of each level of units in the path are represented as a sequence, and the information in the sequence is transmitted and characterized by BLSTM to learn the mutual influence between units in the path, so as to accurately predict the path delay after layout. On this basis, the present invention uses a multi-layer perceptron (Multilayer Perceptron, MLP) network to learn the impact of the global characteristics of the path on the timing of the path after layout, improves the prediction accuracy, and adapts the early timing prediction framework to the scenario of multiple process corners. Based on the prediction results, the present invention implements an optimization process to guide designers or tools to optimize, reduce design iterations, and reduce the time cost of chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a flow chart of early multi-process corner delay prediction based on BLSTM of the present invention.

[0046] Figure 2 Flow chart of sequence feature preprocessing of the present invention.

[0047] Figure 3 Schematic diagram of the process of selecting the process angle of the training set of the present invention.

[0048] Figure 4 This is a structural diagram of the BLSTM layer of the present invention. DETAILED DESCRIPTION

[0049] The following is a clear and complete description of the technical solutions in the examples of the present invention in conjunction with the accompanying drawings in the examples of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present invention.

[0050] The present invention will be further described below in conjunction with specific embodiments.

[0051] Embodiment 1:

[0052] This embodiment introduces an early multi-process corner timing prediction method based on deep learning, which predicts the timing of the path after layout under various process corners based on the timing after logic synthesis and physical information, thereby improving the predictability of the early design. Figure 1 As shown, it specifically includes: physical design, feature selection and data preprocessing, training set process corner selection, model representation learning, path delay value generation and optimization process:

[0053] S1: First is the physical design part. The circuit netlist after logic synthesis is physically designed to obtain the circuit netlist after layout. Static timing analysis is performed on the circuit netlist after logic synthesis and the circuit netlist after layout respectively to obtain the static timing report of the circuit after logic synthesis and the static timing report of the circuit after layout. The timing, physical information and path delay values ​​of each level of units in the path are extracted from the static timing report of the circuit after logic synthesis, and the path delay value information is extracted from the static timing report of the circuit after layout. On this basis, the difference between the path delay value after layout and the path delay value after synthesis is used as the label of the timing prediction model.

[0054] Furthermore, the physical design includes layout planning and layout.

[0055] S2: The second part is feature selection and data preprocessing. Preprocess the timing and physical information of each level of the path extracted from the static timing report of the circuit after logic synthesis in S1 to obtain the sequence features and global features related to the path timing after layout. Divide the preprocessed data into training set data and test set data, use the training set data for model training, and use the test set data to verify the model prediction accuracy and efficiency.

[0056] Furthermore, the preprocessing includes extracting the timing and physical information of each unit in each path for preprocessing to obtain the sequence characteristics of the path, and splicing the sequence characteristics of the path with the process, voltage, temperature and path delay value after logic synthesis of the path to obtain the global characteristics of the path.

[0057] After preprocessing, the sequence feature lengths of all paths are consistent to ensure compatibility with the subsequent bidirectional long short-term memory network (BLSTM). In addition, process, voltage, temperature (PVT) information and path delay after logic synthesis will also affect the path timing after layout, and they are spliced ​​together to form the global characteristics of the path.

[0058] S3: Select the process corner of the training set based on step S2. This part draws on the idea of ​​the greedy algorithm, inputs the sequence features and global features preprocessed in step S2 into the Extreme Gradient Boosting (XGBoost) model for representation learning, and iteratively deletes the path data under a certain process corner from the training set based on the prediction results of the model to obtain a subset of the training set that can achieve the best prediction effect for model training.

[0059] S4: Input the sequence features and global features in the subset of the training set obtained in step S3 into the model for representation learning. The sequence features of the path are input into a bidirectional long short-term memory network for learning to obtain the sequence feature representation vector of the path. The network consists of two reverse long short-term memory (LSTM) layers to provide the network with the previous and next connections of the units in the path; the global features of the path are input into a multilayer perceptron (MLP) network for learning to obtain the path global feature representation vector.

[0060] S5: Path delay value generation part. The representation vector containing path sequence information and global information obtained by model representation learning in step S4 is merged and input into the artificial neural network (ANN) to obtain the path delay change in the logic synthesis stage and the layout stage; the path delay change in the layout stage is added to the path delay value in the logic synthesis stage, and finally the path delay prediction value after layout is obtained.

[0061] S6: Finally, the optimization process part. Based on the prediction result of step S5, the present invention implements an optimization process to guide the logic synthesis tool (IC Compiler) to generate a higher quality circuit netlist, improve the power consumption, performance and area (Power-Performance-Area, PPA) of the design, thereby reducing the iteration of the design and reducing the time cost of chip design.

[0062] Furthermore, the step S2 is as follows: Figure 2 As shown, the specific steps include:

[0063] S21: Path sequence feature extraction: The local information of each level of unit or unit-driven network in the path is spliced ​​into a sequence to reflect the overall timing of the path.

[0064] The present invention selects path sequence characteristics such as cell type, cell delay, input conversion time, output load capacitance and cell fan-out.

[0065] The cell type reflects the logical function and driving strength of the cell. The timing library provides different delay lookup tables for different types of cells. The delay will be different due to different functions and driving strengths. The cell delay is part of the path delay. The cell delay in the synthesis stage can be used as a benchmark for the delay after layout. The input conversion time is one of the indexes of the lookup table for cell delay and output conversion time in the timing library, which directly affects the cell delay and output conversion time, and further affects the delay of subsequent cells through the transmission of conversion time. The output load capacitance, as another dimension index of the lookup table, determines the cell delay and output conversion time. The number of cell fan-outs represents the number of load cells driven by the cell. The larger the fan-out, the larger the output capacitance, and the larger the cell delay. The cell type, cell delay, input conversion time, output load capacitance, and fan-out in the path sequence feature come directly from the timing report after synthesis.

[0066] The global characteristics of a path directly affect the overall timing of the path.

[0067] The present invention selects the process, voltage, temperature conditions of the circuit operation and the path global characteristics such as the path delay in the synthesis stage.

[0068] Timing analysis needs to be performed under specific working conditions. PVT information such as process, voltage, and temperature, as the working conditions of the circuit, directly affects the path timing after layout; the path delay in the synthesis stage provides a benchmark for the path delay prediction after layout.

[0069] The timing prediction framework of the present invention obtains the path delay after layout by calibrating the path delay after synthesis, so the difference between the path delay after layout and the path delay after synthesis is used as the label of the timing prediction model. The final predicted value of the path delay after layout It can be calculated by formula (1), where represents the path delay after synthesis, Represents the path delay change predicted by the model;

[0070] (1)

[0071] S22: In order to convert the extracted features into a form that can be processed by subsequent machine learning models, the feature data needs to be preprocessed. Path sequence features and global features are represented and learned by different models and are processed in different ways.

[0072] Preprocessing method of sequence features: For discrete non-numeric variables such as unit type, the present invention draws on the method of processing text sequences in the field of natural language processing, and uses a tokenizer to establish a one-to-one mapping relationship between unit type variables and numbers, thereby converting discrete non-numeric variables into discrete numeric variables; for continuous numeric variables such as unit delay, input conversion time, output load capacitance, and half-period, the variables are mapped to different bins through binning operations for discretization, thereby converting continuous numeric variables into discrete numeric variables, and the relative size relationship before and after the numeric conversion remains unchanged; fan-out itself is a discrete numeric variable, and no tokenization or binning is required. For each timing path, the relevant features of each level of unit or unit-driven network in the path are subjected to the above-mentioned preprocessing operations to form a feature sequence.

[0073] However, the different lengths of each path in the circuit lead to inconsistent dimensions of the input feature sequence, which cannot be directly input into the BLSTM model for learning. Therefore, the feature sequence needs to be padded or truncated to a uniform length. Considering that in the path timing problem, the feature value of 0 has little effect on the final timing result, this paper pads the feature sequence with zeros, and the final sequence length depends on the longest timing path in the data set.

[0074] The global features need to be converted into numerical features for subsequent multi-layer perceptron model learning. For the process features in the PVT features, the present invention performs a simple one-to-one mapping from character strings to numerical values, mapping the three process models of fast (FF), typical (TT) and slow (SS) to numerical values ​​1, 2, and 3 respectively. The voltage and temperature in the PVT features and the integrated path delay are themselves numerical features, and no special preprocessing operations are required.

[0075] Furthermore, the step S3 is as follows: Figure 3 As shown, the specific steps include:

[0076] S31: The selection of the process corners in the training set is another preparation work for the delay prediction model, which is crucial to the accuracy of the model. The early multi-process corner delay prediction model of the present invention can adapt to the working scenarios of multiple process corners. The model is trained on the path data corresponding to a limited number of process corners, and is used to predict the timing of other paths under known and unknown process corners. The known process corners here refer to the process corners used in the training set, and the unknown process corners refer to the process corners that do not appear in the training set. Simply put, from an empirical point of view, if the training set data can only cover the SS (Slow N Slow P) process corner, then its prediction results for the path under the SS process corner may be excellent, but the timing prediction results for the path under the TT (Typical N Typical P) or even FF (Fast N Fast P) process corner may be poor. Therefore, for the same number of training set process corners, if the process corners can be covered more evenly, the model may achieve better performance. In order to screen the subset of training set process angles that can achieve the best prediction effect, the present invention regards the problem of selecting the training set process angle subset as an optimization problem, and uses a greedy search algorithm to iteratively delete the training data under a certain process angle from the training set to find the optimal process angle subset under the condition that the number of training set process angles is determined.

[0077] Furthermore, the step S4 is as follows: Figure 4 As shown, the specific steps include:

[0078] S41: The path sequence features are input into the BLSTM network for representation learning. The traditional LSTM network is composed of LSTM units at each level. Each LSTM unit learns the information of this level and passes it to the next level, so as to sequentially learn the mutual influence between the elements in the input sequence and obtain the vector representation of the entire input sequence. This LSTM network learns the sequence in a unidirectional way. However, in the path timing problem, the influence between gate units is mutual and bidirectional. The timing of the current gate unit will not only be affected by the previous level and the previous unit, but also by the next level and the subsequent unit. For example, the input conversion time of each level unit in the path affects the output conversion time of the current level unit, thereby affecting the input conversion time of the next level unit. This influence relationship in the path makes the timing information of the previous level unit closely related to the timing information of the subsequent unit. The line length is closely related to the line capacitance. The change of the line length brings about the change of the load capacitance, thereby affecting the timing of the previous level unit or even the previous level unit. This influence relationship makes the timing information of the previous level unit be affected by the information related to the next level unit. Therefore, in the problem of path timing prediction, simply using a unidirectional LSTM network will cause information loss and lead to a decrease in prediction accuracy;

[0079] In order to better learn the mutual influence relationship between units at all levels in the path, this paper uses a bidirectional long short-term memory network to represent and learn the path sequence features. The bidirectional LSTM consists of two opposite unidirectional LSTM layers. Its forward and reverse memory transmission characteristics enable the influence between units in the path to be transmitted to the previous and next levels. The structure diagram of the BLSTM layer: Input sequence {x 1 ,x 2 ,…,x k} is input into the forward LSTM layer to obtain the forward output f of each level k , input into the reverse LSTM layer to obtain the reverse output b of each level k , the final output of each level of the BLSTM layer is composed of the forward output f k and reverse output b k For multiple BLSTM layers, the output vectors of each level after concatenation form a new sequence as the input of the next BLSTM layer. For the last BLSTM layer, the output vector f of the last level of the forward LSTM layer k and the output vector b of the last level of the reverse LSTM layer 1 The concatenation of is used as the representation vector of the entire sequence.

[0080] S42: The impact of the global characteristics of the path on the path timing after layout cannot be ignored. Global characteristics such as process, voltage, temperature and integrated path delay constitute a feature matrix. After being processed by feature engineering, an effective path global feature representation can be obtained. Unlike complex path sequence characteristics, the global characteristics of the path can be described by a data matrix. Therefore, the present invention uses a simple MLP network to characterize and learn the extracted global features. The MLP network used in the present invention is composed of two fully connected layers and one discard layer (dropout layer). The fully connected layer learns the potential information by dimensional transformation of the initial global features. The dropout layer randomly deletes some neurons in the fully connected layer to reduce the occurrence of overfitting. After learning the MLP network, a global feature representation vector is obtained.

[0081] Finally, the global feature representation vector learned by the MLP network and the sequence feature representation vector learned by the BLSTM network are combined to obtain the final path representation vector, which is then input into the artificial neural network to predict the path delay changes in the logic synthesis stage and the layout stage. The predicted path delay changes are added to the path delay value after logic synthesis to obtain an estimate of the path delay value after layout.

[0082] Furthermore, the step S6 specifically includes the following steps:

[0083] S61: This optimization process embeds the delay prediction model proposed by the present invention into the chip design process, and uses the path delay value after layout predicted by the delay prediction model to guide further PPA optimization in the logic synthesis stage to generate a higher quality circuit netlist.

[0084] In order to retain a certain margin, the present invention regards the path with a predicted post-layout path delay value greater than 90% of the clock cycle as a critical path, and uses the set_max_delay command to generate a timing constraint file based on the TCL (Tool Command Language) language, thereby constraining these critical paths that need to be further optimized. Then, Design Compiler is used for incremental optimization to generate a higher quality circuit netlist, improve the power consumption, performance and area (Power-Performance-Area, PPA) of the design, thereby reducing the iteration of the design and reducing the time cost of chip design.

[0085] Embodiment 2:

[0086] A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, an early multi-process corner timing prediction method based on deep learning as described in any one of Embodiment 1 is implemented.

[0087] Embodiment 3:

[0088] A computer device comprising:

[0089] Memory, used to store instructions.

[0090] A processor is used to execute the instructions so that the computer device performs the operations of an early multi-process corner timing prediction method based on deep learning as described in any one of Embodiment 1.

[0091] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0092] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0095] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An early multi-process corner timing prediction method based on deep learning, characterized by: Specifically include: Step S1: obtaining a circuit netlist after logic synthesis and a circuit netlist after layout, performing static timing analysis on the circuit netlist after logic synthesis and the circuit netlist after layout respectively, obtaining a static timing report of the circuit after logic synthesis and a static timing report of the circuit after layout, extracting the timing, physical information and path delay values ​​of each level of units in the path of the circuit after logic synthesis from the static timing report of the circuit after logic synthesis, extracting the path delay value information of the circuit after layout from the static timing report of the circuit after layout, and taking the difference between the path delay value after layout and the path delay value after logic synthesis as a label; Step S2: preprocessing the timing and physical information of each level of the circuit path after logic synthesis to obtain the sequence characteristics and global characteristics of the path; Step S3: inputting the sequence features and global features into the extreme gradient boosting model for process corner selection to obtain optimized sequence features and global features; Step S4: inputting the optimized sequence features into the bidirectional long short-term memory network for learning to obtain the sequence feature representation vector of the path, and inputting the optimized global features into the multi-layer perceptron network for learning to obtain the global feature representation vector of the path; Step S5: merging the sequence feature representation vector of the path with the global feature representation vector of the path, using the merged representation vector and the label as training samples, and using the training samples to train the time series prediction model to obtain a trained time series prediction model; Step S6: Input the circuit netlist to be predicted after logic synthesis into the trained timing prediction model to obtain the path delay prediction value after layout.

2. The method for early multi-process corner timing prediction based on deep learning according to claim 1, characterized in that: Also includes: Step S7: According to the predicted path delay values ​​after layout, a logic synthesis tool is used to obtain an optimized circuit netlist.

3. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: As a preferred solution, the step S2 specifically includes: For discrete non-numeric variables of the path's unit type, a word segmenter is used to create a numeric variable that is mapped one-to-one with the unit type variable; For the continuous numerical variables of the path unit delay, input conversion time, output load capacitance, and half-period, the variables are mapped to different bins for discretization through binning operations, and the discrete numerical variables whose relative size relationship before and after the numerical conversion remains unchanged are obtained; Gets the discrete numeric variable of the cell fan-out of the path; The above numerical variables are combined into the sequence characteristics of the path; The process features in the PVT features of the path are mapped one by one to the values, and merged with the values ​​in the PVT features into PVT numerical variables. The sequence features are spliced ​​with the PVT numerical variables and the path delay values ​​after logic synthesis to obtain the global features of the path.

4. The method for early multi-process corner timing prediction based on deep learning according to claim 3, characterized in that: The dimensions of the sequence features and global features of each path are the same, and the insufficient sequence features are filled with zeros.

5. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: The step S3 specifically includes: The sequence features and global features of the path are input into the extreme gradient boosting model for representation learning to obtain the delay values ​​of the path under different process corner types; Iteratively delete the sequence features and global features of the path under a certain process angle according to the delay values ​​of the paths under different process angle types; The sequence characteristics and global characteristics of the path with a balanced number of process corner types are obtained as the optimized sequence characteristics and global characteristics.

6. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: The bidirectional long short-term memory network comprises: two opposite unidirectional LSTM layers, an input sequence {x1, x2, ..., x k } is input into the forward LSTM layer to obtain the forward output f of each level k , input into the reverse LSTM layer to obtain the reverse output b of each level k , the final output of each level of the BLSTM layer is composed of the forward output f k and reverse output b k For multiple BLSTM layers, the output vectors of each level after splicing form a new sequence as the input of the next BLSTM layer. For the last BLSTM layer, the output vector f of the last level of the forward LSTM layer k The concatenation of the output vector b1 of the last level of the reverse LSTM layer is used as the representation vector of the entire sequence; The multilayer perceptron network consists of two fully connected layers and one dropout layer. The fully connected layer learns potential information by performing dimensional transformation on the initial global features. The dropout layer randomly deletes some neurons in the fully connected layer to obtain a global feature representation vector.

7. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: The time series prediction model adopts an artificial neural network.

8. The method for early multi-process corner timing prediction based on deep learning according to claim 2, characterized in that: The step S7 specifically includes: According to the path delay prediction value after layout, the path whose path delay prediction value is greater than the threshold is regarded as a critical path, and a timing constraint command corresponding to the logic synthesis tool is generated for the critical path; According to the timing constraint commands corresponding to the logic synthesis tool, the logic synthesis tool is used to perform incremental optimization to obtain an optimized circuit netlist.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, an early multi-process corner timing prediction method based on deep learning as described in any one of claims 1 to 8 is implemented.

10. A computer device, characterized in that: include: A memory for storing instructions; A processor is used to execute the instructions so that the computer device performs the operation of the early multi-process corner timing prediction method based on deep learning as described in any one of claims 1 to 8.

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