Explanatable FPGA (Field Programmable Gate Array) multi-target wiring optimization method

Abstract

The invention discloses an interpretable FPGA (Field Programmable Gate Array) multi-target wiring optimization method, which comprises the following steps: in a layout stage, creating and training a congestion-line length multi-task prediction model, and predicting congestion and line length by using the congestion-line length multi-task prediction model; based on the predicted congestion and line length results, performing relation analysis of the congestion and the line length to obtain a congestion-line length influence feature map; and guiding a VTR wiring device to carry out wiring optimization through the congestion-wire length influence feature map. According to the method, the line length and the congestion are predicted at the same time, and the prediction result is fused into the wiring optimization process, so that other factors are prevented from being influenced by the progress of one factor. Besides, multiple indexes are predicted through a machine learning model and can be used as the premise of multi-index optimization, finally, the relation of the multiple indexes can be analyzed through interpretable artificial intelligence, multi-target wiring optimization is guided through the relation, and the situations of congestion and deterioration of the line length indexes during independent prediction optimization can be effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuit electronic design automation (EDA), and in particular to an explainable FPGA multi-objective wiring optimization method. Background Art

[0002] Field Programmable Gate Arrays (FPGAs) provide a highly flexible and powerful platform for designing and implementing custom digital circuits using a complex matrix of programmable logic cells and a wide range of configurable interconnect resources. This versatility makes FPGAs excellent in diverse applications such as prototyping, development, high-performance computing, and embedded systems. In order to transform complex FPGA designs into functional hardware, an electronic design automation (EDA) process becomes essential, which includes stages such as logic synthesis, technology mapping, packaging, placement, and routing to effectively optimize and implement these designs. Among these stages, routing is particularly complex and time-consuming, and is becoming increasingly difficult with the increasing complexity of designs, the presence of large-scale heterogeneous logic components, limited routing resources, and strict design constraints. So far, among FPGA routing solutions, path-finding-based algorithms such as the Verilog-to-Routing (VTR) router and the Adaptive Incremental Router (AIR) can provide relatively good routing solutions, but their heuristic nature means that they cannot guarantee optimal or legal routing solutions in terms of routing length, congestion, timing, or power constraints.

[0003] In order to improve the effectiveness and efficiency of routing, machine learning (ML) technology is increasingly being used for optimization. Generally, routing optimization based on machine learning includes two stages: post-routing indicator prediction and routing optimization based on predicted indicators. For example, the literature (Umair Siddiqi, Timothy Martin, Sam Van den Eijnden, Ahmed Shamli, Gary Grewal, Sadiq Sait, and Shawki Areibi. 2022. Faster FPGA Routing by Forecasting and Pre-Loading Congestion Information. In 2022 ACM / IEEE Workshop on Machine Learning for CAD. ACM, Snowbird, UT, USA, 15-20.) applies random forest regression to predict routing congestion, and then uses these predictions to adjust the cost parameters of the VTR router. (T.Martin, Q.Li, C.Barnes, G.Grewal, and S.Are ibi. 2023.A Deep-Learning Data-Driven Approach for Reducing FPGA Routing Runtimes. In 2023International Conference on Field Programmable Technology (ICFPT). ACM, Yokohama, JAPAN, 7–15.) Using a convolutional encoder-decoder model to predict routing resource utilization graphs from placement, and by combining these predictions to adjust the initial congestion costs of the VTR and AI R routers, their method guides the routing process towards more efficient convergence.The literature (Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis JH Huang, and Evangeline FY Young. 2022. PROS2.0: A Plug-in for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42, 1 (2022), 164–177.) used two different convolutional neural networks to predict routing congestion and wire length. Their method significantly reduced design rule check violations (DRVs) by using predicted congestion data to guide the routing process. In addition, the literature (Yi lu Chen, Miaodi Su, Hongzhi Ding, Shaohong Weng, Zhifeng Lin, and Xiqiong Bai. 2024. High-Correlation 3D Routability Estimation for Congestion-Guided Global Routing. The Journal of Supercomputing 80, 3 (2024), 3114–3141.) developed a convolutional neural network model to perform congestion estimation, and then these estimates were used as the basis for implementing more feasible routing solutions. The above work is based on single-task routing quality prediction and optimization, and now a small number of multi-task-based routing quality prediction works are gradually emerging. For example, the paper (Juming Xian, Yan Xing, Shuting Cai, Weijun Li, Xiaoming Xiong, and Zhengfa Hu. 2024. WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-task Learning. ACM Transactions on Design Automation on Electronic Systems 29, 3 (2024), 1–19.) proposed a multi-task-based wiring quality predictor, aiming to simultaneously predict congestion, wire length, congestion and power after FPGA routing.

[0004] Although current machine learning-based routing optimization methods show promise, there is still a lot of room for improvement. First, FPGA routing involves multi-objective optimization, which requires balancing various conflicting goals, such as minimizing line length, reducing congestion, and minimizing delay. These goals are interrelated, which means that progress on one factor may affect other factors. For example, focusing on reducing line length may lead to increased congestion, and prioritizing reducing congestion may lead to longer line lengths. Current work mostly focuses on prediction and optimization of a single objective, and does not take into account the relationship between multiple indicators. Secondly, the black-box nature of machine learning models often makes the prediction results lack transparency, which also hinders the effective integration of these models with the routing optimization process. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an explainable FPGA multi-objective wiring optimization method.

[0006] To achieve the above purpose, the technical solution provided by the present invention is:

[0007] An explainable FPGA multi-objective routing optimization method, comprising:

[0008] In the layout stage, a congestion-line length multi-task prediction model is created and trained, and the congestion and line length are predicted using the congestion-line length multi-task prediction model.

[0009] Based on the predicted congestion and line length results, the relationship between congestion and line length is analyzed to obtain the congestion-line length impact characteristic diagram;

[0010] The congestion-line length impact characteristic diagram is used to guide the VTR router to perform wiring optimization.

[0011] Furthermore, the congestion-line length multi-task prediction model adopts the CWNet framework, which consists of two unique branches arranged in a cascade structure;

[0012] One branch is dedicated to predicting congestion, and the other branch focuses on predicting line length. The output of the branch predicting congestion is used as the input of the branch predicting line length.

[0013] The branch predicting congestion is a fully convolutional network with an encoder-decoder structure. The encoder part contains a convolutional neural network and a pooling operation, and the activation function is the Leaky ReLU activation function. The decoder part uses a combination of an upsampling module and a convolutional neural network, and the activation function is the Leaky ReLU activation function. The last layer uses the Sigmoid activation function to generate the final output. The skip connection between the encoder and the decoder ensures smooth information transfer and retains fine-grained details and spatial information that may be lost during downsampling.

[0014] The branch for predicting line length is a convolutional neural network, which starts with a convolutional layer, followed by an adaptive average pooling layer and a flattening layer, and finally includes five fully connected layers. After processing through these layers, the scalar value of the line length is output.

[0015] Furthermore, the total loss of the congestion-line length multi-task prediction model is

[0016]

[0017] in, To predict the congestion loss, To predict the line length loss, θ 1 and θ 2 Represent the parameters of the model in the two tasks respectively.

[0018] Furthermore, when the congestion-line length multi-task prediction model predicts congestion and line length, the input features include the distribution of logical resource blocks image place , the connection relationship between logical resource blocksimage connect , Logic Resource Block Pin Utilization Image PinUtilization ;

[0019] The congestion-line length multi-task prediction model combines the congestion prediction results to predict the line length. The data set is as follows:

[0020]

[0021] Among them, n 1 and n 2 These are the number of samples used for the congestion prediction task and the line length prediction task respectively; Features required for congestion prediction tasks; Output image of the congestion prediction task congestion ; These are some of the features required for the line length prediction task, and the output image of the congestion prediction task. congestion Combine all the features required for line length prediction task; This is the output result of the line length prediction task.

[0022] Furthermore, based on the predicted congestion and line length results, the relationship between congestion and line length is analyzed, including:

[0023] The DeepSHAP interpretable artificial intelligence algorithm is used to explain the SHAP value of pixels that relate congestion to line length. The calculation formula is as follows:

[0024]

[0025] Where x(m) and x'(m) represent the mth pixel of the feature vector at x and the mth pixel of the feature vector at x' respectively; x is the sample and x' is the background sample; Indicates k a The SHAP value of the mth pixel in the feature; D a is the background sample data; |D a | is the number of background sample data; P a Divide k a All N except a Combination N a \{k a}; N a For all features, N a ={image place 、image connect 、image PinUtilization}; k a The congestion prediction result of the branch that predicts congestion is an image; |P a |N a \{k a}; Contains from N a \{k a}, representing all the features in N a Except k a The element of 2 represents the branch of predicting line length; X(x(m),x'(m),S) is a function that represents creating a mixed sample by selecting features specified by set S from sample x and selecting the remaining features not included in S from background sample x';

[0026] For a sample x, the congestion-line length impact feature map is generated by calculating the SHAP values ​​of all its pixels using formula (3).

[0027] Furthermore, the congestion-line length impact characteristic diagram is used to guide the VTR router to perform wiring optimization, including:

[0028] The routing architecture of the VTR router is represented by a routing resource graph RRG. In each routing iteration, a search strategy is used on the routing resource graph RRG to determine the lowest cost path for all connections;

[0029] Where cost(v) is defined as the path cost of node v in the routing resource graph RRG, c his (v) and d his (v) are the congestion cost and delay cost of the reverse path from the current node v to the starting point, c(v) and d(v) are the congestion cost and delay cost of the current node v, respectively. exp (v) and dexp (v) are the expected congestion cost and delay cost of the forward path from the current node v to the sink, respectively. γ is the critical factor. The cost calculation formula using node v is as follows:

[0030] cost(v)=(1-γ)(C his (v)+c(v)+c exp (v))+γ(d his (v)+d(v)+d exp (v))(4)

[0031] In formula (4), c exp (v) and d exp (v) The adjustment is performed through the enhanced forward-looking graph, which is obtained by enhancing the forward-looking graph through the congestion-line length impact feature map.

[0032] Furthermore, the forward-looking graph is enhanced through the congestion-line length impact feature graph, including:

[0033] For paths passing through locations with high SHAP values, a penalty factor α is added to both the delay cost and the congestion cost, where α>0. The formula is as follows:

[0034]

[0035] Among them, c exp (v) and d exp (v) is the expected congestion cost and delay cost of the forward path from the current node v to the sink before the forward graph is enhanced by the congestion-line length impact feature graph; and is the expected congestion cost and delay cost of the forward path from the current node v to the sink after the forward graph is enhanced by the congestion-line length impact feature graph; H is the set of high SHAP value areas.

[0036] Compared with the prior art, the principles and advantages of this technical solution are as follows:

[0037] Unlike the existing methods that only predict congestion and then optimize it, this technical solution predicts both line length and congestion, and incorporates the prediction results into the wiring optimization process to avoid the progress of one factor affecting other factors. In addition, the prediction of multiple indicators through machine learning models can serve as a prerequisite for multi-indicator optimization. Finally, interpretable artificial intelligence can analyze the relationship between multiple indicators, and use this relationship to guide the multi-objective wiring optimization, which can effectively avoid the situation where the single prediction optimization of congestion causes the deterioration of line length indicators. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A flowchart of an explainable FPGA multi-objective wiring optimization method of the present invention;

[0040] Figure 2 The present invention is an architecture diagram of a congestion-line length multi-task prediction model used in an interpretable FPGA multi-objective wiring optimization method;

[0041] Figure 3 This is a comparison chart of multi-task losses;

[0042] Figure 4 The following are the prediction results and interpretability analysis results. DETAILED DESCRIPTION

[0043] The present invention will be further described below in conjunction with specific embodiments:

[0044] like Figure 1 As shown, an explainable FPGA multi-objective wiring optimization method described in this embodiment includes the following steps:

[0045] S1. In the layout stage, a congestion-line length multi-task prediction model is created and trained, and the congestion and line length are predicted using the congestion-line length multi-task prediction model;

[0046] In this step, if Figure 2 As shown, the congestion-line length multi-task prediction model adopts the CWNet framework, which consists of two unique branches arranged in a cascade structure;

[0047] One branch is dedicated to predicting congestion, and the other branch focuses on predicting line length. The output of the branch predicting congestion is used as the input of the branch predicting line length.

[0048] The branch predicting congestion is a fully convolutional network with an encoder-decoder structure. The encoder part contains a convolutional neural network and a pooling operation, and the activation function is the Leaky ReLU activation function. The decoder part uses a combination of an upsampling module and a convolutional neural network, and the activation function is the Leaky ReLU activation function. The last layer uses the Sigmoid activation function to generate the final output. The skip connection between the encoder and the decoder ensures smooth information transfer and retains fine-grained details and spatial information that may be lost during downsampling.

[0049] The branch for predicting line length is a convolutional neural network, which starts with a convolutional layer, followed by an adaptive average pooling layer and a flattening layer, and finally includes five fully connected layers. After processing through these layers, the scalar value of the line length is output.

[0050] The total loss of the congestion-line length multi-task prediction model is

[0051]

[0052] in, To predict the congestion loss, To predict the line length loss, θ 1 and θ 2 Represent the parameters of the model in the two tasks respectively.

[0053] Congestion-Line Length Multi-Task Prediction Model When predicting congestion and line length, the input features include the distribution of logical resource blocks image place , the connection relationship between logical resource blocksimage connect , Logic Resource Block Pin Utilization Image PinUtilization ;

[0054] The congestion-line length multi-task prediction model combines the congestion prediction results to predict the line length. The data set is as follows:

[0055]

[0056] Among them, n 1 and n 2 These are the number of samples used for the congestion prediction task and the line length prediction task respectively; Features required for congestion prediction tasks; Output image of the congestion prediction task congestion ; These are some of the features required for the line length prediction task, and the output image of the congestion prediction task. congestion Combine all the features required for line length prediction task; This is the output result of the line length prediction task.

[0057] S2. Based on the predicted congestion and line length results, analyze the relationship between congestion and line length to obtain a congestion-line length impact feature graph;

[0058] This step specifically includes:

[0059] The DeepSHAP interpretable artificial intelligence algorithm is used to explain the SHAP value of pixels that relate congestion to line length. The calculation formula is as follows:

[0060]

[0061] Where x(m) and x'(m) represent the mth pixel of the feature vector at x and the mth pixel of the feature vector at x' respectively; x is the sample and x' is the background sample; Indicates k a The SHAP value of the mth pixel in the feature; D a is the background sample data; |D a | is the number of background sample data; P a Divide k a All N except a Combination N a \{k a}; N a For all features, N a ={image place 、image connect 、image PinUtilization}; k a The congestion prediction result of the branch that predicts congestion is an image; |P a |N a \{k a}; Contains from N a \{k a}, representing all the features in N a Except k a The element of 2 represents the branch of predicting line length; X(x(m),x'(m),S) is a function that represents creating a mixed sample by selecting features specified by set S from sample x and selecting the remaining features not included in S from background sample x';

[0062] For a sample x, the congestion-line length impact feature map is generated by calculating the SHAP values ​​of all its pixels using formula (3).

[0063] S3. The congestion-line length impact characteristic diagram is used to guide the VTR router to optimize the wiring, as follows:

[0064] The routing architecture of the VTR router is represented by a routing resource graph RRG. In each round of routing iteration, the A* search strategy is used on the routing resource graph RRG to determine the minimum cost path for all connections;

[0065] Where cost(v) is defined as the path cost of node v in the routing resource graph RRG, c his (v) and d his(v) are the congestion cost and delay cost of the reverse path from the current node v to the starting point, c(v) and d(v) are the congestion cost and delay cost of the current node v, respectively. exp (v) and d exp (v) are the expected congestion cost and delay cost of the forward path from the current node v to the sink, respectively. γ is the critical factor. The cost calculation formula using node v is as follows:

[0066] cost(v)=(1-γ)(c his (v)+c(v)+c exp (v))+γ(d his (v)+d(v)+d exp (v))(4)

[0067] In formula (4), c exp (v) and d exp (v) Adjusted by an enhanced lookahead graph, which is obtained by enhancing the lookahead graph with a congestion-wirelength impact feature graph. The lookahead graph estimates the delay and congestion cost from the current expansion node to the target sink, allowing the router to quickly identify a low-cost path to the destination.

[0068] The forward-looking graph is enhanced with congestion-line length impact feature graphs, including:

[0069] For paths passing through locations with high SHAP values, a penalty factor α is added to both the delay cost and the congestion cost, where α>0. The formula is as follows:

[0070]

[0071] Among them, c exp (v) and d exp (v) is the expected congestion cost and delay cost of the forward path from the current node v to the sink before the forward graph is enhanced by the congestion-line length impact feature graph; and is the expected congestion cost and delay cost of the forward path from the current node v to the sink after the forward graph is enhanced by the congestion-line length impact feature graph; H is the set of high SHAP value areas.

[0072] In order to demonstrate the superiority and effectiveness of the solution described in the present invention, the following experiments were conducted:

[0073] Verification was performed on open source and industry-authoritative benchmarks, namely VPR and Koios2.0. The two datasets differ in circuit scale. The specific information is as follows:

[0074] Table 1 Characteristics of FPGA design

[0075]

[0076] All experiments were carried out on the Linux platform. The algorithms proposed in this invention were implemented using Python and C++ languages ​​and ran on a workstation with an Intel i7-10700 CPU, 128G memory and an NVIDIA GeForce RTX 3070 Ti graphics card.

[0077] The cosine annealing learning rate strategy is adopted, and the initial value is set to 0.001. The batch size is set to 8, and the training configuration is 12000 iterations. In addition, the Adam W optimizer is used with a weight decay of 0.001 and a β coefficient of (0.9, 0.99). For data partitioning, 20% of the samples are assigned to the test set, and the remaining samples form the training set. In the wiring optimization, the penalty coefficient is set to 1.

[0078] Two types of metrics are needed: one for evaluating the performance of the CWNet model and some other metrics for evaluating the routing optimization performance of the proposed method. For CWNet, mean absolute percentage error (MAPE), normalized root mean square error (NRMS), and multi-task performance (ΔMTL) are used to evaluate the prediction performance of congestion-specific tasks, wirelength-specific tasks, congestion-specific tasks, and wirelength-specific tasks in coordination. For the final routing optimization results, the performance will be evaluated from the perspective of peak congestion, wirelength, critical path delay, and routing time.

[0079] 1) CWNet’s performance

[0080] The results in Table 2 show that CWNet outperforms two baseline multi-task learning (MTL) models in overall prediction performance. Specifically, CWNet outperforms all corresponding single-task learning (STL) and multi-task learning baseline models in predicting line length. In terms of congestion prediction, CWNet surpasses STL-DLCong, but fails to reach the performance level of other related STL and MTL models. Overall, CWNet provides a competitive solution for jointly learning congestion and line length, especially performing well in line length prediction, while still showing potential for improvement in congestion prediction. In addition, the time cost presented in Table 3 shows that although CWNet is slower than MTL-HS, it runs more efficiently than the two STL model combinations and MTL-SS. By analyzing Figure 3 The training and test losses of all MTL models in , it can be seen that CWNet converges faster than MTL-SS, but slower than MTL-HS.

[0081] Table 2 Comparison of model performance

[0082]

[0083] Table 3 Comparison of model time expenditure

[0084]

[0085] 2) Congestion-Line Length Impact Characteristic Diagram

[0086] Figure 4 The predicted congestion feature map and its corresponding congestion-wirelength impact feature map for the design named tpu_like.large.os are shown. In general, the congestion-wirelength impact map shows four scenarios: 1) high SHAP values ​​at pixels with high congestion values, 2) high SHAP values ​​at pixels with low congestion values, 3) low SHAP values ​​at pixels with high congestion values, and 4) low SHAP values ​​at pixels with low congestion values. Among them, scenarios 1 and 4 are the most common. Therefore, it is clear that the effect of congestion on wirelength is very complex and non-linear. Significant effects are observed not only in pixels with high congestion, but also in pixels with low congestion.

[0087] 3) CWRO wiring optimization performance

[0088] The benchmark routers used for comparison include VTR and HC. VTR refers to the AI ​​R algorithm implemented in VTR 8, while HC refers to optimizing VTR using only the congestion graph predicted by STL-C. For all 22 designs, their routing metrics, including peak congestion, wire length, critical path delay, and time cost, are listed in Table 4.

[0089] The results presented in Table 4 show that CWRO statistically outperforms VTR and HC in terms of peak congestion, wire length, critical path delay, and time cost. In particular, CWRO achieves significant reductions in peak congestion and time cost compared to VTR, with an average reduction of 45.64% and 20.38%, respectively. In contrast, the average reduction ratios of wire length and critical path delay are relatively small, at 3.07% and 2.54%, respectively. In addition, HC slightly outperforms VTR in critical path delay and time cost, but this improvement comes at the expense of peak congestion and wire length deterioration, which deteriorate by 61.54% and 0.41%, respectively. In the last seven large designs, CWRO's advantage in peak congestion becomes increasingly obvious, while HC's disadvantage becomes more prominent.

[0090] Table 4 Comparison of wiring optimization results

[0091]

[0092] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, all changes made according to the shape and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An explainable FPGA multi-objective routing optimization method, characterized in that: include: In the layout stage, a congestion-line length multi-task prediction model is created and trained, and the congestion and line length are predicted using the congestion-line length multi-task prediction model. Based on the predicted congestion and line length results, the relationship between congestion and line length is analyzed to obtain the congestion-line length impact characteristic diagram; The congestion-line length impact characteristic diagram is used to guide the VTR router to perform wiring optimization.

2. The interpretable FPGA multi-objective routing optimization method according to claim 2, characterized in that: The congestion-linelength multi-task prediction model adopts the CWNet framework, which consists of two unique branches arranged in a cascade structure; One branch is dedicated to predicting congestion, and the other branch focuses on predicting line length. The output of the branch predicting congestion is used as the input of the branch predicting line length. The branch predicting congestion is a fully convolutional network with an encoder-decoder structure. The encoder part contains a convolutional neural network and a pooling operation, and the activation function is the Leaky ReLU activation function. The decoder part uses a combination of an upsampling module and a convolutional neural network, and the activation function is the Leaky ReLU activation function. The last layer uses the Sigmoid activation function to generate the final output. The skip connection between the encoder and the decoder ensures smooth information transfer and retains fine-grained details and spatial information that may be lost during downsampling. The branch for predicting line length is a convolutional neural network, which starts with a convolutional layer, followed by an adaptive average pooling layer and a flattening layer, and finally includes five fully connected layers. After processing through these layers, the scalar value of the line length is output.

3. The interpretable FPGA multi-objective routing optimization method according to claim 2, characterized in that: The total loss of the congestion-line length multi-task prediction model is in, To predict the congestion loss, To predict the line length loss, θ1 and θ2 represent the parameters of the model in the two tasks respectively.

4. The interpretable FPGA multi-objective routing optimization method according to claim 2, characterized in that: Congestion-Line Length Multi-Task Prediction Model When predicting congestion and line length, the input features include the distribution of logical resource blocks image place , the connection relationship between logical resource blocksimage connect , Logic Resource Block Pin Utilization Image PinUtilization ; The congestion-line length multi-task prediction model combines the congestion prediction results to predict the line length. The data set is as follows: Among them, n1 and n2 are the number of samples used for congestion prediction task and line length prediction task respectively; Features required for congestion prediction tasks; Output image of the congestion prediction task congestion ; These are some of the features required for the line length prediction task, and the output image of the congestion prediction task. congestion Combine all the features required for line length prediction task; This is the output result of the line length prediction task.

5. The interpretable FPGA multi-objective routing optimization method according to claim 2, characterized in that: Based on the predicted congestion and line length results, the relationship between congestion and line length is analyzed, including: The DeepSHAP interpretable artificial intelligence algorithm is used to explain the SHAP value of pixels that relate congestion to line length. The calculation formula is as follows: Where x(m) and x'(m) represent the mth pixel of the feature vector at x and the mth pixel of the feature vector at x' respectively; x is the sample and x' is the background sample; Indicates k a The SHAP value of the mth pixel in the feature; D a is the background sample data; |D a | is the number of background sample data; P a Divide k a All N except a Combination N a \{k a }; N a For all features, N a ={image place 、image connect 、image PinUtilization }; k a The congestion prediction result of the branch that predicts congestion is an image; |P a |N a \{k a }; Contains from N a \{k a }, representing all the features in N a Except k a elements; f2 represents the branch of predicting line length; X(x(m), x'(m), S) is a function that represents creating a mixed sample by selecting features specified by set S from sample x and selecting the remaining features not included in S from background sample x'; For a sample x, the congestion-line length impact feature map is generated by calculating the SHAP values ​​of all its pixels using formula (3).

6. The interpretable FPGA multi-objective wiring optimization method according to claim 5, characterized in that: The congestion-line length impact characteristic diagram guides the VTR router to optimize the wiring, including: The routing architecture of the VTR router is represented by a routing resource graph RRG. In each routing iteration, a search strategy is used on the routing resource graph RRG to determine the lowest cost path for all connections; Where cost(v) is defined as the path cost of node v in the routing resource graph RRG, c his (v) and d his (v) are the congestion cost and delay cost of the reverse path from the current node v to the starting point, c(v) and d(v) are the congestion cost and delay cost of the current node v, respectively. exp (v) and d exp (v) are the expected congestion cost and delay cost of the forward path from the current node v to the sink, respectively. γ is the critical factor. The cost calculation formula using node v is as follows: cost(v)=(1-γ)(c his (v)+c(v)+c exp (v))+γ(d his (v)+d(v)+d exp (v)) (4) In formula (4), c exp (v) and d exp (v) The adjustment is performed through the enhanced forward-looking graph, which is obtained by enhancing the forward-looking graph through the congestion-line length impact feature map.

7. The interpretable FPGA multi-objective routing optimization method according to claim 6, characterized in that: The forward-looking graph is enhanced with congestion-line length impact feature graphs, including: For paths passing through locations with high SHAP values, a penalty factor α is added to both the delay cost and the congestion cost, where α>0. The formula is as follows: Among them, c exp (v) and d exp (v) is the expected congestion cost and delay cost of the forward path from the current node v to the sink before the forward graph is enhanced by the congestion-line length impact feature graph; and is the expected congestion cost and delay cost of the forward path from the current node v to the sink after the forward graph is enhanced by the congestion-line length impact feature graph; H is the set of high SHAP value areas.

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