Multi-core chip voltage drop rapid prediction method based on convolutional neural network

Abstract

The invention belongs to the field of integrated circuit design and optimization, and discloses a chip performance optimization technology based on IrDrop prediction. According to the technology, a simulation tool and a deep learning model are combined, and efficient design and optimization of chip dynamic voltage frequency regulation (DVFS) are achieved. The method comprises the following steps: processing randomly generated and sampled power and frequency pairs, constructing a circuit model, acquiring data in combination with simulation calculation, obtaining voltage drop distribution of a multi-core chip, and improving calculation precision by adopting a fixed point iteration method. Data sets of power budget, frequency and voltage drop are further collected, and a convolutional neural network model is trained, so that nanosecond-level voltage drop rapid calculation of the complex multi-core chip is realized, and an efficient and accurate solution is provided for chip performance optimization.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design and optimization, and in particular relates to a method for improving and optimizing a chip dynamic voltage frequency scaling (DVFS) method. Background Art

[0002] At present, the thermal management methods of system-level chips mainly include dynamic voltage and frequency scaling (DVFS) and task migration. When adjusting the chip voltage and frequency, voltage drop (IrDrop) is a key factor that cannot be ignored. Traditional voltage drop calculation and decision-making methods usually rely on Hspice or circuit analysis to simulate and calculate circuit models. However, with the continuous improvement of chip integration, the power grid model of the chip system is also expanding, which poses a huge challenge to the calculation of voltage drop and DVFS optimization methods. Traditional methods can perform accurate simulation and calculation when dealing with small-scale circuits, but when facing large-scale integrated circuits, they often use the worst-case voltage drop to roughly represent the voltage drop change under DVFS. Although this method simplifies the calculation process, it also sacrifices a lot of performance, resulting in conservative voltage and frequency matching, thus failing to fully release the system performance potential.

[0003] Although this traditional worst-case approach improves the feasibility of calculation to a certain extent, its conservatism directly affects the effect of chip performance optimization. In large-scale integrated circuits (VLSI), the voltage drop distribution is not only complex but also highly dynamic, and is significantly affected by the power consumption distribution and task allocation of multi-core chips. Traditional methods have difficulty in capturing these dynamic changes in real time, resulting in limited performance improvement during dynamic voltage frequency scaling (DVFS).

[0004] With the development of artificial intelligence and machine learning technologies, data-driven methods have brought new solutions to chip optimization. Through deep learning modeling, key features can be quickly extracted from complex power grids and task allocation scenarios to achieve rapid prediction and optimization of voltage drops. At the same time, the computing power of modern multi-core chip simulation systems also provides strong support for large-scale data collection and complex model training. This emerging technical means has brought the possibility of solving the problem of difficulty in balancing accuracy and efficiency in traditional methods. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a real-time voltage drop fast prediction method for dynamic voltage and frequency adjustment in multi-core chip systems. This method can significantly improve the calculation speed while ensuring the calculation accuracy, providing effective support for chip performance optimization and thermal management.

[0006] The present invention obtains the standard power frequency variation range by using the Parsec-Blackscholes benchmark test, and generates random sequence data covering the frequency range of 1GHz-4GHz and the power range of 0.1W-5.1W in combination with a specially designed data generator. The Hspice simulation calculation is performed using an iterative method to accurately collect the associated data of power, frequency and voltage drop, and based on this, a convolutional neural network model is trained to obtain a high-precision voltage drop prediction capability. Finally, the trained model is embedded in the HotSniper simulation platform for verification and application, achieving the voltage drop calculation at the nanosecond level at a speed far exceeding the traditional method under the premise of controlling the error within 2.7%.

[0007] The present invention provides a real-time voltage drop fast prediction method for dynamic voltage frequency adjustment (DVFS) in a multi-core chip system. By combining the iterative method with the deep learning model, a large amount of time consumption in the traditional calculation method is avoided; the main working point of the system is found through the iterative method, and the training and optimization process of the voltage drop prediction model is simplified; by taking the key parameters such as voltage, current and resistance of the multi-core chip power grid model as input, a high-precision voltage drop prediction model is obtained by using deep convolutional neural network (CNN) training, and it is embedded in the simulation platform for fast prediction. This method generates widely covered training data through random sampling, and uses convolutional neural network and regression model to accurately model the voltage drop, thereby ensuring efficient and accurate prediction of the voltage drop in a short time, providing stable support for system optimization.

[0008] Second, considering the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by the present invention are specifically described as follows: The stability maintenance method for long short-term memory network compression of the present invention uses an iterative method to find the main fixed points that are difficult to solve, and separates the linear part at the main fixed points, and applies DEIM only to the nonlinear part, thereby ensuring the stability of the compressed long short-term memory network at the main working point.

[0009] Third, the following important points also serve as auxiliary evidence for the creativity of the claims of the present invention: (1) the expected benefits and commercial value of the technical solution of the present invention after transformation; (2) the technical solution of the present invention fills the technical gaps in the industry at home and abroad; (3) whether the technical solution of the present invention solves the technical problems that people have been eager to solve but have never been able to solve; and (4) whether the technical solution of the present invention overcomes technical prejudice. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 It is a flowchart of the method for quickly predicting voltage drop of a multi-core chip provided by an example of the present invention;

[0012] Figure 2 The Irdrop graph is calculated based on the iterative method within the multi-core chip voltage drop fast prediction method of the present invention;

[0013] Figure 3 It is a schematic diagram of a standard multi-core power grid model used in the multi-core chip voltage drop fast prediction method of the present invention;

[0014] Figure 4 It is a schematic diagram of the layout of a 64-core chip FLP provided by an example of the present invention; DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0016] The specific methods and steps are as follows:

[0017] (1) Determine the frequency and power range, determine the applicable frequency and power range to cover the required state and adapt to the commonly used benchmark. Run multiple benchmark programs in HotSniper, covering different frequency domains and commonly used temperature and voltage ranges, summarize and determine the reasonable frequency and power range. Use random sampling method to generate training data to ensure data diversity and coverage.

[0018] (2) Preprocessing and generation of training data: Preprocess the generated training data, extract the SPICE information such as voltage, current, resistance, etc. required by the multi-core chip, and assign values ​​to the standardized power grid model. For different training data, define the initial IrDrop value, and use the minimum voltage method to select the minimum value of IrDrop+F(f) as the VDD value of the power grid model. A new set of voltage drop values ​​is obtained through training and used as the initial value for the next iterative calculation. In each iteration, the voltage, current and other data are updated and recalculated, and the voltage drop error is gradually reduced, and finally an acceptable voltage drop value is obtained. The corresponding data of these frequencies, powers and voltage drops are the training data. Collect multiple sets of data to form a complete data set, 80% of which are used as training sets and 20% as test sets, providing a basis for subsequent model training and verification.

[0019] (3) A deep learning architecture is constructed based on a multi-layer convolutional neural network (LeNet model), and the ReLU activation function is combined to enhance the nonlinear expression ability of the model. The mean square error (MSE) is used as the loss function, and the back propagation method is used to iteratively optimize the model to continuously reduce the prediction error, and finally complete the training and generation of a high-precision voltage drop prediction model.

[0020] (4) The actual application of the model adopts the replacement method. The trained prediction model is embedded in the system-level optimization solution, and the voltage and frequency matching pair is obtained through the DVFS method. In millisecond-level calculations, the model is used to quickly predict the voltage drop on the system chip, and then optimize the voltage and frequency matching method. Under the same power budget conditions, the DVFS method is optimized and the overall system performance is improved by reducing the voltage supply and increasing the operating frequency.

Claims

1. A multi-core chip voltage drop fast prediction method based on convolutional neural network, characterized in that: The performance and frequency of the system are improved by modifying the dynamic frequency-voltage matching relationship in real time. The method includes: obtaining the initial training value by running multiple benchmark tests, using an iterative method to process data and obtain the voltage drop of multi-core chips, building a deep learning architecture based on a convolutional neural network, and testing and using the new method based on the Hotsniper tool.

2. The multi-core chip voltage drop fast prediction method based on convolutional neural network as claimed in claim 1, characterized in that The iterative method is used to deal with the problem of IRDrop without initial value, and the convolutional neural network is used to replace the Hspice iterative calculation process.

3. The multi-core chip voltage drop fast prediction method according to claim 2, characterized in that The frequency range of the training data is 1GHz to 4GHz, and the power budget range is 0.1W to 5.1W.

4. The multi-core chip voltage drop fast prediction method according to claim 3 is characterized in that A gating grid model has been added and a method for replacing nonlinear gating with linear gating has been added.

5. The multi-core chip voltage drop fast prediction method according to claim 4, characterized in that A handshake method for internal and external links in Docker.

6. The application of the multi-core chip voltage drop fast prediction method according to claims 1 to 5, characterized in that In the dark silicon state, multi-core chips solve the on-chip voltage drop to solve the matching pair problem of the dynamic voltage and frequency adjustment algorithm, including but not limited to the iterative solution of voltage drop involved in task migration in thermal management and dynamic voltage adjustment.

7. A neural network solves power grid wiring prediction, characterized in that The information data processing and gate setting method replaces the nonlinear method with the linear method as shown in claims 3 to 4.

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