Quantum circuit width optimization method based on quantum bit reusable transformation

Abstract

The invention relates to the technical field of quantum circuit optimization, in particular to a quantum circuit width optimization method based on quantum bit reusable transformation. The problem that a reusable quantum bit recognition technology has limitation is solved. According to the technical scheme, the method comprises the steps that S1, quantum bit multiplexing conditions are defined; s2, quantum circuit division is carried out; s3, judging the reusable quantum bits; s4, identifying a preceding quantum gate and a following quantum gate acting on the non-multiplexed quantum bit; s5, formulating a quantum bit multiplexing transformation strategy; and S6, converting the subsequent quantum gate into the preceding quantum gate. The method has the beneficial effects that the width of the quantum circuit is optimized; the cost required for line mapping to meet connectivity constraints is reduced; and the execution fidelity of the quantum circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum circuit optimization, and in particular to a quantum circuit width optimization method based on quantum bit reusable transformation. Background Art

[0002] As a cutting-edge computing technology, quantum computing integrates the ideas of quantum physics, computer science and information theory. Reference paper: Lau JWZ, Lim KH, Shrotriya H, et al. NISQ computing: where are we and where do we go? [J]. AAPPS bulletin, 2022, 32(1): 27. At present, quantum computing technology is in the NISQ (noisy intermediate-scale quantum) era. Reference paper: De Leon NP, Itoh KM, Kim D, et al. Material science and opportunities for quantum computing hardware [J]. Science, 2021, 372(6539): eabb2823. Due to the limitations of hardware manufacturing, existing quantum computers are strictly constrained in the number of available quantum bits. With the development of quantum computing technology, the number of quantum bits required to design complex quantum circuits has gradually increased, but existing equipment can hardly meet this demand. Reference paper: Czarnik P, Arrasmith A, Cincio L, et al. Qubit-efficient exponential suppression of errors[J]. arXiv preprint arXiv:2102.06056, 2021. In order to fully tap the potential of quantum computing in practical applications, researchers are actively exploring more efficient ways to utilize quantum bits.

[0003] A quantum circuit is a representation of a quantum algorithm. It operates on logical qubits through a sequence of quantum gates and measures the logical qubits at the end of the circuit to achieve specific quantum computing functions. Reference: Wang H, Hofheinz M, Ansmann M, et al. Measurement of the decay of Fock states in a superconducting quantum circuit [J]. Physical Review Letters, 2008, 101(24): 240401. In traditional static quantum circuits, the measurement operation is usually located at the end of the quantum circuit to read the final state of the qubit.

[0004] References: E, Tripathi V, Seif A, et al. Quantum Fourier transform using dynamic circuits [J]. Physical Review Letters, 2024, 133 (15): 150602. and Vazquez AC, Tornow C, Riste D, et al. Scaling quantum computing with dynamic circuits [J]. arXiv preprint arXiv: 2402.17833, 2024. With the development of quantum computing hardware, current quantum computing hardware begins to support dynamic circuits. References: Hong X, Feng Y, Li S, et al. Equivalence checking of dynamic quantum circuits [C] / / Proceedings of the 41st IEEE / ACM International Conference on Computer-Aided Design. 2022: 1-8. Dynamic circuits support intermediate circuit measurement and intermediate circuit reset operations, where the reset operation can return the state of the measured quantum bit to the ground state. References: E,Tripathi V,Wang DS,et al.Efficient long-range entanglementusing dynamic circuits[J].PRX Quantum,2024,5(3):030339.Mid-circuit Measurement and Reset is a combination of measurement and reset operations.

[0005] Since 2023, reference paper: Javadi-Abhari A, Treinish M, Krsulich K, et al. Quantum computing with Qiskit [J]. arXiv preprint arXiv: 2405.08810, 2024. Intermediate measurement and reset have been integrated into their respective platforms by some quantum computing hardware manufacturers. Through intermediate measurement and reset, when designing quantum circuits, a quantum bit can be measured in the middle of the circuit and reset to the ground state to achieve specific computing functions. This mechanism provides more flexibility and optimization opportunities for quantum computing.

[0006] Through intermediate measurement and reset, the qubit that has completed all operations can be measured and reset to replace the qubit that has not been used, thereby reducing the number of qubits required for the circuit. This method of reducing the number of qubits required for a quantum circuit is called qubit multiplexing. However, reference papers: DeCross M, Chertkov E, Kohagen M, et al. Qubit-reuse compilation with mid-circuit measurement and reset [J]. Physical Review X, 2023, 13 (4): 041057. and Hua F, Jin Y, Chen Y, et al. Caqr: A compiler-assisted approach for qubit reuse through dynamic circuit [C] / / Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages ​​and Operating Systems, Volume 3. 2023: 59-71. After the circuit is mapped from the logic circuit to the quantum computing hardware device, the large number of inserted SWAP gates will reduce the opportunity for quantum bit reuse. Therefore, quantum bit reuse is usually used in logical quantum circuits before mapping to quantum computing hardware.

[0007] Reference paper: Sadeghi M, Khadirsharbiyani S, Kandemir M T. Quantum circuit resizing [J]. arXiv preprint arXiv: 2301.00720, 2022. The width of a quantum circuit is a key parameter, usually defined as the number of qubits in a quantum circuit, and also the number of physical qubits required when the quantum circuit is executed on quantum computing hardware. If the number of qubits required for a quantum circuit exceeds the support capacity of the quantum computing hardware, the circuit will not be able to be executed on a quantum computer. Therefore, reasonable optimization of the circuit width helps to improve the executability and efficiency of quantum computing. Quantum bit multiplexing is a method of optimizing circuit width, which reduces the number of physical qubits required when the quantum circuit is executed on quantum computing hardware by optimizing the number of logical qubits required in the logical quantum circuit. Quantum bit multiplexing plays an important role in circuit width optimization, enabling optimized circuits to be executed on quantum computing hardware with insufficient number of physical qubits.

[0008] When using the current reusable qubit determination technology to determine reusable qubits, if there is no qubit reuse opportunity in the line, then the line width cannot be optimized. In fact, past work related to qubit reuse did not consider converting non-reusable qubits into reusable qubits. Therefore, when reusable qubits cannot be obtained using qubit reuse conditions, if non-reusable qubits are converted into reusable qubits, then the line width can be optimized.

[0009] The current quantum computing technology is in the NISQ era. Qubits are very valuable resources in quantum computing, and qubit reuse can reduce the number of qubits required for quantum circuit execution. Therefore, how to determine whether a qubit can be reused and convert non-reusable qubits into reusable qubits is of great significance to the width optimization of quantum circuits.

[0010] Current work on qubit reuse does not consider converting non-reusable qubits into reusable qubits. The last quantum gate acting on q1 is g2, and the quantum gate g1 acting on q3 is executed before g2. If q1 is measured and reset after g2 is executed to replace q3, the equivalence of the circuit will be destroyed. Therefore, for the qubit pair [q1,q3], the circuit cannot achieve width optimization by reusing q1 instead of q3.

[0011] However, according to the literature Itoko T, Raymond R, Imamichi T, et al. Computing, 2022, 3(1): 1-41. The mutual exchange rules between single-qubit gates and single-qubit gates, double-qubit gates and double-qubit gates, and single-qubit gates and double-qubit gates are given in the paper. g2 can exchange execution timing with g1 under the premise of maintaining circuit equivalence. After the adjustment, the execution timing of all quantum gates acting on q1 is prior to the execution timing of all quantum gates acting on q3. Therefore, q1 can be reused to replace q3. After q1 is reused to replace q3, the conversion of non-reusable quantum bits to reusable quantum bits can be achieved through equivalent transformation of the circuit. This consideration can further optimize the width of quantum circuits.

[0012] In summary, the prior art still has the following problems:

[0013] (1) Limitations of existing reusable qubit identification technologies: Current reusable qubit identification technologies mainly focus on converting quantum circuits into DAGs and using graph theory to identify reusable qubits. This type of identification technology does not take single qubit gates into account when converting quantum circuits into DAGs. However, these identification technologies do not delve into the essence of qubit reuse, which results in the loss of reusable qubits when using existing reusable qubit identification technologies.

[0014] (2) Failure to consider converting non-reusable qubits into reusable qubits: In fact, not all quantum circuits have opportunities for qubit reuse. If the current reusable qubit identification technology cannot identify reusable qubits in a quantum circuit, then the quantum circuit cannot achieve width optimization. However, some qubits can be converted into reusable qubits. By converting non-reusable qubits into reusable qubits, quantum circuits that were originally unable to achieve width optimization can achieve width optimization.

[0015] How to solve the above problem is the problem to be solved by the present invention. Summary of the invention

[0016] The object of the present invention is to provide a method for optimizing the width of a quantum circuit based on a reusable transformation of qubits. With the support of current quantum computing hardware for dynamic circuits, qubits can be measured and reset during the execution of quantum circuits. Based on intermediate measurements and resets, the qubit is measured and reset immediately after the last operation of the qubit so that it can be reused. However, not all qubits can be reused, and qubits need to meet specific reuse conditions before they can be reused. In fact, some non-reusable qubits can be converted into reusable qubits. In response to this problem, the present invention first proposes a qubit reusable condition, and then proposes a method for reusable transformation of qubits. Through quantum circuit transformation, qubits that were originally non-reusable can be made reusable, thereby further improving the width optimization effect of quantum circuits.

[0017] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is specifically as follows:

[0018] A quantum circuit width optimization method based on quantum bit reusable transformation comprises the following steps:

[0019] Step S1: define quantum bit multiplexing conditions;

[0020] Step S2: performing quantum circuit division;

[0021] Step S3: determining the reusable quantum bits;

[0022] Step S4: Identify the preceding quantum gate and the succeeding quantum gate acting on the non-reusable quantum bit

[0023] Step S5: Formulate a quantum bit reusable transformation strategy;

[0024] Step S6: Convert the subsequent quantum gate into the preceding quantum gate.

[0025] Step S1 is specifically as follows:

[0026] In a quantum circuit, let Q be the set of its quantum bits, Q = {q0,...,q i ,...,q n-1};

[0027] Among them: q0 represents the quantum bit with index order 0, q j represents the quantum bit with index order j, q n-1 Represents the quantum bit with index order n-1, where n represents the total number of quantum bits.

[0028] G is the set of its quantum gates, G = {g0,...,g j ,...,g m-1}.

[0029] Where: g0 represents the quantum gate with index order 0, g represents the quantum gate with index order j, and g m-1 represents the quantum gate with index order m-1, where m represents the total number of quantum gates;

[0030] Formulate the definition: For two different quantum bits q in a quantum circuit i ,q j If you can reuse q i Make it a replacement for q j , then q i ,q j The quantum bit pair [q i ,q j ] is a valid reuse pair; if it is not possible to reuse q i Make it a replacement for q j , then q i ,q j The quantum bit pair [q i ,q j ] is an invalid reuse pair;

[0031] where q i represents the quantum bit with index order i, q j Represents the quantum bit with index order j, and i≠j.

[0032] Step S2 is specifically as follows:

[0033] The qubits that have completed all operations in the quantum circuit can be measured and reset, so that the qubits that have completed all operations can be reused. i ,q j ], if you want to reuse q i , in addition to considering the action on q i The execution of the quantum gate on the replaced quantum bit q also needs to be considered. j The execution of quantum gates on

[0034] In order to analyze and judge the reusability of quantum bits, the present invention provides a time division method for quantum circuits to analyze the effects of quantum bits on q i ,q j The execution of the quantum gates on the circuit; the partitioning method is only used to analyze and determine the reusability of quantum bits. After the processing is completed, the execution timing of the quantum gates in the equivalent circuit can be restored to the execution timing before the partitioning.

[0035] The timing partitioning method is a method used to analyze the execution of quantum gates in quantum circuits and to analyze and determine the reusability of quantum bits;

[0036] The time-series partitioning method first converts the quantum circuit into a directed acyclic graph: Directed Acyclic Graph: DAG, performs topological sorting on the DAG, and obtains a topologically ordered sequence of nodes in the DAG;

[0037] The N quantum gates in the circuit are then divided into N time steps according to the order in the topologically ordered sequence.

[0038] Step S3 is specifically as follows:

[0039] For a quantum bit pair [q i ,q j ], to determine whether there is a two-qubit gate acting on qubit q simultaneously i and q j ;

[0040] If there is a two-qubit gate that acts on qubit q simultaneously i and q j , then q cannot be reused i Make it a replacement for q j , that is [q i ,q j ] is an invalid reuse pair;

[0041] If there is no two-qubit gate acting simultaneously on qubit q i and q j , then judge all the actions on q i Are the execution timings of the quantum gates on q all prior to all the gates acting on q? j The execution timing of the quantum gates on ;

[0042] If all actions on q i The execution order of the quantum gates on q j The execution sequence of quantum gates on q i Make it a replacement for q j ; Otherwise, q cannot be reused i Make it a replacement for q j .

[0043] Step S4 is specifically as follows:

[0044] In the circuit after timing division, for q i Non-reusable quantum bit pair [q i ,q j ],

[0045] The execution sequence precedes all actions on qj The quantum gate acts on q i The gate is called the first quantum gate;

[0046] The execution sequence is any one acting on q j Behind the door and acting on q i The gate is called a backward quantum gate;

[0047] Since the execution sequence of the subsequent quantum gate does not satisfy q i Reusability condition requires converting all subsequent quantum gates into prior quantum gates;

[0048] In the process of converting the subsequent quantum gate into the preceding quantum gate, an equivalent transformation needs to be made to the quantum circuit;

[0049] Therefore, the conversion process of the subsequent quantum gate into the preceding quantum gate is actually the process of equivalent transformation of the quantum circuit, making q i Meeting the reusability condition means achieving q i Reusable quantum circuit equivalent transformation.

[0050] Step S5 is specifically as follows:

[0051] For a quantum bit pair [q i ,q j ], if a post-gate can be transformed by equivalent circuits, its execution sequence is prior to all gates acting on q j quantum gate, then this backward gate can be converted into a forward gate;

[0052] For a quantum bit pair [q i ,q j ], if a post-gate cannot be transformed by equivalent circuits to make its execution sequence precede all gates acting on q j quantum gate, then this backward gate cannot be converted into a forward gate, q i The reusability condition cannot be met.

[0053] Step S6 is specifically as follows:

[0054] S61: Locate the quantum gate whose execution sequence is before the current quantum gate and the closest to the current quantum gate. j Quantum gates;

[0055] S62: moving forward the execution timing of the current subsequent quantum gate;

[0056] If the execution sequence of the current subsequent quantum gate precedes the action on q located in S61 j If there is a quantum gate, check whether the current subsequent quantum gate has been converted into the preceding quantum gate;

[0057] If the current subsequent quantum gate has been converted to the preceding quantum gate, the circuit transformation is terminated;

[0058] If it is not converted to the preceding quantum gate, return to S61;

[0059] If the current backward quantum gate cannot move the execution sequence forward, then enter S63;

[0060] S63: Move back the positioning effect in S61 to q j The execution timing of quantum gates;

[0061] If the execution sequence of the current subsequent quantum gate precedes the action on q located in S61 j If there is a quantum gate, check whether the current subsequent quantum gate has been converted into the preceding quantum gate;

[0062] If the current subsequent quantum gate has been converted to the preceding quantum gate, the circuit transformation is terminated;

[0063] If the current subsequent quantum gate has not been converted into a preceding quantum gate, then return to S61;

[0064] If it is not possible to move the positioning action in S61 backward to q j The execution sequence of the quantum gate of q makes the execution sequence of the current subsequent quantum gate precede that of the gate acting on q j The execution sequence of the quantum gate ends the circuit transformation, q i The reusability conditions are not met;

[0065] For a quantum bit pair [q i ,q j ], in order to make q i If the reuse condition is met, the above strategy can be executed sequentially for the subsequent quantum gates in the circuit until all subsequent quantum gates are converted into the preceding quantum gates;

[0066] If the circuit cannot convert the subsequent quantum gate into the preceding quantum gate during a certain equivalent transformation, the circuit transformation is terminated, and the quantum bit pair [q i ,q j ] is an invalid reuse pair, i.e., q cannot be reused i Alternative to q j ;

[0067] If several equivalent transformations are performed on the line, acting on q i ,q j The execution sequence of the quantum gate satisfies q i If the multiplexing condition is met, the line conversion is also terminated and q can be reused. i Alternative to q j .

[0068] Quantum gates are quantum gates that can be executed in real quantum computing hardware.

[0069] Compared with the prior art, the present invention has the following beneficial effects:

[0070] (1) Optimizing the width of quantum circuits

[0071] The present invention specifically analyzes the characteristics of quantum bit reuse and proposes quantum bit reuse conditions based on these characteristics. Based on the quantum bit reuse conditions, the present invention further considers converting non-reusable quantum bits into reusable quantum bits to further enhance the width optimization effect of quantum circuits and reduce the number of quantum bits required for quantum circuit execution.

[0072] (2) Reduce the cost of route mapping to satisfy connectivity constraints

[0073] The present invention also brings indirect advantages to the optimization of quantum circuits. By further reducing the number of quantum bits required for circuit execution, the number of SWAP gates required to be inserted to map the circuit to the topological architecture of real quantum computing hardware to meet connectivity constraints can be potentially reduced, thereby reducing the possibility of reduced fidelity of the quantum circuit due to excessive circuit depth.

[0074] (3) Improving the execution fidelity of quantum circuits

[0075] The present invention also brings indirect advantages to improving the fidelity of quantum circuit execution. The error rate of quantum bits in real quantum computing devices and the connection error rate between quantum bits are different. Since quantum bit multiplexing can reduce the number of quantum bits required for circuit execution, when the quantum circuit is mapped to the topological architecture of the real quantum computing device, the quantum bits with higher error rates can be selectively avoided, thereby potentially improving the fidelity of quantum circuit execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0077] Figure 1 This is a schematic diagram of the static quantum circuit of the present invention.

[0078] Figure 2 It is a combined schematic diagram of the measurement and reset operations of the present invention.

[0079] Figure 3 Schematic diagram of intermediate measurement and reset supported by the dynamic circuit of the present invention; (a) is a schematic diagram of a static circuit without inserting the measurement and reset combination; (b) is a schematic diagram of a dynamic circuit after inserting the measurement and reset combination.

[0080] Figure 4 Schematic diagram of the present invention for reducing the quantum bits required for a circuit through quantum bit multiplexing; (a) is a schematic diagram of the original circuit; (b) is a schematic diagram of the circuit after multiplexing q0 instead of q1.

[0081] Figure 5 This is a schematic diagram showing that the present invention cannot reuse q1 to replace q3.

[0082] Figure 6 Schematic diagram of circuit transformation for realizing quantum bit reuse in the present invention; (a) is the circuit after equivalent transformation, and (b) is the circuit after multiplexing q1 instead of q3.

[0083] Figure 7 Schematic diagram of the original line and the corresponding DAG of the present invention; (a) is the schematic diagram of the original line, (b) is the schematic diagram of the DAG corresponding to the original line, and (c) is the schematic diagram of the line after division.

[0084] Figure 8 This is a schematic diagram of an equivalent circuit after q0 is multiplexed to replace q1 in the present invention.

[0085] Fig. 9 It is a circuit diagram after equivalent transformation of the present invention.

[0086] Fig.10 This is a circuit diagram after q0 is multiplexed to replace q4 in the present invention.

[0087] Fig.11 Schematic diagram of the reusable transformation of quantum bits in the present invention

[0088] Fig.12 Schematic diagram of the leading gate and trailing gate corresponding to [q0, q4] of the present invention.

[0089] Fig.13 Schematic diagram of the sample circuit of the present invention.

[0090] Fig.14 In the present invention, g2 has been converted into a look-ahead gate schematic diagram.

[0091] Fig.15 G6 of the present invention is still a schematic diagram of the rear door.

[0092] Fig.16 In the present invention, all the rear doors have been converted into the front doors. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0094] Example 1

[0095] like Figure 1 As shown, in traditional static quantum circuits, the measurement operation is usually located at the end of the quantum circuit to read the final state of the quantum bit.

[0096] like Figure 2 As shown, the dynamic circuit supports mid-circuit measurement and mid-circuit reset operations, wherein the reset operation can return the state of the measured quantum bit to the ground state, and mid-circuit measurement and reset (Mid-circuit Measurement and Reset) is a combination of measurement and reset operations.

[0097] like Figure 3 As shown in the figure, through intermediate measurement and reset, when designing a quantum circuit, a quantum bit can be measured in the middle of the circuit and reset to the ground state to achieve a specific computing function. This mechanism provides more flexibility and optimization opportunities for quantum computing.

[0098] like Figure 4 As shown, after the execution of quantum gate g0, the logical quantum bit q0 acted upon by its control bit will no longer have any subsequent operations, and q1 acted upon by the control bit of g1 has not yet started any operations, so q0 can be measured and reset to replace q1.

[0099] like Figure 5 As shown in the circuit in , the last quantum gate acting on q1 is g2, and the quantum gate g1 acting on q3 is executed before g2. If q1 is measured and reset after g2 is executed to replace q3, the equivalence of the circuit will be destroyed. Therefore, for the quantum bit pair [q1,q3], the circuit cannot achieve width optimization by reusing q1 to replace q3.

[0100] According to the mutual independence exchange rules of quantum gates, g2 exchanges execution timing with g1 while maintaining circuit equivalence. The adjusted circuit is as follows Figure 6 (a). At this time, the execution timing of all quantum gates acting on q1 is earlier than the execution timing of all quantum gates acting on q3, so q1 can be reused to replace q3. The circuit after reusing q1 to replace q3 is as follows Figure 6 (b). Therefore, the conversion of non-reusable quantum bits to reusable quantum bits can be achieved by equivalent transformation of the circuit. This consideration can further optimize the width of the quantum circuit.

[0101] By making equivalent transformations to quantum circuits, non-reusable quantum bits can be converted into non-reusable quantum bits, so that the width of some quantum circuits that cannot be optimized can be optimized by quantum bit reuse. Therefore, the present invention provides a quantum circuit width optimization method based on quantum bit reusable transformation.

[0102] A quantum circuit width optimization method based on quantum bit reusable transformation comprises the following steps:

[0103] Step S1: define quantum bit multiplexing conditions;

[0104] Step S2: performing quantum circuit division;

[0105] Step S3: determining the reusable quantum bits;

[0106] Step S4: Identify the preceding quantum gate and the succeeding quantum gate acting on the non-reusable quantum bit

[0107] Step S5: Formulate a quantum bit reusable transformation strategy;

[0108] Step S6: Convert the subsequent quantum gate into the preceding quantum gate.

[0109] Step S1 is specifically as follows:

[0110] In a quantum circuit, let Q be the set of its quantum bits, Q = {q0,...,q i ,...,q n-1};

[0111] Among them: q0 represents the quantum bit with index order 0, q j represents the quantum bit with index order j, q n-1 Represents the quantum bit with index order n-1, where n represents the total number of quantum bits.

[0112] G is the set of its quantum gates, G = {g0,...,g j ,...,g m-1}.

[0113] Where: g0 represents the quantum gate with index order 0, g represents the quantum gate with index order j, and g m-1 represents the quantum gate with index order m-1, where m represents the total number of quantum gates;

[0114] Formulate the definition: For two different quantum bits q in a quantum circuit i ,q j If you can reuse q i Make it a replacement for q j , then q i ,q jThe quantum bit pair [q i ,q j ] is a valid reuse pair; if it is not possible to reuse q i Make it a replacement for q j , then q i ,q j The quantum bit pair [q i ,q j ] is an invalid reuse pair;

[0115] where q i represents the quantum bit with index order i, q j Represents the quantum bit with index order j, and i≠j.

[0116] Step S2 is specifically as follows:

[0117] The qubits that have completed all operations in the quantum circuit can be measured and reset, so that the qubits that have completed all operations can be reused. i ,q j ], if you want to reuse q i , in addition to considering the action on q i The execution of the quantum gate on the replaced quantum bit q also needs to be considered. j The execution of quantum gates on

[0118] In order to analyze and judge the reusability of quantum bits, the present invention provides a time division method for quantum circuits to analyze the effects of quantum bits on q i ,q j The execution of the quantum gates on the circuit; the partitioning method is only used to analyze and determine the reusability of quantum bits. After the processing is completed, the execution timing of the quantum gates in the equivalent circuit can be restored to the execution timing before the partitioning.

[0119] The timing partitioning method is a method used to analyze the execution of quantum gates in quantum circuits and to analyze and determine the reusability of quantum bits;

[0120] The time-series partitioning method first converts the quantum circuit into a directed acyclic graph: Directed Acyclic Graph: DAG, performs topological sorting on the DAG, and obtains a topologically ordered sequence of nodes in the DAG;

[0121] The N quantum gates in the circuit are then divided into N time steps according to the order in the topologically ordered sequence.

[0122] Figure 7 An example of this partitioning method is shown. Figure 7 The DAG of line conversion in (a) is as follows Figure 7 (b) shows that Figure 7After topological sorting of the DAG in (b), we get the topologically ordered sequence g0, g1, g2, g3, g4, g5, g6 (the topologically ordered sequence is not unique). Figure 7 As shown in (c), according to the obtained topological ordered sequence, the quantum gates are divided into corresponding time steps in turn.

[0123] Step S3 is specifically as follows:

[0124] For a quantum bit pair [q i ,q j ], to determine whether there is a two-qubit gate acting on qubit q simultaneously i and q j ;

[0125] If there is a two-qubit gate that acts on qubit q simultaneously i and q j , then q cannot be reused i Make it a replacement for q j , that is [q i ,q j ] is an invalid reuse pair;

[0126] If there is no two-qubit gate acting simultaneously on qubit q i and q j , then judge all the actions on q i Are the execution timings of the quantum gates on q all prior to all the gates acting on q? j The execution timing of the quantum gates on ;

[0127] If all actions on q i The execution order of the quantum gates on q j The execution sequence of quantum gates on q i Make it a replacement for q j ; Otherwise, q cannot be reused i Make it a replacement for q j .

[0128] like Figure 7 As shown in (c), there is no quantum gate between q0 and q1, and the execution sequence of quantum gates g0 and g3 precedes that of quantum gates g4 and g6. Therefore, q0 can be reused to replace q1. The equivalent circuit is as follows: Figure 8 shown.

[0129] for Figure 7 The quantum bit pair [q0,q4] in (c) does not meet the reuse condition of q0, and q0 cannot be reused to replace q4. However, according to the exchange rule that quantum gates do not affect each other, g3 can exchange execution timing with g2 and g1 in sequence while maintaining circuit equivalence. The circuit after equivalent transformation is as follows Fig. 9 shown.

[0130] At this time, the execution sequence of g0 and g3 is earlier than that of g1 and g2, which satisfies the condition of multiplexing q0 to replace q4. The circuit after multiplexing q0 to replace q4 is as follows Fig.10 shown.

[0131] From the above example, we can see that for q i Non-reusable quantum bit pair [q i ,q j ], perform equivalent transformation on the circuit so that the execution timing of the quantum gates in the circuit satisfies q i Reusable conditions. Since it acts on q i ,q j The complex dependencies between the quantum gates on the i It is difficult to adjust the execution timing of quantum gates that meet the reuse conditions.

[0132] Step S4 is specifically as follows:

[0133] In the circuit after timing division, for q i Non-reusable quantum bit pair [q i ,q j ],

[0134] The execution sequence precedes all actions on q j The quantum gate acts on q i The gate is called the first quantum gate;

[0135] The execution sequence is any one acting on q j Behind the door and acting on q i The gate is called a backward quantum gate;

[0136] by Figure 7 (c) Take the quantum bit pair [q0,q4] in the circuit as an example, q0 does not meet the reuse condition. Fig.12 As shown in the figure, the execution timing of g0 precedes all quantum gates acting on q4, and g0 is the first quantum gate. The execution timing of g3 is after g1 and g2, and g3 is the second quantum gate.

[0137] Since the execution sequence of the subsequent quantum gate does not satisfy q i The reusability condition requires that all subsequent quantum gates be converted into prior quantum gates; Fig.11 As shown in the figure, this figure is for q i Non-reusable quantum bit pair [q i ,q j ] i A general diagram of reusable transformation, describing the general process of converting a subsequent quantum gate into a preceding quantum gate, where the action on q j The quantum gate moves to the right, acting on qi The quantum gate moves to the left.

[0138] In the process of converting the subsequent quantum gate into the preceding quantum gate, an equivalent transformation needs to be made to the quantum circuit;

[0139] Therefore, the conversion process of the subsequent quantum gate into the preceding quantum gate is actually the process of equivalent transformation of the quantum circuit, making q i Meeting the reusability condition means achieving q i Reusable quantum circuit equivalent transformation.

[0140] Step S5 is specifically as follows:

[0141] For a quantum bit pair [q i ,q j ], if a post-gate can be transformed by equivalent circuits, its execution sequence is prior to all gates acting on q j quantum gate, then this backward gate can be converted into a forward gate;

[0142] For a quantum bit pair [q i ,q j ], if a post-gate cannot be transformed by equivalent circuits to make its execution sequence precede all gates acting on q j quantum gate, then this backward gate cannot be converted into a forward gate, q i The reusability condition cannot be met.

[0143] Step S6 is specifically as follows:

[0144] S61: Locate the quantum gate whose execution sequence is before the current quantum gate and the closest to the current quantum gate. j Quantum gates;

[0145] S62: moving forward the execution timing of the current subsequent quantum gate;

[0146] If the execution sequence of the current subsequent quantum gate precedes the action on q located in S61 j If there is a quantum gate, check whether the current subsequent quantum gate has been converted into the preceding quantum gate;

[0147] If the current subsequent quantum gate has been converted to the preceding quantum gate, the circuit transformation is terminated;

[0148] If it is not converted to the preceding quantum gate, return to S61;

[0149] If the current backward quantum gate cannot move the execution sequence forward, then enter S63;

[0150] S63: Move back the positioning effect in S61 to q j The execution timing of quantum gates;

[0151] If the execution sequence of the current subsequent quantum gate precedes the action on q located in S61 j If there is a quantum gate, check whether the current subsequent quantum gate has been converted into the preceding quantum gate;

[0152] If the current subsequent quantum gate has been converted to the preceding quantum gate, the circuit transformation is terminated;

[0153] If the current subsequent quantum gate has not been converted into a preceding quantum gate, then return to S61;

[0154] If it is not possible to move the positioning action in S61 backward to q j The execution sequence of the quantum gate of q makes the execution sequence of the current subsequent quantum gate precede that of the gate acting on q j The execution sequence of the quantum gate ends the circuit transformation, q i The reusability conditions are not met;

[0155] For a quantum bit pair [q i ,q j ], in order to make q i If the reuse condition is met, the above strategy can be executed sequentially for the subsequent quantum gates in the circuit until all subsequent quantum gates are converted into the preceding quantum gates;

[0156] If the circuit cannot convert the subsequent quantum gate into the preceding quantum gate during a certain equivalent transformation, the circuit transformation is terminated, and the quantum bit pair [q i ,q j ] is an invalid reuse pair, i.e., q cannot be reused i Alternative to q j ;

[0157] If several equivalent transformations are performed on the line, acting on q i ,q j The execution sequence of the quantum gate satisfies q i If the multiplexing condition is met, the line conversion is also terminated and q can be reused. i Alternative to q j .

[0158] Quantum gates are quantum gates that can be executed in real quantum computing hardware.

[0159] Example 2

[0160] Based on Example 1, the present invention provides a small sample circuit line width optimization to prove the effectiveness of the proposed method. Fig.13The sample circuit in performs the reusable transformation of quantum bits. Here, the quantum bit pair [q1, q3] is selected as the test object, where q1 cannot be reused to replace q3. For the tested quantum bit pair [q1, q3], the quantum gates acting on q1 are g0, g2, and g6, and the quantum gates acting on q3 are g0 and g2. The reusable transformation of q1 is realized according to the quantum bit reusable transformation strategy proposed in the present invention.

[0161] Step 1: Fig.13 In the example, the execution timing of g0 precedes the execution timing of all quantum gates acting on q3. According to the definition of the preceding quantum gate of the present invention, quantum gate g0 is the preceding quantum gate. Therefore, there is no need to perform an equivalent transformation on the circuit, and the execution timing of g0 remains unchanged.

[0162] Step 2: Fig.13 In the definition of the subsequent quantum gate according to the present invention, g2 is the subsequent quantum gate, and an equivalent change needs to be made to the circuit to convert the subsequent quantum gate g2 into the preceding quantum gate. According to the quantum gate exchange rule that quantum gates do not affect each other, the quantum bits acted on by the control bits of g2 and g1 are the same, so g2 can exchange execution timing with g1. Fig.14 In the example, g2 has been converted into a first-run quantum gate and there is no need to adjust the execution timing.

[0163] Step 3: Fig.14 In the figure, according to the definition of the subsequent quantum gate of the present invention, g6 is the subsequent quantum gate, and an equivalent change needs to be made to the circuit to convert the subsequent quantum gate g2 into the preceding quantum gate. According to the rule that quantum gates do not affect each other, the quantum bits acted on by g6, g5, and g4 are different, so g6 can exchange execution timing with g5 and g4 in turn, so that its execution timing is earlier than g4. Fig.15 As shown, after the equivalent transformation of the circuit, the execution timing of g6 is earlier than the execution timing of g5 and g4.

[0164] Step 4: Fig.15 In the example, according to the definition of the subsequent quantum gate of the present invention, g6 is still the subsequent quantum gate. At this time, g6 is blocked from moving forward, but according to the exchange rules in the literature cited in the present invention, g1 can exchange execution timing with g3 and g6 in turn. Fig.16 In this example, all subsequent quantum gates have been converted to prior quantum gates, and q1 has been converted into a reusable quantum bit, enabling it to replace q3.

[0165] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A quantum circuit width optimization method based on quantum bit reusable transformation, characterized in that: The following steps are involved: Step S1: define quantum bit multiplexing conditions; Step S2: performing quantum circuit division; Step S3: determining the reusable quantum bits; Step S4: Identify the preceding quantum gate and the succeeding quantum gate acting on the non-reusable quantum bit; Step S5: Formulate a quantum bit reusable transformation strategy; Step S6: Convert the subsequent quantum gate into the preceding quantum gate.

2. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 1, characterized in that: Step S1 is specifically as follows: In a quantum circuit, let Q be the set of its quantum bits, Q = {q0,...,q i ,...,q n-1 }; Among them: q0 represents the quantum bit with index order 0, q j represents the quantum bit with index order j, q n-1 represents the quantum bit with index order n-1, where n represents the total number of quantum bits; G is the set of its quantum gates, G = {g0,...,g j ,...,g m-1 }; Where: g0 represents the quantum gate with index order 0, g represents the quantum gate with index order j, and g m-1 represents the quantum gate with index order m-1, where m represents the total number of quantum gates; Formulate the definition: For two different quantum bits q in a quantum circuit i ,q j If you can reuse q i Make it a replacement for q j , then q i ,q j The quantum bit pair [q i ,q j ] is a valid reuse pair; if it is not possible to reuse q i Make it a replacement for q j , then q i ,q j The quantum bit pair [q i ,q j ] is an invalid reuse pair; where q i represents the quantum bit with index order i, q j Represents the quantum bit with index order j, and i≠j.

3. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 1, characterized in that: Step S2 is specifically as follows: The timing partitioning method is a method used to analyze the execution of quantum gates in quantum circuits and to analyze and determine the reusability of quantum bits; The time-series partitioning method first converts the quantum circuit into a directed acyclic graph: Directed Acyclic Graph: DAG, performs topological sorting on the DAG, and obtains a topologically ordered sequence of nodes in the DAG; The N quantum gates in the circuit are then divided into N time steps according to the order in the topologically ordered sequence.

4. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 1, characterized in that: Step S3 is specifically as follows: For a quantum bit pair [q i ,q j ], to determine whether there is a two-qubit gate acting on qubit q simultaneously i and q j ; If there is a two-qubit gate that acts on qubit q simultaneously i and q j , then q cannot be reused i Make it a replacement for q j , that is [q i ,q j ] is an invalid multiplexing pair; If there is no two-qubit gate acting simultaneously on qubit q i and q j , then judge all the actions on q i Are the execution timings of the quantum gates on q all prior to all the gates acting on q? j The execution timing of the quantum gates on ; If all actions on q i The execution order of the quantum gates on q j The execution sequence of quantum gates on q i Make it a replacement for q j ; Otherwise, q cannot be reused i Make it a replacement for q j .

5. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 4, characterized in that: Step S4 is specifically as follows: In the circuit after timing division, for q i Non-reusable quantum bit pair [q i ,q j ]; The execution sequence precedes all actions on q j The quantum gate acts on q i The gate is called the first quantum gate; The execution sequence is any one acting on q j Behind the gate and acting on q i The gate is called a backward quantum gate; Since the execution sequence of the subsequent quantum gate does not satisfy q i Reusability condition requires converting all subsequent quantum gates into prior quantum gates; In the process of converting the subsequent quantum gate into the preceding quantum gate, it is necessary to make an equivalent transformation on the quantum circuit; Therefore, the conversion process of the subsequent quantum gate into the preceding quantum gate is actually the process of equivalent transformation of the quantum circuit, making q i Meeting the reusability condition means achieving q i Reusable quantum circuit equivalent transformation.

6. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 5, characterized in that: Step S5 is specifically as follows: For a quantum bit pair [q i ,q j ], if a post-gate can be transformed by equivalent circuits, its execution sequence is prior to all gates acting on q j quantum gate, then this backward gate can be converted into a forward gate; For a quantum bit pair [q i ,q j ], if a post-gate cannot be transformed by equivalent circuits to make its execution sequence precede all gates acting on q j quantum gate, then this subsequent gate cannot be converted into a preceding gate, q i The reusability condition cannot be met.

7. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 6, characterized in that: Step S6 is specifically as follows: S61: Locate the quantum gate whose execution sequence is before the current quantum gate and the closest to the current quantum gate. j Quantum gates; S62: moving forward the execution timing of the current subsequent quantum gate; If the execution sequence of the current subsequent quantum gate precedes the action on q located in S61 j If there is a quantum gate, check whether the current subsequent quantum gate has been converted into the preceding quantum gate; If the current subsequent quantum gate has been converted to the preceding quantum gate, the circuit transformation is terminated; If it is not converted to the preceding quantum gate, return to S61; If the current backward quantum gate cannot move the execution sequence forward, then enter S63; S63: Move back the positioning effect in S61 to q j The execution timing of quantum gates; If the execution sequence of the current subsequent quantum gate precedes the action on q located in S61 j If there is a quantum gate, check whether the current subsequent quantum gate has been converted into the preceding quantum gate; If the current subsequent quantum gate has been converted to the preceding quantum gate, the circuit transformation is terminated; If the current subsequent quantum gate has not been converted into a preceding quantum gate, then return to S61; If it is not possible to move the positioning action in S61 backward to q j The execution sequence of the quantum gate of q makes the execution sequence of the current subsequent quantum gate precede that of the gate acting on q j The execution sequence of the quantum gate ends the circuit transformation, q i The reusability condition is not met.

8. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 7, characterized in that: For a quantum bit pair [q i ,q j ], in order to make q i If the reuse condition is met, the above strategy can be executed sequentially for the subsequent quantum gates in the circuit until all subsequent quantum gates are converted into the preceding quantum gates; If the circuit cannot convert the subsequent quantum gate into the preceding quantum gate during a certain equivalent transformation, the circuit transformation is terminated, and the quantum bit pair [q i ,q j ] is an invalid reuse pair, i.e., q cannot be reused i Alternative to q j ; If several equivalent transformations are performed on the line, acting on q i ,q j The execution sequence of the quantum gate satisfies q i If the multiplexing condition is met, the line conversion is also terminated and q can be reused. i Alternative to q j .

9. A quantum circuit width optimization method based on quantum bit reusable transformation according to claim 2, characterized in that: Quantum gates are quantum gates that can be executed in real quantum computing hardware.

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