Quantum error mitigation acceleration method and accelerator using sparsity in tensor product

Abstract

The invention discloses a quantum error mitigation acceleration method and accelerator using sparsity in a tensor product, and belongs to the technical field of quantum computation.The method comprises the steps that a quantum error mitigation conversion equation is established; the quantum error mitigation conversion equation is divided into three steps of operation of matrix-vector multiplication, tensor product and multiplication accumulation; sparsity acceleration is realized based on the output sparsity and the input sparsity; executing probability-level and state-level parallel computing on the tensor product operation to realize parallelism acceleration based on sparsity; and alternately executing row main sequence and column main sequence generation operation on the tensor product operation in an iteration round to realize operation fusion acceleration based on sparsity and parallelism. According to the method, the calculation efficiency and fidelity of the quantum read-out error mitigation method can be improved, so that the development and application of the quantum calculation technology are further promoted.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically relating to a quantum error mitigation and acceleration method and accelerator that utilizes the sparsity in tensor products. Background Technology

[0002] Quantum computers, as a revolutionary advancement in information technology, have demonstrated significant advantages over classical computers in solving certain types of problems, such as combinatorial optimization and machine learning. However, current quantum computers primarily handle the computation, while other operations, such as encoding, decoding, and post-processing, still rely on classical computers. Many claims of "quantum acceleration" often ignore the latency issues of classical computers, which may prevent the realization of end-to-end acceleration. To implement an end-to-end quantum accelerator, it is necessary to consider not only the encoding and compilation process of qubits but also many peripheral processes that depend on classical computation. Given the heterogeneous and decoupled architecture of quantum computers, peripheral accelerators are crucial for achieving true quantum advantage. Among these processes, quantum error mistigation (QEM) is widely considered a major bottleneck in realizing quantum accelerators. To overcome this challenge, precise calibration of noise errors is essential to ensure high-fidelity output results.

[0003] To address this challenge, academia and industry are actively exploring solutions at both the software and hardware levels. At the software level, researchers are developing various algorithms and techniques to improve the efficiency and accuracy of readout error mitigation. For example, they are reducing readout crosstalk errors by measuring subsets of qubits, using Hamming weight maps and iterative Bayesian networks for modeling, and employing bit flipping techniques to compensate for the probability of reading "1". While these methods alleviate the readout error problem to some extent, they still face challenges of high computational complexity and resource consumption. At the hardware level, researchers are dedicated to designing more efficient readout circuits and discriminators to improve the accuracy of single-qubit state discrimination. The hardware discriminator in the HERQULES project is a typical example, utilizing the trajectory information of the readout frequency to improve discrimination accuracy. Furthermore, the SpREM project proposed a hardware-software co-design method aimed at reducing computational complexity by leveraging the Hamming sparsity in the mitigation matrix. While these methods have made some progress, further optimization and refinement are needed to achieve more efficient and accurate readout error mitigation.

[0004] Beyond software and hardware efforts, improving the fidelity of error mitigation remains a major research challenge. This includes structure-based error mitigation methods, deep learning-based methods, and algebraic methods. Algebraic error mitigation, a white-box and formal approach, has proven effective in superconducting and optical quantum hardware. This approach can be further divided into matrix-based error mitigation and iterative tensor product-based methods. Matrix-based error mitigation achieves this by multiplying a noisy probability vector by a mitigation matrix, making the probability distribution closer to the ideal distribution. However, as the number of qubits increases, the matrix size grows exponentially, leading to a sharp increase in computational workload and memory requirements. Tensor product-based methods are essentially approximations of matrix-based methods, aiming to reduce the computational workload caused by the exponential growth in matrix size. Although tensor product-based mitigation methods are software-friendly and experimentally effective, they inevitably face the dilemma of balancing latency and fidelity, especially in large-scale quantum systems where the increased mitigation time and memory requirements are key factors limiting their application.

[0005] In summary, the current approach to quantum readout error mitigation utilizes the sparsity of tensor products to provide a new acceleration method for quantum error mitigation. However, existing techniques mainly rely on intermediate data pruning or threshold pruning strategies. These methods are limited by the limited hardware resources of quantum accelerators and the loss of fidelity in practical applications. Therefore, it is necessary to further improve the computational efficiency and fidelity of mitigation methods to further promote the development and application of quantum computing technology. Summary of the Invention

[0006] In view of the above, the purpose of this invention is to provide a quantum error mitigation acceleration method and accelerator that utilizes the sparsity in tensor products. The method utilizes the inherent sparsity of Hilbert space to achieve quantum error mitigation acceleration. The key is that the superposition state generated by the quantum algorithm covers only a subset of the Hilbert space (output sparsity), while the ground state naturally exhibits bit-level sparsity (input sparsity). By effectively skipping zero-value-related calculations through a sparse data stream characterized by probabilistic and state-level parallelism, and by designing a hardware architecture that supports various tensor product calculation paradigms, end-to-end acceleration is achieved to reduce readout errors.

[0007] To achieve the above-mentioned objectives, the present invention provides the following technical solution: This invention provides a quantum error mitigation and acceleration method utilizing the sparsity in tensor products, comprising the following steps: The noise probability vector read from the quantum is multiplied by the mitigation matrix to establish the quantum error mitigation transformation equation. The mitigation matrix is ​​divided into several sub-mitigation matrices, and the fundamental vector of the noise probability vector is divided into qubits corresponding to the several sub-mitigation matrices. The quantum error mitigation transformation equation is divided into three steps: matrix-vector multiplication, tensor product, and multiplication accumulation. Matrix-vector multiplication performs multiplication between the mitigation matrix and the fundamental vector and flattens it to obtain the intermediate value. Tensor product performs tensor product calculation of the intermediate value to obtain the intermediate vector and flattens it to obtain the intermediate matrix. Multiplication accumulation performs multiplication and accumulation between the intermediate matrix and the noise probability vector to obtain the mitigation probability vector as the output. Based on the output sparsity of the mitigation probability vector, the non-zero elements are pre-acquired to capture the elements that need to be multiplied and accumulated, and backtracked to the tensor product operation and multiplication accumulation operation. Based on the input sparsity of the basic vector, the matrix-vector multiplication is transformed into directly extracting the columns in the mitigation matrix, thereby accelerating the sparsity. The intermediate vector in the tensor product operation is simultaneously computed in parallel by row and in parallel by column to generate the rows and columns of the intermediate matrix, respectively, thus achieving parallelism acceleration based on sparsity. The tensor product operation is performed alternately in row-major and column-major order to generate intermediate matrices in iteration rounds, thereby reducing the waiting time of the multiplication accumulation operation between adjacent iteration rounds and achieving operation fusion acceleration based on sparsity and parallelism.

[0008] Preferably, the step of multiplying the noise probability vector of the quantum readout with the mitigation matrix to establish the quantum error mitigation transformation equation includes: The matrix-based quantum error mitigation method multiplies the noise probability vector from the quantum readout with the mitigation matrix to obtain the mitigated probability vector, thus approximating the ideal probability vector. The quantum error mitigation transformation equation is expressed as follows: , in, This represents the mitigation probability vector. Represents the mitigation matrix. This represents the noise probability vector.

[0009] Preferably, the step of dividing the mitigation matrix into several sub-mitigation matrices and dividing the fundamental vector of the noise probability vector into qubits corresponding to the several sub-mitigation matrices includes: By employing a quantum error mitigation method based on tensor products, the mitigation matrix in the quantum error mitigation transformation equation is transformed... Divided into Subgroup Relief Matrix Then the quantum error mitigation transformation equation is transformed into: , in, This represents the mitigation probability vector. Represents the noise probability vector. Represents the tensor product; noise probability vector basic vectors Further segmentation into and The qubits corresponding to the group relief matrix Then the quantum error mitigation transformation equation is transformed into: , in, Represents the fundamental vector The noise probability vector in the state. Indicates after the measurement of the quantum bit The set of fundamental vectors with zero probability in non-zero-probability vectors.

[0010] Preferably, the step of pre-acquiring non-zero elements from the output sparsity of the probability vector to capture elements requiring multiplication and accumulation, and backtracking to the tensor product operation and multiplication-accumulation operation, includes: Based on the output sparsity of the mitigation probability vector, the non-zero elements in the mitigation probability vector are obtained in advance. For each non-zero element, the multiplication and accumulation operations are backtracked to determine the elements that need to be multiplied and accumulated. Furthermore, the tensor product operation steps are backtracked to determine the elements that need to be operated on.

[0011] Preferably, the input sparsity based on the fundamental vector transforms matrix-vector multiplication into directly extracting columns from the mitigation matrix, including: In quantum systems, the fundamental vectors are represented as unit vectors. By identifying the non-zero indices in the fundamental vectors, matrix-vector multiplication operations are transformed into selecting the corresponding columns directly from the relief matrix based on the non-zero indices.

[0012] Preferably, the step of simultaneously performing row-parallel computation and column-parallel computation on the intermediate vector in the tensor product operation to generate the rows and columns of the intermediate matrix respectively includes: In tensor product operations, orthogonal probabilistic parallelism and state-level parallelism are identified. Probabilistic parallelism involves parallel computation of multiple intermediate vectors, while state-level parallelism involves parallel computation of multiple elements in each intermediate vector. Based on probabilistic parallelism, row-by-row parallel computation of each row element is performed on the intermediate vector in tensor product operations. Simultaneously, based on state-level parallelism, column-by-column parallel computation of each column element is performed on the intermediate vector in tensor product operations. This generates a block of the intermediate matrix in each computation cycle, and finally outputs the entire intermediate matrix.

[0013] Preferably, if the operands and row indices are the same for the values ​​of the same row in each slice, then operand reuse and index reuse are performed accordingly when calculating the values ​​of the same row in each slice.

[0014] Preferably, the tensor product operation is performed alternately in row-major and column-major order to generate the intermediate matrix in each iteration cycle to reduce the waiting time of the multiplication accumulation operation between adjacent iteration cycles, including: In the current iteration, the tensor product operation generates the intermediate matrix row by row in row-major order, and in the next iteration, the tensor product operation generates the intermediate matrix column by column in column-major order. Therefore, the multiplication and accumulation operation can be executed independently after the tensor product operation in the next iteration without waiting for all multiplication and accumulation operations in the current iteration to be completed.

[0015] To achieve the above-mentioned objectives, this invention also provides a quantum error mitigation accelerator that utilizes the sparsity in tensor products, based on the above-mentioned quantum error mitigation acceleration method utilizing the sparsity in tensor products, and includes: a matrix-vector multiplication computation unit, a tensor product computation unit, a multiplication accumulation computation unit, and a memory. The matrix-vector multiplication calculation unit is used to perform column selection operations on the relief matrix based on the strings in the base vector, obtain the columns of the relief matrix and flatten them into intermediate values; The tensor product calculation unit is used to process the tensor product data stream in a probabilistic parallel and state-level parallel manner, calculates the intermediate vector and flattens it into an intermediate matrix. The multiplication and accumulation calculation unit is used to receive the results from the tensor product calculation unit in a block-to-block manner. Each intermediate matrix block is generated in row-major order or column-major order and multiplied with the noise probability vector. The results of different blocks are accumulated and aggregated to obtain the mitigation probability vector as the output. The memory is used to store the input mitigation matrix and the output mitigation probability vector, respectively.

[0016] Preferably, in the matrix-vector multiplication calculation unit, a cascaded multiplexer is designed to select strings in the basic vectors and operate in a cascaded structure; in the tensor product calculation unit, a processing unit including a multiplier and a decomposer is designed. The multiplier is used to perform tensor product calculation, and the decomposer is used to select the input operands or intermediate results of the tensor product operation and to configure the output path to select whether to output the calculation result directly or to transmit it to the next processing unit through a register.

[0017] Compared with the prior art, the beneficial effects of the present invention include at least the following: (1) This invention divides the computation into three operators: matrix-vector multiplication, tensor product and multiplication accumulation, thereby identifying opportunities for inherent sparsity acceleration. By constructing an efficient sparsity-relieved data stream, it can achieve sparsity acceleration based on output sparsity and input sparsity. On this basis, it can achieve parallel acceleration based on probability level and state level, and further achieve iterative acceleration based on row-major order and column-major order, thereby achieving high data reuse and high throughput, thus effectively reducing computational load and improving computational efficiency.

[0018] (2) By designing a special accelerator hardware architecture, this invention can connect the sparse mitigation data flow in the acceleration method. By designing a cascaded multiplexer in the matrix-vector multiplication calculation unit, it can optimize the processing efficiency of sparse data flow, reduce invalid calculations, and improve the resource utilization of the calculation unit. By designing a reconfigurable processing unit in the tensor product calculation unit, it can dynamically respond to various parameter configurations in the iterative tensor product, realize the efficient utilization of hardware resources and the flexible allocation of calculation tasks, and improve the overall calculation efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of a quantum error mitigation and acceleration method utilizing the sparsity in tensor products provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the quantum readout error mitigation calculation process based on iterative tensor product provided in an embodiment of the present invention; Figure 3 This is a schematic diagram comparing the sparsity of delayed decomposition based on the BV algorithm and the quantum algorithm provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the sparse mitigation data flow for parallelized tensor product operations provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the simultaneous use of two parallelization strategies involving four non-zero probability basic states, as provided in an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the fusion of MVM, TP, and MAC operations provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the overall architecture design of the SiTA accelerator provided in an embodiment of the present invention; Figure 8This is a schematic diagram showing the structural details of the cascaded multiplexer provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of dynamic multiplier chains with different tensor product configurations provided in the embodiments of the present invention; Figure 10 This is a schematic diagram illustrating the acceleration effect of the SiTA accelerator relative to a baseline provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the accelerated ablation study results provided in an embodiment of the present invention; Figure 12 This is a schematic diagram showing the comparison of throughput and performance of the SiTA accelerator relative to a baseline provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of this invention.

[0022] The inventive concept of this invention is to address the insufficient computational efficiency and fidelity of existing quantum readout error mitigation methods. This invention provides a quantum error mitigation acceleration method and accelerator that utilizes the sparsity of tensor products. By dividing the general mitigation process into three operations—matrix-vector multiplication (MVM), tensor product (TP), and multiplication-accumulation (MAC)—two sparse opportunities for acceleration are identified: output sparsity and input sparsity. Based on these two sparsity modes, a sparse mitigation data stream with probabilistic and state-level parallelism is proposed, utilizing these sparsity characteristics to optimize the computational path. Finally, these operators are fused to achieve overall acceleration, and an accelerator architecture is designed to implement this data stream. This results in significant parallelism and data reuse characteristics, effectively skipping zero-value calculations, thereby greatly improving computational efficiency and achieving high performance while maintaining good error mitigation fidelity.

[0023] Figure 1 This is a schematic flowchart of a quantum error mitigation and acceleration method utilizing the sparsity in tensor products provided in an embodiment of the present invention. Figure 1 As shown, the embodiment provides a quantum error mitigation and acceleration method utilizing the sparsity in tensor products, including the following steps: S1, multiply the noise probability vector read from the quantum by the mitigation matrix to establish the quantum error mitigation transformation equation, divide the mitigation matrix into several sub-mitigation matrices and divide the fundamental vector of the noise probability vector into qubits corresponding to the several sub-mitigation matrices.

[0024] When measuring a qubit, the readout noise will be an ideal probability vector (i.e., an ideal probability distribution). Mapped to the noise probability vector (i.e., the noise probability distribution) noise matrix It is The matrix needs This measurement characterizes it. Conversely, in this embodiment, the matrix-based quantum error mitigation method reduces noise errors by multiplying the noise probability vector from the quantum readout by the mitigation matrix to obtain the mitigated probability vector, thus making the noise probability vector approximate the ideal probability vector. The quantum error mitigation transformation equation is expressed as follows: , in, This represents the mitigation probability vector. Represents the mitigation matrix. , This represents the noise probability vector.

[0025] In this embodiment, a quantum error mitigation method based on tensor product is further used to transform the mitigation matrix in the quantum error mitigation transformation equation. Based on the division into qubits Subgroup Relief Matrix Then the quantum error mitigation transformation equation is transformed into: , in, Represents the tensor product.

[0026] Further dividing the qubit into noise probability vectors basic vectors Further segmentation into and The qubits corresponding to the group relief matrix Then the quantum error mitigation transformation equation is transformed into: , in, Represents the fundamental vector The noise probability vector in the state. Indicates after the measurement of the quantum bit The set of fundamental vectors with zero probability in non-zero-probability vectors.

[0027] Taking 4 qubits as an example, Represented as: , The next step is to divide the four qubits into three groups. The relief process is described as follows: , in, This refers to the first two qubits, while and These refer to the 3rd and 4th qubits, respectively. According to the above process, the embodiment involves further operations based on iterative tensor product.

[0028] S2 divides the quantum error mitigation transformation equation into three steps: matrix-vector multiplication, tensor product, and multiplication accumulation. Matrix-vector multiplication performs multiplication between the mitigation matrix and the fundamental vector and flattens it to obtain the intermediate value. Tensor product performs tensor product calculation of the intermediate value to obtain the intermediate vector and flattens it to obtain the intermediate matrix. Multiplication accumulation performs multiplication and accumulation between the intermediate matrix and the noise probability vector to obtain the mitigation probability vector as the output.

[0029] like Figure 2 As shown, taking 4 qubits as an example, the embodiment first inputs the fundamental vector... The mitigation operation is decomposed into three tensor operations: matrix-vector multiplication (MVM), tensor product (TP), and multiplicative accumulation (MAC). The matrix-vector multiplication (MVM) operation refers to the multiplication between the mitigation matrix and the fundamental vector. For example, in the mitigation process of the above four qubits, , , among them This represents all elements. Considering the static grouping scheme, the overall computational complexity is determined by the non-zero probability... The decision is made. The tensor product (TP) operation is performed on the vector after the MVM step, generating a matrix that can be flattened into an intermediate matrix. of (An intermediate vector, representing the combination of the measured non-zero probability ground states (fundamental vectors). Each non-zero probability state...) Responsible for a series of tensor products, such as Figure 2 In Each non-zero probability requires This multiplication operation accounts for a significant portion of the computational complexity. Most of it. Then, the multiplicative accumulation (MAC) operation multiplies the intermediate matrices to output a mitigated probability vector as the mitigated probability result: .

[0030] S3 pre-acquires non-zero elements based on the output sparsity of the mitigation probability vector to capture the elements that need to be multiplied and accumulated, and backtracks to the tensor product operation and multiplication accumulation operation. Based on the input sparsity of the basic vector, matrix-vector multiplication is converted into directly extracting columns from the mitigation matrix to achieve sparsity acceleration.

[0031] Following the computational scheme based on the iterative tensor product method, sparsity is further utilized to accelerate the computation process. The sparse scheme is divided into output sparsity and input sparsity.

[0032] (1) Output sparsity. Output mitigation probability vector. Essentially sparse, the superposition states generated by quantum algorithms occupy only a portion of the Hilbert space. For example, some simple quantum algorithms generate only a few non-zero probability ground states, exhibiting high sparsity: the 16-qubit BV algorithm (Bernstein-Vazirani) achieves 98.6%, and the 16-qubit GHZ algorithm (Greenberger-Horne-Zeilinger) achieves 96.7%, such as... Figure 3 As shown in (b) of the diagram, iter on the horizontal axis represents the number of iterations, and q represents the number of qubits. Furthermore, as the number of iterations increases, the variational quantum algorithm typically converges to a specific quantum state, resulting in a highly sparse output probability distribution. Figure 3 In (b) of the example, when the number of iterations reaches 40, the sparsity of the 10-qubit VQE algorithm (Variational Quantum Eigensolver), the 10-qubit QAOA algorithm (Quantum Approximate Optimization Algorithm), and the 10-qubit FALQON algorithm (Feedback-based Adaptive Learning Quantum Optimizer) are 65.5%, 80.4%, and 75.3%, respectively. Since the ideal probability distribution is usually within the range of the noise probability distribution, in this embodiment, output sparsity is identified by calculating only the non-zero probability elements in the noise probability vector. Specifically, this involves pre-obtaining the non-zero elements in the mitigation probability vector, backtracking to the multiplication and accumulation operations based on each non-zero element to determine the elements requiring multiplication and accumulation, and further backtracking to the tensor product operation step to determine the elements requiring tensor product operations. Pruning the mitigation vector leads to higher accuracy because the overall probability distribution is more concentrated within the ideal range. Through pruning the mitigation vector test, the fidelity of the 12-qubit BV algorithm improved from 0.59 to 0.63. From an arithmetic perspective, recognizing output sparsity can reduce... Figure 2 The complexity of the tensor product (TP) and multiply-accumulate (MAC) operations is shown.

[0033] (2) Input sparsity. The fundamental vectors (ground states) in a quantum system are typically represented as unit vectors, where each vector contains only one 1 element and the rest are 0. Therefore, input sparsity is essentially bit-level sparsity, for example... Figure 2 In Leveraging this sparsity, the matrix-vector multiplication (MVM) operation is transformed into selecting a column from the relief matrix, determined by the non-zero indices in the fundamental vectors. For example... Figure 3 As shown in (a), this utilization of sparsity significantly reduces the computational load of MVM operations by 85.7%. Figure 3 In (a) of the paper, the total redundant computation involving input and output sparsity was analyzed, and the result was 91.2%, which highlights the great potential for optimization and shows that further improvements can significantly improve performance and reduce unnecessary computational overhead.

[0034] S4 performs parallel row-wise and parallel column-wise computations on the intermediate vector in the tensor product operation to generate the rows and columns of the intermediate matrix respectively, achieving parallel acceleration based on sparsity.

[0035] In the embodiments, parallelism is further identified in the error-mitigated sparse data stream. Orthogonal probabilistic parallelism and state-level parallelism are identified in the tensor product (TP) operation. Probabilistic parallelism involves parallel computation of multiple intermediate vectors. State-level parallelism involves parallel computation of multiple elements within each intermediate vector, by flattening the intermediate vector obtained from the TP operation into a single state. The intermediate matrix This is equivalent to dividing the output matrix into blocks and calculating the elements in parallel. For example... Figure 4 As shown in (a), the probabilistic parallel processing of the intermediate matrix... Two elements in and Parallel computing, based on the tensor product principle, means that the computation of these two elements is independent of each other, and requires obtaining six different elements from the input vector. , This method outputs rows of an intermediate matrix, allowing MAC operations with noisy probability vectors to generate mitigated probability values ​​independently. For example... Figure 4 As shown in (b), the state-level parallel computation computes the elements of the same intermediate vector, that is, different quantum states of the same intermediate vector. , This parallelization is responsible for generating the columns of the intermediate matrix. It can reuse input elements, leveraging the inherent data reuse property in tensor product operations, such as... and Reused for calculation and Therefore, interconnect resources between PEs (processing elements) and on-chip memory are needed to allow for the broadcasting of input elements. Considering the use of both parallelization strategies, a chunk of the intermediate matrix will be generated within one cycle, using lateral parallelism. and vertical parallelism These represent the parallelism in the probability level and state level dimensions, respectively.

[0036] Parallelization is essentially a dense data stream; in this implementation, sparsity and parallelism are combined for acceleration, such as... Figure 5 As shown.

[0037] First, we utilize the sparsity of the output, and the specific steps are as follows: (1) Backtracking the intermediate matrix Non-zero values ​​in the vector are used to control redundant computations caused by the sparsity of the probability vector. Figure 5 For example, consider four non-zero probability ground states: "0000", "0010", "1101", and "1110". The intermediate matrix... Lines 0 (0000), 2 (0010), 13 (1101), and 14 (1110) are compressed.

[0038] (2) Identify the operands of the tensor product based on the row index and the grouping scheme of the qubits. For example, The row index is .according to Grouping schemes can track median values ​​(matrix) The index of the operand in ) , , .

[0039] (3) The intermediate matrix Compressed into a dense matrix with row indices, it can still achieve parallel computation of tensor products and compute non-zero outputs.

[0040] (4) In the matrix Columns and vectors MAC operations are performed between non-zero probability ground states. .

[0041] When tracking non-zero elements, a block-based parallelization strategy allows for the reuse of indices and operands, mitigating the problem of frequent output probability updates. For values ​​within the same row of a block, the row indices required for their operands are the same. For example, in... Figure 5 middle, and All share indexes Therefore, each block can reuse a set of decoded indices. Similarly, for values ​​in the same column within a block, the required operands come from the same index. For example, and The tensor product all used and Therefore, each block can reuse the result of matrix-vector multiplication. This approach leverages the sparsity of outputs through block-based parallel computing, while simultaneously enabling index and operand reuse.

[0042] Next, we will leverage the sparsity of the input, with the following specific steps: (1) Obtain the corresponding sub-ground states from the ground state according to the grouping scheme. For example... Figure 5 According to Grouping scheme, Divided into , , .

[0043] (2) Based on its normalization property, the number represented by the ground state points to the position of 1 in the basis vectors. For example, in In the text, "11" represents the number 3, indicating The third element is 1. .

[0044] (3) Based on the position of "1", the columns of the mitigation matrix can be directly extracted from the ground state to complete the matrix-vector multiplication (MVM) operation, as follows: , By leveraging bit-level sparsity to directly extract columns of the mitigation matrix, matrix-vector multiplication (MVM) operations can be skipped, thus saving computational resources and time.

[0045] S5 performs row-major and column-major calculations alternately in iterations to generate intermediate matrices for tensor product operations, thereby reducing the waiting time of multiplication accumulation operations between adjacent iterations and achieving operation fusion acceleration based on sparsity and parallelism.

[0046] Building upon sparsity and parallelism acceleration, a further acceleration scheme involving operation fusion is implemented. During iterative error mitigation, the MAC operation can be pipelined with MVM and TP operations because it is element-wise computed. However, this requires multiple iterations to improve fidelity, involving complex data dependencies between different iterations. The output of the MAC operator in the previous iteration serves as the input for the next iteration. Since the output generation sequences differ, two iterations cannot directly overlap, such as... Figure 6 As shown in (a) in the example. In this embodiment, through the intermediate matrix This problem is solved by swapping blocks, which helps reduce the waiting time between iterations. Specifically, during the first iteration ( Iter.1 It generates the intermediate matrix row by row in a row-major order, i.e., Z-order. During the second iteration ( Iter.2 It switches to column-major order, i.e., N-order, as shown in Figure 6. By doing so, the three operators are successfully merged, ensuring data independence. Matrix and The blocks are computed simultaneously, and then the MAC phase is performed independently, without waiting for all MAC operators in the first iteration to complete. This reduces the waiting time for MAC operators between iterations, such as... Figure 6 As shown in (b), for an 8×8 intermediate matrix size, the waiting time is reduced from 64 cycles to 8 cycles, which significantly improves the efficiency of iterative computation.

[0047] Based on the same inventive concept, embodiments of the present invention also provide a quantum error mitigation accelerator (named SiTA) that utilizes the sparsity in tensor products to achieve fast and accurate quantum readout error mitigation. Figure 7 The overall accelerator architecture design of SiTA is demonstrated. It consists of memory and three computation modules, which organize the computation process in a fully pipelined manner. These modules include: a matrix-vector multiplication unit (MVM unit), a tensor product unit (TP unit), a multiplication-accumulation unit (MAC unit), and memory (including SRAM for the input matrix and SRAM for the output vector). The MVM unit performs column selection operations on the relief matrix based on strings in the base vector, obtaining the columns of the relief matrix and flattening them into intermediate values. The MAC unit processes the tensor product data stream in probabilistic and state-level parallelism, calculating intermediate vectors and flattening them into intermediate matrices. The MAC unit receives the results from the MAC unit in a block-by-block manner. Each block of the intermediate matrix is ​​generated in row-major or column-major order and multiplied by the noise probability vector. The results of different blocks are accumulated and aggregated to obtain the relief probability vector as the output. The memory stores the input relief matrix and the output relief probability vector separately.

[0048] The hardware module accepts configurable parameters, supporting error mitigation at different granularities, such as different grouping schemes and iteration counts. Memory hierarchy: Inputs include 1) a mitigation matrix, 2) a non-zero noise probability vector, and 3) a base vector of non-zero probabilities. After dividing the qubits into multiple groups, the mitigation matrix becomes relatively small and can be pre-stored in on-chip memory. On the other hand, the non-zero noise probability vector is dynamic and varies depending on the circuitry and the measured qubits. Therefore, in this embodiment, the non-zero noise probability vector and its base vector are streamed through two independent channels, such as... Figure 7As shown. The on-chip memory system includes two main SRAMs (Static Random Access Memory): one for the relief matrix (64KB) and the other for the relief probability vector (16KB). For easy access to the random vector, the relief matrix can be stored in different repositories, up to four in total. The 16KB output memory holds the relief probability vector, allowing for up to 8K non-zero FP16 (16-bit floating-point) probability data, sufficient to accommodate the results of current quantum algorithms and quantum devices.

[0049] like Figure 7 The document also provides an example of memory behavior when handling the 128-qubit BV algorithm, explaining several fundamental hardware terms: Controller Interface represents the communication bridge with external controllers (such as CPU, DMA, etc.), responsible for protocol conversion and command parsing; Access Control Logic represents the execution of control logic for data read and write operations; Broadcast represents copying data multiple times and sending it in parallel to multiple PEs for reception; Sub-index Buffer represents the memory area that buffers sub-index data; Accumulation represents summing multiple intermediate data; Input Buffer represents the memory area that buffers input data. Figure 7 In the process, the noise probability vector contains 2896 non-zero values. A grouping scheme of dividing 128 bits into 64 groups is used to obtain 64 4×4 matrices for iterative tensor product. The mitigation matrix requires 16KB (4×2×2KB) of on-chip memory, containing two groups of 64×4×4 mitigation matrices. In one cycle, the four fundamental vectors enter a 512b index buffer (128b×4) for the decoding stage. The decoding result is used as a read signal to obtain column vectors from the SRAM matrix. After the tensor product calculation is completed through the dynamic multiplier chain, 512b (2×16×16b) of memory is required to store the chunks of the two intermediate matrices. The final result is transferred off-chip via 6KB of output SRAM (2896×16b).

[0050] In the various computing units of the SiTA accelerator, the MVM computing unit consists of two register arrays and a cascaded multiplexer. It leverages bit-level sparsity to read a series of binary strings of fundamental states and determine which column needs to be sent to the mitigation matrix, thus implementing a column selection operator. The TP computing unit is a key computing engine involving multiple processing units (PEs). It receives columns from the mitigation matrix and, based on the qubit grouping scheme (e.g., ...), ... , , The unit selects elements and then parallelizes the sparse tensor product data stream in a probabilistic and state-level parallel manner. The MAC computation unit receives the results from the TP computation unit in a block-to-block manner. Each block is multiplied by the noise probability vector in MAC-Z or MAC-N order. Finally, the results from different blocks are aggregated to output the mitigated vector.

[0051] Since the measured qubits and their non-zero probabilities are dynamically determined by the target circuit, a cascaded multiplexer was designed and developed in the MVM computing unit in this embodiment to load arbitrary binary strings from the ground state. Clearly, the entire quantum state space is... However, only a very small number of these sparsities have a non-zero probability. Therefore, multiplexers are used to identify their indices, allowing for precise location of non-zero values ​​within the input sparsity. For example... Figure 8 As shown, a set of multiplexers is applied to select binary strings from the base vectors respectively, working in a cascaded structure, which achieves a trade-off between latency (which can overlap with computation) and area. Figure 8 An example of extracting the 68th bit from a 128-qubit ground state using a cascaded multiplexer is shown. This cascaded multiplexer consists of four levels, including three 4-to-1 multiplexers (4-to-1 MUX) and one 2-to-1 multiplexer (2-to-1 MUX), to select the appropriate bit string at each level. Furthermore, four dividers are used to generate the selection signals for the multiplexers. For the 68th bit, the 128-bit ground state is divided into four 32-bit binary strings, stored in four registers (…). Figure 8 In (represented in 32-bit), these registers serve as inputs to a 4-to-1 multiplexer. The selection signal is obtained by calculating ⌊68 / 32⌋, pointing to the binary string from bit 64 to bit 95, the division sign... This represents the divider. The remaining 4 bits will go to the next stage and operate in a similar manner, selecting the binary string between the 64th and 71st qubits. Based on this process, the 68th bit (q) of the binary string can be obtained. 68 This provides an index for column extraction. Furthermore, this cascaded multiplexer can be adapted to quantum systems with varying numbers of qubits via a cascaded selection method.

[0052] Furthermore, a dynamic multiplier chain was designed in the processing unit. The number of qubits and the grouping scheme of different quantum hardware vary according to the readout frequency of each qubit, resulting in a dynamic change in the number of multiplications in the tensor product operator. To accommodate different quantum devices, a flexible processing unit (PE) was designed in the embodiment, consisting of four multipliers (for computation) and five demultiplexers. Their configuration signals are generated by software-level control, based on the number of qubits and the corresponding grouping strategy, ensuring the generation of appropriate control signals. Specifically, demultiplexer C0 is used to select the data source between intermediate results from other PEs and the operands of the tensor product. Similarly, demultiplexers C1, C2, and C3 select the operands of the tensor product to achieve continuous multiplication. Demultiplexer C4 determines whether to output the computation data or transfer the data to the next PE via a register, such as... Figure 9 As shown. Figure 9 (a) shows the division of the 4-qubit system into 3 groups The PE configuration details involve two multiplication operations. The tensor product calculation requires only one PE, and no data transfer is needed between PEs. PE0 and PE1 perform the operations respectively. and The tensor product is calculated. For PE0, the multipath decomposers C0 and C1 select the tensor product. and As input, C2 and C3 choose 1 as input, without changing the calculation result. The demultiplexer C4 chooses to directly output the calculation result. To complete the tensor product calculation. Similarly, PE1 selects... , and As operands of tensor products, and directly output the calculation results. . Figure 9 (b) shows the 32-qubit system divided into 16 groups. The PE configuration details are as follows: each group contains two qubits, and the requirement to perform 16 multiplications exceeds the capacity of a single processing unit (PE) multiplier. Therefore, multiple PEs are needed to collaboratively perform the tensor product operation, and data transfer occurs between PEs. For PE0 and PE1, demultiplexers C1, C2, and C3 are all configured to select the input operands for the tensor product operation. Demultiplexer C4 of PE0 transfers the intermediate result to a register and sends it as input to PE1 for subsequent computation. Finally, after computation and transfer by PE1 and PE2, the tensor product result is obtained. It was calculated on PE3.

[0053] The quantum error mitigation accelerator utilizing the sparsity in tensor products, as provided in the above embodiments, is implemented in hardware as follows: The SiTA accelerator is implemented using Xilinx High-Level Synthesis (HLS) to generate hardware description languages ​​(HDLs), such as Verilog, from high-level C++ code. Its performance was evaluated on the Xilinx Alveo U50 platform, operating at a clock frequency of 300 MHz. The SiTA accelerator was also implemented in RTL and synthesized using the Synopsys design compiler to estimate the chip area and total power consumption under the FreePDK 45nm standard cell library. In this embodiment, SiTA was synthesized based on 45nm CMOS technology, and the parameters are shown in Table 1.

[0054] Table 1. Area and power of SiTA architecture

[0055] As detailed in Table 1, SiTA operates seamlessly at a clock frequency of 1 GHz with a total power consumption of 0.85 W and a compact chip area of ​​4.36 mm². Further analysis shows that the dynamic multiplier chain is the main contributor to power consumption, accounting for 52.9% of the total power consumption. On the other hand, the on-chip buffer responsible for storing the mitigation matrix and mitigation probability vector plays a crucial role in chip area utilization, occupying 56.9% of the total chip area.

[0056] The following comparison, using specific test data, between the SiTA provided in this embodiment of the invention and existing readout error mitigation methods IBU (Realizing topologically ordered states on a quantum processor), Mthree (Scalable mitigation of measurement errors on quantum computers), QuFEM (Fast and accurate quantum readout calibration using the finite element method), and SpREM (Exploiting hamming sparsity for fast quantum readout error mitigation) is conducted to evaluate its effectiveness. QuFEM runs on an AMD EPYC 9554 CPU (using numpy v1.24.3), while IBU and Mthree run on an NVIDIA A100 PCIe 80 GB GPU (using jax-gpu v0.4.13 and cuBLAS v12.4). SpREM is a hardware-level technology implemented on the Xilinx Alveo U50 platform, operating at a clock frequency of 300 MHz. The number of iterations is set to 2 for all iterative methods. The pruning threshold for QuFEM is set to 10⁻⁵. Baseline parameters are fine-tuned to ensure high accuracy while maintaining low latency.

[0057] (1) Relief Matrix and Benchmark Setup: The relief matrix was characterized using QuFEM by running 1380 matrix characterization circuits on the Quafu and Rigetti quantum platforms. Detailed noise characteristics of the two quantum devices are provided in Table 2, where, CZ This indicates a controlled phase gate error. XYThis represents the XY gate error simulating the XY interaction in quantum computing. The benchmark tests in the experiments included five well-known quantum algorithms: the Bernstein-Vazirani (BV) algorithm, the Greenberger-Horne-Zeilinger (GHZ) algorithm, and three variational quantum algorithms: the feedback-based quantum optimization algorithm (FALQON), the variational quantum solver (VQE), and the quantum approximation optimization algorithm (QAOA). The number of shots running these quantum circuits was set to 100,000 to ensure a stable probability vector.

[0058] Table 2 Quantum Device Specifications

[0059] Hellinger fidelity was used as an evaluation metric to measure the effectiveness of the mitigation. Hellinger fidelity, as a measure of similarity between two probability distributions, assesses how close a noisy distribution is to an ideal (i.e., noise-free) probability distribution. Latencies for SiTA and SpREM were measured using Xilinx runtime, while their power consumption was analyzed using xbutil. GPU execution time was measured using cudaEventElapsedTime, and power consumption was obtained via nvidia-smi.

[0060] (2) The beneficial effects of speed increase: Figure 10 The speedup of SiTA relative to the baseline is demonstrated. SiTA achieves geometrically average speedups of 3.9x, 5.5x, 826.1x, and 1340.8x, respectively, compared to SpREM, Mthree, IBU, and QuFEM. These speedups are achieved by leveraging sparsity to eliminate redundant computations. Specifically, SiTA employs probabilistic and state-level parallelism to accelerate the tensor product operator and utilizes sparsity to eliminate computations involving zero values. For the 96-qubit GHZ algorithm, SiTA achieves a speedup of up to 1217.7x relative to IBU on an NVIDIA A100 GPU. This is because IBU does not optimize for latency between iterations, resulting in low GPU utilization. SiTA demonstrates speedups of 3.8x to 4.7x compared to SpREM in the BV and GHZ algorithms. In practical applications, although SpREM uses a Hamming sparse format to compress the mitigation matrix, it lacks techniques for characterizing this matrix, preventing it from directly mitigating large-scale quantum circuits with more than 19 qubits. When characterization time is taken into account, SiTA achieves an end-to-end speedup of more than 3.8 to 4.7 times compared to SpREM.

[0061] (3) Speed ​​Improvement Analysis: Figure 11Figure (a) shows a comparison of operation counts between SiTA and QuFEM. By utilizing the sparsity of the output and input, SiTA reduces the number of operations by an average of 1.6 times and 1.1 times compared to QuFEM, respectively. Output sparsity corresponds to the critical operation: tensor product. For example, in the 12-qubit BV algorithm, this operation accounts for 93.7% of the total redundant computation. Therefore, output sparsity significantly reduces the number of operations when eliminating redundant computations. Figure 3 Figure (b) illustrates the speed improvement of SiTA relative to QuFEM. The overall speed improvement of 1340.8 times (1340.8 x) mainly comes from three technologies provided in this embodiment: sparsity acceleration, parallelism acceleration, and operation fusion acceleration. First, the specialized design of the tensor product computation unit contributes 415.1 times the speed improvement by combining probabilistic and state-level parallelism. Second, the sparsity mitigation data flow skips calculations related to zero values, achieving a speed improvement of 1.7 times. Third, the operation fusion technique reduces latency between iterations, further enhancing the speed improvement.

[0062] (4) Beneficial effects of throughput: such as Figure 12 As shown, SiTA achieves a geometric mean throughput of 386.2 GOPS, representing a throughput improvement of 3.2x, 4.3x, and 351.1x compared to SpREM, Mthree, and IBU, respectively. SiTA combines probabilistic and state-level parallelism to accelerate the tensor product critical operation in the readout error mitigation process. By integrating Z-order and N-order operators, SiTA fuses operators from two iterations, promoting overlapping computation and significantly improving overall execution efficiency. Therefore, this method achieves a maximum throughput of 420.1 GOPS. It is worth noting that SiTA achieves better performance in the GHZ algorithm. This is because the GHZ algorithm outputs more ground states, which increases the load on the SiTA accelerator, enabling it to perform computational mitigation more efficiently.

[0063] (5) Beneficial effects of energy efficiency: In terms of energy efficiency, SiTA achieves an energy efficiency of 14.6 GOPS / W, which is 1.3 times, 3.2 times, and 2433.3 times higher than SpREM, Mthree, and IBU, respectively. Figure 12 As shown. Furthermore, SiTA demonstrates impressive improvements in energy efficiency, achieving a three-order-of-magnitude improvement (1985.9x to 4187.3x) compared to IBU on the NVIDIA A100 GPU. This significant enhancement is largely attributed to SiTA's design, which stores the mitigation matrix on-chip, effectively minimizing off-chip memory access. By reducing the need for external memory interactions, SiTA not only improves energy efficiency but also optimizes overall performance.

[0064] (6) Fidelity Benefits: For clarity, a simplified representation of the variational quantum algorithm is provided for comparison and discussion. For example, QAOA-10-2L represents a 10-qubit QAOA algorithm with two layers of quantum gates L, as shown in Table 3. The Hellinger fidelity comparison results between SiTA and the baseline are presented in Table 3.

[0065] Table 3 Comparison of Hellinger fidelity between SiTA and baseline methods

[0066] For the BV and GHZ algorithms, SiTA's results showed the highest output fidelity, with average improvements of 2.3x, 1.5x, 1.4x, 1.3x, and 1.1x over the original results, respectively, exceeding those of Mthree, SpREM, IBU, and QuFEM. These three variational quantum algorithms contain more two-qubit gates in their quantum circuits, leading to increased crosstalk noise during readout. However, IBU and Mthree do not consider crosstalk, while SpREM only simulates local crosstalk. Therefore, the error mitigation effects of Mthree, IBU, and SpREM are low, and even ineffective for the QAOA, VQE, and FALQON algorithms. For example, Mthree offers no mitigation effect for the VQE-12-2L algorithm on the Rigetti quantum platform. In contrast, SiTA mitigates crosstalk noise between different qubits through an iterative tensor product formula, achieving an average fidelity improvement of 25.0%. Furthermore, SiTA was observed to improve the fidelity of the BV, GHZ, and QAOA algorithms compared to QuFEM, while the fidelity of SiTA and QuFEM was similar for the VQE and FALQON algorithms. This is attributed to the simple circuit structures of the BV, GHZ, and QAOA algorithms, which have less noise and therefore output sparse noise probability vectors. However, in the VQE and FALQON algorithms, their higher circuit noise levels result in a uniform distribution of the measured fundamental states in the Hilbert space.

[0067] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A quantum error mitigation acceleration method using sparsity in tensor products, characterized in that: The following steps are involved: Multiplying the noise probability vector read out by the quantum error by the mitigation matrix to establish a quantum error mitigation conversion equation, dividing the mitigation matrix into a plurality of groups of sub-mitigation matrices and dividing the basis vector of the noise probability vector into quantum bits corresponding to the plurality of groups of sub-mitigation matrices; The quantum error mitigation conversion equation is divided into three operations: matrix-vector multiplication, tensor product and multiplication-accumulation. The matrix-vector multiplication performs the multiplication calculation between the mitigation matrix and the basis vector and flattens it to obtain the intermediate value. The tensor product performs the tensor product calculation of the intermediate value to obtain the intermediate vector and flattens it to the intermediate matrix. The multiplication-accumulation performs the multiplication and accumulation of the intermediate matrix and the noise probability vector to obtain the mitigation probability vector as the output. Based on the output sparsity of the mitigation probability vector, non-zero elements in it are pre-acquired to capture the elements that need to be multiplied and accumulated and trace back to the tensor product operation and the multiplication-accumulation operation. Based on the input sparsity of the basis vector, the matrix-vector multiplication is converted into directly extracting the columns in the mitigation matrix to achieve sparsity acceleration. The intermediate vectors in the tensor product operation are simultaneously subjected to row-parallel computation and column-parallel computation to generate rows and columns of the intermediate matrix respectively, thereby achieving parallel acceleration based on sparsity. The tensor product operation is alternately performed in row-major order and column-major order in iteration rounds to generate calculations of intermediate matrices so as to reduce the waiting time of multiplication and accumulation operations between adjacent iteration rounds, thereby achieving operation fusion acceleration based on sparsity and parallelism.

2. The quantum error mitigation acceleration method using sparsity in tensor product according to claim 1, characterized in that: The multiplication of the quantum readout noise probability vector and the mitigation matrix to establish a quantum error mitigation conversion equation includes: Through the matrix-based quantum error mitigation method, the noise probability vector of the quantum readout is multiplied by the mitigation matrix to obtain the mitigation probability vector, so that the noise probability vector is close to the ideal probability vector. The formula of the quantum error mitigation conversion equation is expressed as: ， in, represents the mitigation probability vector, represents the mitigation matrix, represents the noise probability vector.

3. The quantum error mitigation acceleration method using sparsity in tensor product according to claim 1 or 2, characterized in that: The mitigation matrix is ​​divided into a plurality of groups of sub-mitigation matrices and the basis vector of the noise probability vector is divided into quantum bits corresponding to the plurality of groups of sub-mitigation matrices, including: Through the quantum error mitigation method based on tensor product, the mitigation matrix in the quantum error mitigation conversion equation is transformed into Divide into Group Mitigation Matrix , then the quantum error mitigation conversion equation formula is converted to: ， in, represents the mitigation probability vector, represents the noise probability vector, represents tensor product; The noise probability vector The basis vector Further divided into The quantum bit corresponding to the group mitigation matrix , then the quantum error mitigation conversion equation formula is converted to: ， in, Represented in basis vector The noise probability vector under the state, It means that after the quantum bit is measured The set of non-zero probability basis vectors in .

4. The quantum error mitigation acceleration method using sparsity in tensor product according to claim 1, characterized in that: The method of pre-acquiring non-zero elements therein based on the output sparsity of the mitigation probability vector to capture elements that need to be multiplied and accumulated and tracing back to the tensor product operation and the multiplication and accumulation operation includes: Based on the output sparsity of the mitigation probability vector, non-zero elements in the mitigation probability vector are obtained in advance, and the multiplication and accumulation operations are traced back according to each non-zero element to determine the elements that need to be multiplied and accumulated, and the tensor product operation step is further traced back to determine the elements that need to be subjected to the tensor product operation.

5. The quantum error mitigation acceleration method using sparsity in tensor product according to claim 1, characterized in that: The method converts the matrix-vector multiplication into directly extracting columns in the mitigation matrix based on the input sparsity of the basis vector, including: The basis vectors in the quantum system are represented as unit vectors. By identifying the non-zero indices in the basis vectors, the matrix-vector multiplication operation is transformed into directly selecting the corresponding columns from the mitigation matrix according to the non-zero indices.

6. The quantum error mitigation acceleration method using sparsity in tensor product according to claim 1, characterized in that: The method of performing row-parallel calculation and column-parallel calculation on the intermediate vectors in the tensor product operation simultaneously to generate rows and columns of the intermediate matrix respectively includes: In the tensor product operation, orthogonal probability-level parallelism and state-level parallelism are identified. The probability-level parallelism is to calculate multiple intermediate vectors in parallel, and the state-level parallelism is to calculate multiple elements in each intermediate vector in parallel. According to the probability-level parallelism, the intermediate vectors in the tensor product operation are calculated in parallel on each row of elements. At the same time, according to the state-level parallelism, the intermediate vectors in the tensor product operation are calculated in parallel on each column of elements, thereby generating a block in the intermediate matrix in each calculation cycle, and finally outputting the entire intermediate matrix.

7. The quantum error mitigation acceleration method using sparsity in tensor product according to claim 6, characterized in that: For the values ​​of the same row in each slice, the operands and their row indexes are the same, and operand reuse and index reuse are performed accordingly when calculating the values ​​of the same row in each slice.

8. The quantum error mitigation acceleration method using sparsity in tensor products according to claim 1, characterized in that: The tensor product operation is alternately performed in row-major order and column-major order in iteration rounds to generate calculations of intermediate matrices so as to reduce the waiting time of multiplication and accumulation operations between adjacent iteration rounds, including: In the current iteration round, the tensor product operation follows the row-major order to generate the intermediate matrix row by row, and in the next iteration round, the tensor product operation follows the column-major order to generate the intermediate matrix column by column. Then, after the tensor product operation in the next iteration round, the multiplication and accumulation operation can be performed independently without waiting for all the multiplication and accumulation operations in the current iteration round to be completed.

9. A quantum error mitigation accelerator using sparsity in tensor products, implemented based on the quantum error mitigation acceleration method using sparsity in tensor products as claimed in any one of claims 1 to 8, characterized in that: include: Matrix-vector multiplication computing unit, tensor product computing unit, multiplication-accumulation computing unit and memory; The matrix-vector multiplication calculation unit is used to perform a column selection operator on the mitigation matrix according to the character string in the basis vector, obtain the columns of the mitigation matrix and flatten them into intermediate values; The tensor product calculation unit is used to process the tensor product data stream in a probability level parallel and state level parallel manner, calculate the intermediate vector and flatten it into an intermediate matrix; The multiplication-accumulation calculation unit is used to receive the results from the tensor product calculation unit in a block-by-block manner, each block of the intermediate matrix is ​​generated in a row-major order or a column-major order and multiplied with the noise probability vector, and the results of different blocks are accumulated and aggregated to obtain a mitigation probability vector as an output; The memory is used to store the input mitigation matrix and the output mitigation probability vector respectively.

10. The quantum error mitigation accelerator using sparsity in tensor products according to claim 9, characterized in that: A cascade multiplexer is designed in the matrix-vector multiplication calculation unit to select strings in the basic vector respectively and work in a cascade structure; a processing unit including a multiplier and a demultiplexer is designed in the tensor product calculation unit, the multiplier is used to perform tensor product calculation, and the demultiplexer is used to select input operands or intermediate results of the tensor product operation and to configure the output path to select to output the calculation result directly or transfer it to the next processing unit through a register.

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