Controller

Abstract

A controller includes: a receiving interface configured to receive first frame data and a first vertical synchronization packet; and a transmission interface configured to transmit a first frame request signal when a first period from a time point at which the reception interface completes reception of the first frame data to a time point at which the reception interface starts to receive the first vertical synchronization data packet is longer than a first reference period, and the sending interface sends the first frame request signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0137090, filed on October 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a processor, a controller including the processor, a method of driving the controller, and a display device including the controller. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has become prominent. In response to this, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] The display device may display images at a high frequency or at a low frequency as required. For example, when displaying a moving image, the image may be displayed at a high frequency, and when displaying a still image or in a standby state, the image may be displayed at a low frequency.

[0006] When entering a low-frequency display mode from a high-frequency display mode, an afterimage of a previous image may remain due to hysteresis characteristics of a drive transistor in a pixel, and thus an undesired display may occur. Summary of the invention

[0007] The present invention includes a controller that can prevent afterimages from occurring when entering a low-frequency display mode even if the controller does not include a separate frame memory. In addition, the present invention includes a method of driving the controller and a display device including the controller.

[0008] According to an embodiment, a controller includes: a receiving interface, configured to receive a first frame data and a first vertical synchronization data packet; and a sending interface, configured to send a first frame request signal, and when a first time period from a time point when the receiving interface completes receiving the first frame data to a time point when the receiving interface starts receiving the first vertical synchronization data packet is longer than a first reference time period, the sending interface sends the first frame request signal.

[0009] In an embodiment, the controller may send the first frame request signal after a time point at which reception of the second frame data after the first frame data is completed.

[0010] In an embodiment, the first frame data and the second frame data may be different image data.

[0011] In an embodiment, when the first frame request signal is transmitted, the controller may receive a second vertical synchronization data packet.

[0012] In an embodiment, the controller may receive third frame data after receiving the second vertical synchronization data packet, and the third frame data and the second frame data may be the same image data.

[0013] In an embodiment, the controller may send a second frame request signal after a time point at which the reception of the third frame data is completed.

[0014] In an embodiment, a second period from the time point of completing the reception of the second frame data to the time point of starting to receive the second vertical synchronization data packet may be shorter than the first period.

[0015] In an embodiment, a third period from the time point of completing the reception of the third frame data to the time point of starting to receive the third vertical synchronization data packet may be equal to the second period.

[0016] In an embodiment, when the first time period is shorter than the first reference time period and longer than the second reference time period, the receiving interface of the controller can further receive multiple frame data, and when the number of frames that are shorter than the first reference time period and longer than the second reference time period is consistent with the number of reference frames, the sending interface can send the first frame request signal after completing the time point of receiving the second frame data which is the last frame data among the multiple frame data.

[0017] In an embodiment, the plurality of frame data may be different image data.

[0018] In an embodiment, when the first frame request signal is transmitted, the controller may receive a second vertical synchronization data packet.

[0019] In an embodiment, the controller may receive third frame data after receiving the second vertical synchronization data packet, and the third frame data and the second frame data may be the same image data.

[0020] In an embodiment, the controller may send a second frame request signal after a time point at which the reception of the third frame data is completed.

[0021] In an embodiment, a second period from the time point of completing the reception of the second frame data to the time point of starting to receive the second vertical synchronization data packet may be shorter than the first period.

[0022] In an embodiment, a third period from the time point of completing the reception of the third frame data to the time point of starting to receive the third vertical synchronization data packet may be equal to the second period.

[0023] In an embodiment, the controller may further include: a first register storing the first reference period; a second register storing the second reference period; and a third register storing the number of times the frame request signal is sent.

[0024] In an embodiment, the first frame request signal and the second frame request signal may be transmitted based on the number of transmission times stored in the third register, and the number of transmission times may be 2 or more.

[0025] According to an embodiment, a method of driving a controller may include: receiving a first frame of data; receiving a first vertical synchronization data packet; and sending a first frame request signal when a first time period from a time point when reception of the first frame of data is completed to a time point when reception of the first vertical synchronization data packet starts is longer than a first reference time period.

[0026] In an embodiment, the controller may send the first frame request signal after a time point at which reception of the second frame data after the first frame data is completed.

[0027] In an embodiment, the first frame data and the second frame data may be different image data.

[0028] In an embodiment, when the first frame request signal is transmitted, the controller may receive a second vertical synchronization data packet.

[0029] In an embodiment, the controller may receive third frame data after receiving the second vertical synchronization data packet, and the third frame data and the second frame data may be the same image data.

[0030] In an embodiment, the controller may send a second frame request signal after a time point at which the reception of the third frame data is completed.

[0031] In an embodiment, a second period from the time point of completing the reception of the second frame data to the time point of starting to receive the second vertical synchronization data packet may be shorter than the first period.

[0032] In an embodiment, a third period from the time point of completing the reception of the third frame data to the time point of starting to receive the third vertical synchronization data packet may be equal to the second period.

[0033] In an embodiment, when the first time period is shorter than the first reference time period and longer than the second reference time period, the receiving interface of the controller can further receive multiple frame data, and when the number of frames that are shorter than the first reference time period and longer than the second reference time period is consistent with the number of reference frames, the sending interface can send the first frame request signal after completing the time point of receiving the second frame data which is the last frame data among the multiple frame data.

[0034] In an embodiment, the plurality of frame data may be different image data.

[0035] In an embodiment, when the first frame request signal is transmitted, the controller may receive a second vertical synchronization data packet.

[0036] In an embodiment, the controller may receive third frame data after receiving the second vertical synchronization data packet, and the third frame data and the second frame data may be the same image data.

[0037] In an embodiment, the controller may send a second frame request signal after a time point at which the reception of the third frame data is completed.

[0038] In an embodiment, a second period from the time point of completing the reception of the second frame data to the time point of starting to receive the second vertical synchronization data packet may be shorter than the first period.

[0039] In an embodiment, a third period from the time point of completing the reception of the third frame data to the time point of starting to receive the third vertical synchronization data packet may be equal to the second period.

[0040] According to an embodiment, a display device may include: a processor configured to send a first frame data and a first vertical synchronization data packet; a controller configured to generate a data voltage corresponding to the first frame data; and a pixel unit configured to display an image based on the data voltage, and the controller may send a first frame request signal to the processor when a first period from a time point when reception of the first frame data is completed to a time point when reception of the first vertical synchronization data packet starts is longer than a first reference period.

[0041] In an embodiment, even if the controller does not include a separate frame memory, the controller, the method of driving the controller, and the display device including the controller according to the present disclosure can prevent an afterimage from occurring when entering a low-frequency display mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other features of the present invention will become more apparent by further describing the embodiments of the present invention in detail with reference to the accompanying drawings, in which:

[0043] Figure 1A is a schematic block diagram showing a display device according to an embodiment;

[0044] Figure 1B is a schematic block diagram showing a display device according to an embodiment;

[0045] Figure 2 is a schematic circuit diagram showing a sub-pixel according to an embodiment;

[0046] Figure 3 The driving method according to the embodiment is shown Figure 2 A timing diagram of the sub-pixel method;

[0047] Figure 4A is a timing diagram showing a method of driving a display device according to an embodiment;

[0048] Figure 4B is a timing diagram showing a method of driving a display device according to an embodiment;

[0049] Figure 4C is a timing diagram showing a method of driving a display device according to an embodiment;

[0050] Figure 4D is a timing diagram showing a method of driving a display device according to an embodiment;

[0051] Figure 5 is a flowchart illustrating a method of driving a display device according to an embodiment;

[0052] Figure 6 is a timing diagram showing a method of driving a display device according to an embodiment;

[0053] Figure 7 is a flowchart illustrating a method of driving a display device according to an embodiment; and

[0054] Figure 8 is a block diagram of an electronic device according to an embodiment. DETAILED DESCRIPTION

[0055] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0056] In order to clearly describe the present invention, parts not related to the description are omitted, and the same or similar elements are denoted by the same reference numerals throughout the specification. Therefore, the above reference numerals may be used in other drawings.

[0057] In addition, for the convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the present invention is not necessarily limited to the size and thickness shown in the drawings. In the drawings, the thickness may be exaggerated to clearly show each layer and region.

[0058] In addition, the expression "is the same" in the description may mean "is substantially the same". That is, the expression "is the same" may be sufficiently identical so that a person of ordinary skill understands that it is the same. Other expressions may also be expressions from which "substantially" is omitted.

[0059] Unless explicitly described to the contrary, throughout the specification, the word "include" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the stated elements, but not to exclude any other elements. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ as examples). As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0060] Although the terms first, second, etc. can be used in this article to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another constituent element. Therefore, without departing from the teaching of the present disclosure, the first constituent element discussed below can be referred to as the second constituent element.

[0061] For descriptive purposes, spatially relative terms such as "under," "below," "below," "above," and "on" may be used herein, and thereby describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "below" or "beneath" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the term "below" can cover both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0062] Various embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes of the regions shown, but will include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of regions of the device and are not intended to be limiting.

[0063] The same number always refers to the same element. In the accompanying drawings, for clarity, the thickness (thickness) of some lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms "first", "second", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the "first" element discussed below may also be referred to as the "second" element.

[0064] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be restrictive. Unless the context clearly indicates otherwise, as used herein, "one", "one (kind / person)", "the (said)" and "at least one (kind / person)" do not represent a limitation on quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (kind / person)" will not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0065] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0066] Figure 1A and Figure 1B is a schematic block diagram showing a display device according to an embodiment.

[0067] refer to Figure 1A According to an embodiment, the display device 10 may include a memory 8, a processor 9, a controller 11, a scan driver 13, a pixel unit 14, and an emission driver 15.

[0068] In an embodiment, the processor 9 may include a transmission interface 91 and a reception interface 92. For example, the transmission interface 91 may transmit data DATA, a data clock DCK, and a synchronization signal ESYNC.

[0069] In an embodiment, the data DATA may include frame data and a vertical synchronization packet. The data DATA may also include a horizontal synchronization packet. The frame data may be image data. The vertical synchronization packet may be a control packet notifying that the transmission of the current frame data is finished and the transmission of the next frame data is about to start. The horizontal synchronization packet may be a control packet notifying that the transmission of the current horizontal line among the multiple horizontal lines configuring the image is finished and the transmission of the next horizontal line is about to start. At the same time, the horizontal synchronization packet may also be continuously provided at a time point when the frame data is not transmitted.

[0070] In an embodiment, the data clock DCK may be a clock signal of a transmission unit for notifying data DATA. The controller 11 may sample the data DATA based on the data clock DCK. Meanwhile, the data clock DCK may be embedded in the data DATA. In this case, the controller 11 may extract the data clock DCK from the data DATA using a clock recovery circuit. In this case, the processor 9 may not provide the data clock DCK separately.

[0071] In an embodiment, the synchronization signal ESYNC may be a signal for synchronization between the processor 9 and the controller 11. For example, the period of the synchronization signal ESYNC may be the same as the period of the horizontal synchronization data packet. That is, the period of the synchronization signal ESYNC may correspond to one horizontal period. When synchronization is not required or there is another synchronization signal, the synchronization signal ESYNC may be omitted.

[0072] In an embodiment, the reception interface 92 may receive the frame request signal TE. At least a portion of the transmission interface 91 and the reception interface 92 may have a standard defined by a Mobile Industry Processor Interface (MIPI).

[0073] In an embodiment, the processor 9 may include a graphics processing unit in the processor 9. The graphics processing unit may generate (or render) frame data FDi corresponding to an image. In another embodiment, the processor 9 may be connected to an external graphics processing unit. The processor 9 may be an application processor (AP) or a central processing unit (CPU).

[0074] In an embodiment, the memory 8 may store frame data FDi generated by the processor 9 or the graphics processing unit. The frame data FDi may be image data that is being rendered. That is, the frame data FDi may be image data that has not yet been rendered. At the same time, the memory 8 may provide pre-stored frame data FDo according to a request from the processor 9. For example, the frame data FDo may be image data at a past time point of the frame data FDi, and may be image data that has been rendered. For example, when the frame data FDi is the Nth image data, the frame data FDo may be the (N-1)th image data. N may be an integer greater than 1.

[0075] In an embodiment, the frame data may include a grayscale for each pixel. For example, the grayscale may include a first color grayscale for expressing a first color, a second color grayscale for expressing a second color, and a third color grayscale for expressing a third color.

[0076] In an embodiment, the controller 11 may receive data DATA, data clock DCK and synchronization signal ESYNC from the processor 9, and may transmit a frame request signal TE in some cases. As described above, according to an embodiment, the configuration of the data clock DCK and synchronization signal ESYNC may be omitted.

[0077] In an embodiment, the controller 11 may include a receiving interface 11 r for receiving frame data and vertical synchronization data packets, and a sending interface 11 t for sending a frame request signal TE.

[0078] In an embodiment, the frame request signal TE may be a signal by which the controller 11 requests the frame data FDo from the processor 9. When the processor 9 receives the frame request signal TE, the processor 9 may cancel the scheduled schedule and provide the frame data FDo. The frame data FDo may be the latest frame data that has completed rendering among the data stored in the memory 8. When the processor 9 receives the frame request signal TE, the processor 9 may first provide a vertical synchronization data packet and then provide the frame data FDo.

[0079] For example, in an embodiment, when the controller 11 senses that the display frequency of the image is reduced from a high frequency to a low frequency, the controller 11 may send a frame request signal TE according to a predetermined reference. The frame request signal TE may be repeatedly sent at a high frequency. Therefore, an image corresponding to the frame data FDo may be repeatedly displayed at a high frequency. Therefore, by repeatedly displaying an image at a high frequency before displaying the image at a low frequency, an afterimage phenomenon due to a hysteresis characteristic may be prevented. When entering a low frequency drive of the display device 10, a function of inserting a frame to repeatedly display an image at a high frequency may be referred to as a frame insertion function.

[0080] In the examples and also with reference to Figure 1B, the controller 11 may include a plurality of registers REG1, REG2, REG3, and REG4 for storing set values ​​for the frame insertion function. For example, the first register REG1 may store mode information, the second register REG2 may store a first reference period, the third register REG3 may store frequency information, and the fourth register REG4 may store the number of times the frame request signal TE is sent. The description of the registers REG1, REG2, REG3, and REG4 refers to the description of the following FIG. 4A to FIG. 5 . For reference, more registers may be added in other embodiments. The controller 11 may sample the grayscale for each pixel from the data DATA based on the data clock DCK. The controller 11 may convert the grayscale as a digital signal into a data voltage as an analog voltage. In addition, the controller 11 may generate a control signal for writing the data voltage to the pixel unit 14 and provide the control signal to the scan driver 13 and the emission driver 15. However, depending on the structure of the pixel, the emission driver 15 may be omitted.

[0081] In an embodiment, the controller 11 may apply data voltages to the data lines DL1, DL2, DL3, ... and DLn in units of pixel rows (or in units of horizontal lines). "n" may be an integer greater than 0. A pixel row may refer to a sub-pixel connected to the same scan line and emission line.

[0082] In an embodiment, the scan driver 13 may generate a scan signal to be provided to the scan lines SL0, SL1, SL2, ... and SLm by receiving a clock signal and a scan start signal from the controller 11. For example, the scan driver 13 may sequentially provide a scan signal having an on-level pulse to the scan lines SL1 to SLm. For example, the scan driver 13 may be configured in the form of a shift register, and may generate a scan signal in a method of sequentially transmitting a scan start signal in the form of an on-level pulse to a next-level circuit under the control of a clock signal. "m" may be an integer greater than 0.

[0083] In an embodiment, the emission driver 15 may generate an emission signal to be provided to the emission lines EL1, EL2, EL3, ... and ELo by receiving a clock signal and an emission stop signal from the controller 11. For example, the emission driver 15 may sequentially provide an emission signal having an off-level pulse to the emission lines EL1 to ELo. For example, the emission driver 15 may be configured in the form of a shift register, and may generate an emission signal in a method of sequentially transmitting an emission stop signal in the form of an off-level pulse to a next-stage circuit under the control of a clock signal. "o" may be an integer greater than 0.

[0084] In an embodiment, the pixel unit 14 includes pixels. Each pixel may include a plurality of sub-pixels. For example, a pixel may include a first sub-pixel emitting light in a first color, a second sub-pixel emitting light in a second color, and a third sub-pixel emitting light in a third color. According to an embodiment, each pixel may include only two sub-pixels, and an image may be displayed by sharing sub-pixels with adjacent pixels.

[0085] In an embodiment, each sub-pixel SPij may be connected to a corresponding data line, a scan line, and an emission line. Each of i and j may be an integer greater than 0. The sub-pixel SPij may refer to a sub-pixel in which a scan transistor is connected to an i-th scan line and a j-th data line.

[0086] In an embodiment, the first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue, the second color may be one of red, green, and blue other than the first color, and the third color may be one of red, green, and blue other than the first color and the second color. In addition, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors. However, in an embodiment, for ease of description, it is assumed that the first color is red, the second color is green, and the third color is blue.

[0087] In an embodiment, the pixel unit 14 may be in a diamond shape, for example. RGB stripe, S stripe, Real RGB and normal of various shapes set.

[0088] In the embodiment, it is assumed that the subpixels of the pixel unit 14 are arranged in a first direction DR1 and a second direction DR2 perpendicular to the first direction DR1. In addition, it is assumed that the emission direction of the subpixels is a third direction DR3 oriented perpendicular to the first direction DR1 and the second direction DR2.

[0089] Figure 2 is a schematic circuit diagram showing a sub-pixel according to an embodiment.

[0090] In the examples and with reference to Figure 2 , the sub-pixel SPij includes transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, and a light emitting element LD.

[0091] In the following, an embodiment of a circuit configured by a P-type transistor is described as an example. However, in another embodiment, those skilled in the art will be able to design a circuit configured by an N-type transistor by distinguishing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design a circuit configured by a combination of a P-type transistor and an N-type transistor. P-type transistors are collectively referred to as transistors in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. N-type transistors are collectively referred to as transistors in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. Transistors can be configured in various forms such as thin film transistors (TFTs), field effect transistors (FETs), and bipolar junction transistors (BJTs).

[0092] In an embodiment, the first transistor T1 may have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may be referred to as a driving transistor.

[0093] In an embodiment, the second transistor T2 may have a gate electrode connected to the scan line SLi1, a first electrode connected to the data line DLj, and a second electrode connected to the second node N2. The second transistor T2 may be referred to as a scan transistor.

[0094] In an embodiment, the third transistor T3 may have a gate electrode connected to the scan line SLi2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be referred to as a diode-connected transistor.

[0095] In an embodiment, the fourth transistor T4 may have a gate electrode connected to the scan line SLi3, a first electrode connected to the first node N1, and a second electrode connected to the initialization line INTL. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0096] In an embodiment, the fifth transistor T5 may have a gate electrode connected to an i-th emission line ELi (hereinafter, also referred to as the emission line ELi), a first electrode connected to the first power line ELVDDL, and a second electrode connected to the second node N2. The fifth transistor T5 may be referred to as an emission transistor. In another embodiment, the gate electrode of the fifth transistor T5 may be connected to an emission line different from the emission line connected to the gate electrode of the sixth transistor T6.

[0097] In an embodiment, the sixth transistor T6 may have a gate electrode connected to the i-th emission line ELi, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light emitting element LD. The sixth transistor T6 may be referred to as an emission transistor. In another embodiment, the gate electrode of the sixth transistor T6 may be connected to an emission line different from the emission line connected to the gate electrode of the fifth transistor T5.

[0098] In an embodiment, the seventh transistor T7 may have a gate electrode connected to the scan line SLi4, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light emitting element LD. The seventh transistor T7 may be referred to as a light emitting element initialization transistor.

[0099] In an embodiment, a first electrode of the storage capacitor Cst may be connected to the first power line ELVDDL, and a second electrode may be connected to the first node N1.

[0100] In an embodiment, the anode of the light emitting element LD may be connected to the second electrode of the sixth transistor T6, and the cathode may be connected to the second power line ELVSSL. The light emitting element LD may be a light emitting diode. The light emitting element LD may be configured by an organic light emitting element (organic light emitting diode), an inorganic light emitting element (inorganic light emitting diode) or a quantum dot / well light emitting element (quantum dot / well light emitting diode) or the like. Although in the present embodiment, only one light emitting element LD is provided in each pixel, in another embodiment, a plurality of light emitting elements may be provided in each pixel. At this time, the plurality of light emitting elements may be connected in series, in parallel, or in series and in parallel, etc. The light emitting element LD of each sub-pixel SPij may emit light of one of the first color, the second color and the third color.

[0101] In an embodiment, the first power line ELVDDL may be supplied with a first power voltage, the second power line ELVSSL may be supplied with a second power voltage, and the initialization line INTL may be supplied with an initialization voltage. In an embodiment, the first power voltage may be greater than the second power voltage. In an embodiment, the initialization voltage may be equal to or greater than the second power voltage. In an embodiment, the initialization voltage may correspond to the smallest data voltage among the data voltages corresponding to the output grayscale. In another embodiment, the magnitude of the initialization voltage may be smaller than the magnitude of the data voltage corresponding to the color grayscale.

[0102] Figure 3 The driving method according to the embodiment is shown Figure 2 Timing diagram of the sub-pixel method.

[0103] refer to Figure 3 , also refer to Figure 2, hereinafter, for the convenience of description, it is assumed that the scan lines SLi1, SLi2, and SLi4 are the i-th scan line SLi, and the scan line SLi3 is the (i-1)th scan line SL(i-1). However, according to embodiments, the connection relationship of the scan lines SLi1, SLi2, SLi3, and SLi4 may be various. For example, the scan line SLi4 may be the (i-1)th scan line or the (i+1)th scan line.

[0104] In an embodiment, an emission signal of an off level (logical high level) is applied to the i-th emission line ELi, a data voltage DATA(i-1)j for the (i-1)-th sub-pixel is applied to the data line DLj, and a scan signal of an on level (logical low level) is applied to the scan line SLi3. The high / low of the logic level may vary depending on whether the transistor is P-type or N-type.

[0105] In an embodiment, since a scan signal of a cut-off level is applied to the scan lines SLi1 and SLi2, the second transistor T2 is turned off and the data voltage DATA(i-1)j for the (i-1)th sub-pixel is prevented from being input to the i-th sub-pixel SPij (hereinafter, also referred to as sub-pixel SPij).

[0106] In the embodiment, since the fourth transistor T4 is turned on, the first node N1 is connected to the initialization line INTL, and thus the voltage of the first node N1 is initialized. Since the emission signal of the off level is applied to the emission line ELi, the transistors T5 and T6 are turned off, and unnecessary light emission of the light emitting element LD according to the initialization voltage application process is prevented.

[0107] In an embodiment, a data voltage DATAij for the i-th subpixel SPij is applied to the data line DLj, and a scan signal of a conduction level is applied to the scan lines SLi1 and SLi2. Therefore, transistors T2, T1 and T3 are turned on, and the data line DLj and the first node N1 are electrically connected to each other. Therefore, a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DATAij is applied to the second electrode (i.e., the first node N1) of the storage capacitor Cst, and the storage capacitor Cst maintains a voltage corresponding to the difference between the first power voltage and the compensation voltage. Such a period may be referred to as a threshold voltage compensation period or a data writing period. In addition, in an embodiment, when the scan line SLi4 is the i-th scan line, since the seventh transistor T7 is turned on, the anode of the light emitting element LD and the initialization line INTL are connected to each other, and the charge amount of the light emitting element LD is initialized to a charge amount corresponding to the voltage difference between the initialization voltage and the second power voltage.

[0108] In an embodiment, as the emission signal of the on level is applied to the i-th emission line ELi, the transistors T5 and T6 may be turned on, thereby forming a driving current path connecting the first power line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light emitting element LD and the second power line ELVSSL.

[0109] In an embodiment, the amount of driving current flowing to the first electrode and the second electrode of the first transistor T1 is adjusted according to the voltage held in the storage capacitor Cst. The light emitting element LD emits light with a brightness corresponding to the amount of driving current. The light emitting element LD emits light until an emission signal of a cutoff level is applied to the emission line ELi.

[0110] In an embodiment, when the emission signal is at an on level, the sub-pixel receiving the corresponding emission signal may be in a display state. Therefore, the period in which the emission signal is at an on level may be referred to as an emission period EP (or emission allowed period). In addition, when the emission signal is at an off level, the sub-pixel receiving the corresponding emission signal may be in a non-display state. Therefore, the period in which the emission signal is at an off level may be referred to as a non-emission period NEP (or emission not allowed period).

[0111] In the embodiments, reference Figure 3 The described non-emission period NEP is for preventing the sub-pixel SPij from emitting light with undesired brightness during the initialization period and the data writing period.

[0112] In an embodiment, one or more non-emission periods NEP may be additionally provided while the data written to the sub-pixel SPij is maintained (e.g., one frame period). This may be to effectively express low gray levels by reducing the emission period EP of the sub-pixel SPij, or to smoothly blur the motion of the image.

[0113] FIG. 4A to FIG. 4D is a timing diagram illustrating a method of driving a display device according to an embodiment. Figure 5 is a flowchart illustrating a method of driving a display device according to an embodiment.

[0114] In the examples and with reference to Figure 4A , which shows a rendering period of the frame data FDi, the data DATA output from the processor 9, the operation clock CYC of the controller 11, and the frame request signal TE output from the controller 11.

[0115] In the examples and again with reference to Figure 1B as well as Figure 4A , also refer to Figure 1A, the first register REG1 may store information indicating the first mode as mode information. The second register REG2 may store 13'd31 as the first reference period. 13'd31 may be data indicating that the cycle of the operating clock CYC is repeated 31 times in the data of the 13-bit capacity. At this time, the first reference period may be a period corresponding to approximately 20Hz, and may be approximately 50ms. The third register REG3 may store information indicating that the frequency CHz is approximately 144Hz as frequency information. The fourth register REG4 may store information corresponding to 3 as the number of times the frame request signal TE is sent.

[0116] In an embodiment, during the frame period t1a to t2a, the processor 9 may sequentially send vertical synchronization data packets VSYNC and frame data FDo(N) to display an image at a high frequency AHz. One frame period may correspond to a transmission period of the vertical synchronization data packet VSYNC. The back porch period VBP and the front porch period VFP may indicate a period between the transmission period of the vertical synchronization data packet VSYNC and the transmission period of the frame data FDo(N), rather than a specific data packet. The length of the front porch period VFP and the length of the back porch period VBP may be predefined. In another embodiment, the processor 9 may send data packets corresponding to the back porch period VBP and the front porch period VFP. In an embodiment and with reference to Figure 4A , the high frequency AHz is shown assuming that it is the maximum frequency at which the processor 9 can operate. However, the high frequency AHz may be lower than the maximum frequency at which the processor 9 can operate, and in this case, an extended front edge period EVFP1 to be described later may exist between the front edge period VFP and the vertical synchronization data packet VSYNC.

[0117] In an embodiment, it is assumed that the processor 9 enters the low frequency display mode from the high frequency display mode from the time point t2a. For example, it is assumed that the processor 9 generates and transmits an image at a low frequency BHz from the time point t2a. At this time, the processor 9 does not send additional information notifying the frequency change to the controller 11. The processor 9 can adjust the rendering speed of the image according to the frequency. For example, the speed of generating frame data FDi (N + 2) during the period t2a to t5a operating at the low frequency BHz can be lower than the speed of generating frame data FDi (N + 1) during the period t1a to t2a operating at the high frequency AHz.

[0118] In an embodiment, during the frame periods t2a to t5a, the processor 9 may sequentially transmit a vertical synchronization packet VSYNC and frame data FDo(N+1). The frame data FDo(N+1) may be the same image data as the frame data FDi(N+1).

[0119] In the embodiment, at this time, the controller 11 may check the first period t3a to t5a from the time point t3a at which the first frame data FD1 is received to the time point t5a at which the first vertical synchronization data packet VP1 is received, or the first period t4a to t5a from the end time point t4a of the front porch period VFP to the time point t5a at which the first vertical synchronization data packet VP1 is received (see Figure 5 S101). Figure 4A In the example of , the first frame data FD1 may be frame data FDo(N+1). While the processor 9 generates frame data FDi(N+2) during the low frequency operation period, the previous frame data FDo(N+1) generated in the period t1a to t2a may be transmitted and output to the controller 11.

[0120] In an embodiment, the controller 11 can understand the length of the extended front period EVFP1 by calculating the repetition cycle of the operation clock CYC during the extended front period EVFP1. For example, the operation clock CYC can be a signal synchronized with the synchronization signal ESYNC and can have a cycle longer than the cycle of the synchronization signal ESYNC. For example, one cycle of the operation clock CYC can be equal to about 400 cycles of the synchronization signal ESYNC.

[0121] In an embodiment, the controller 11 may determine whether the first period (or the extended front period EVFP1) is longer than a first reference period (see Figure 5 S102). The first reference period may be predefined. For example, the first reference period may be predefined to be equal to the first period when the display frequency is approximately 20 Hz. For example, as described above, the second register REG2 may store 13'd31 as the first reference period. 13'd31 may be data indicating that the cycle of the operating clock CYC is repeated 31 times in the data of 13-bit capacity. Therefore, when the cycle of the operating clock CYC is repeated more than 31 times, the controller 11 may determine that the first period is longer than the first reference period. The first reference period may be a reference for checking whether the display device 10 is driven at a low frequency (here, approximately 20 Hz or lower).

[0122] In the following, for the convenience of description, a case where the range of the high frequency AHz is greater than about 40Hz and equal to or less than about 144Hz is described as an example. In the embodiment, a case where the range of the low frequency BHz is equal to or less than about 20Hz is described as an example. A case where the intermediate frequency DHz described later is greater than about 20Hz and equal to or less than about 40Hz is described as an example (refer to Figure 6 ). Therefore, in Figure 4AIn the example of , the controller 11 may determine that the first period t3a to t5a or t4a to t5a is longer than the first reference period.

[0123] In an embodiment, the controller 11 may generate a frame request signal TE at a predetermined number of times and send the frame request signal TE to the processor 9 (see Figure 5 For example, the fourth register REG4 may store information corresponding to 3 as the number of times the frame request signal TE is sent. Figure 4A , a case where the frame request signal TE is transmitted three times (at time points t6a, t8a, and t10a) is described as an example.

[0124] In an embodiment, the controller 11 may send a first frame request signal TE1 after a time point t6a of the second frame data FD2 after completing the reception of the first frame data FD1. The first frame data FDo(N+1) and the second frame data FDo(N+2) may be different image data. For example, the controller 11 may send a first frame request signal TE1 during a second time period t6a to t7a after completing the reception of the second frame data FD2 at a time point t6a. That is, when the controller 11 determines that the first time period is greater than the first reference time period, the controller 11 may determine that a frame insertion function needs to be applied and send a first frame request signal TE1 in the next frame. When the processor 9 receives the first frame request signal TE1, the processor 9 may send a second vertical synchronization data packet VP2.

[0125] In an embodiment, the second time period t6a to t7a from the time point t6a at which the reception of the second frame data FD2 is completed to the time point t7a at which the reception of the second vertical synchronization data packet VP2 is started can be shorter than the corresponding first time period t3a to t5a. That is, the frequency CHz of the frame period t5a to t7a in which the frame insertion function is performed can be higher than the low frequency BHz. The frequency CHz can be the maximum frequency at which the processor 9 can operate. The frequency CHz can be the maximum value of the range of the high frequency AHz. Therefore, the image corresponding to the frame data FDo(N+2) can be repeatedly displayed at a high frequency CHz. Therefore, by repeatedly displaying the image at a high frequency before displaying the image at a low frequency BHz after the time point t11a, the afterimage phenomenon caused by the hysteresis characteristic can be prevented.

[0126] In an embodiment, the processor 9 may send the third frame data FD3 after sending the second vertical synchronization data packet VP2. Since the rendering of the next frame data FDi(N+3) is not completed in the processor 9, the third frame data FDo(N+2) and the second frame data FDo(N+2) may be the same image data.

[0127] In an embodiment, the controller 11 may transmit the second frame request signal TE2 after the time point t8a at which the reception of the third frame data FD3 is completed.

[0128] In an embodiment, the third period t8a to t9a from the time point t8a at which the reception of the third frame data FD3 is completed to the time point t9a at which the reception of the third vertical synchronization data packet VP3 is started may be equal to the second period t6a to t7a.

[0129] In an embodiment, the controller 11 may send the frame request signal TE3 again at time point t10a. The number of times the frame request signal TE is sent may be determined in advance. Therefore, in an embodiment, the frame insertion function may be repeatedly performed three times during the period t5a to t11a (in the period t5a to t7a, the period t7a to t9a, and the period t9a to t11a).

[0130] In an embodiment, the controller 11 may not send the frame request signal TE at the time point t12a when the frame data FDo(N+2) is received. Therefore, the extended front edge period EVFP1 may appear after the time point t13a, and thus the pixel unit 14 may display an image at a low frequency BHz. Since the time after the time point t14a overlaps with the time after the time point t5a, additional description is omitted.

[0131] This embodiment can be variously modified by changing the set values ​​stored in the registers REG1, REG2, REG3, REG4, . . . .

[0132] In the examples and also with reference to Figure 4B , in the third register REG3, a case where the frequency C1Hz for the frame insertion function is set to be lower than the high frequency AHz of the period t1a to t2a is shown, and the description of the period corresponding to the time points t6a1, t8a1, t9a1, t10a1 and t11a1 will be omitted. For example, the high frequency AHz may be 144Hz, and the set frequency C1Hz may be 120Hz. In this case, after receiving the second frame data FD2, an extended front period EV11 may occur between the front period VFP and the second vertical synchronization data packet VP2. At this time, the first frame request signal TE11 may occur during the extended front period EV11. According to the generation timing of the first frame request signal TE11, the inserted frame period t5a to t7a1 may be set to correspond to the frequency C1Hz. Similarly, the second frame request signal TE21 may occur during the extended front period EV21. The third frame request signal TE31 may occur during the extended front period EV31.

[0133] In the examples and also with reference to Figure 4C, the frequency CHz set in the third register REG3 can be set equal to the high frequency AHz. However, in this embodiment, it is assumed that information corresponding to 2 is stored in the fourth register REG4 as the number of times the frame request signal TE is sent. Therefore, it can be confirmed that the frame request signals TE1 and TE2 are sent only twice.

[0134] In the examples and also with reference to Figure 4D , shows a case where the frequency C1 Hz set in the third register REG3 is set to be lower than the high frequency A Hz of the period t1a to t2a and information corresponding to 2 is stored in the fourth register REG4 as the number of transmission times of the frame request signal TE.

[0135] Figure 6 is a timing diagram illustrating a method of driving a display device according to an embodiment. Figure 7 is a flowchart illustrating a method of driving a display device according to an embodiment.

[0136] In the examples and with reference to Figure 6 , which shows a rendering period of the frame data FDi, the data DATA output from the processor 9, the operation clock CYC of the controller 11, and the frame request signal TE output from the controller 11.

[0137] In the examples and again with reference to Figure 1B as well as Figure 6 , also refer to Figure 1A , the first register REG1 may store information indicating the second mode as mode information. The second register REG2 may store 13'd31 as a first reference period, wherein 13'd31 may be data indicating that the cycle of the operating clock CYC is repeated 31 times in the data of the 13-bit capacity. At this time, the first reference period may be a period corresponding to approximately 20 Hz, and may be approximately 50 ms. The third register REG3 may store information indicating that the frequency CHz is 144 Hz as frequency information. The fourth register REG4 may store information corresponding to 3 as the number of times the frame request signal TE is sent.

[0138] In addition, in an embodiment, the controller 11 may further include a fifth register and a sixth register. The fifth register may store information about the second reference period. For example, the information about the second reference period may be 13'd13. 13'd31 may be data indicating that the cycle of the operating clock CYC is repeated 31 times in the data of the 13-bit capacity. At this time, the second reference period may be a period corresponding to approximately 40 Hz, and may be approximately 25 ms. By using the first reference period and the second reference period, the second reference period may be a reference for confirming whether the display device 10 is driven at an intermediate frequency DHz (e.g., greater than 20 Hz and equal to or less than 40 Hz).

[0139] In an embodiment, the sixth register may store information about the number of reference frames. For example, the information about the number of reference frames may be 4'd3. 4'd3 may be data indicating 3 frames in data of 4-bit capacity.

[0140] In an embodiment, during the frame period t1b to t2b, the processor 9 may sequentially transmit a vertical synchronization data packet VSYNC and frame data FDo(N) in order to display an image at a high frequency AHz.

[0141] In an embodiment, it is assumed that the processor 9 enters the intermediate frequency display mode from the high frequency display mode from the time point t2b. For example, it is assumed that the processor 9 generates and transmits an image at the intermediate frequency DHz from the time point t2b. At this time, the processor 9 does not send additional information notifying the frequency change to the controller 11. The processor 9 can adjust the rendering speed of the image according to the frequency. For example, the speed of generating frame data FDi (N+2) during the period t2b to t5b operating at the intermediate frequency DHz can be lower than the speed of generating frame data FDi (N+1) during the period t1b to t2b operating at the high frequency AHz.

[0142] In an embodiment, during the frame periods t2b to t5b, a vertical synchronization data packet VSYNC and frame data FDo(N+1) may be sequentially transmitted. The frame data FDo(N+1) may be the same image data as the frame data FDi(N+1).

[0143] In an embodiment, the controller 11 may check a first period t3b to t5b from a time point t3b at which the first frame data FD1 is received to a time point t5b at which the first vertical synchronization data packet VP1 is received, or a first period t4b to t5b from a time point t4b at which the front porch period VFP is received to a time point t5b at which the first vertical synchronization data packet VP1 is received (see Figure 7 S201). Figure 6 In the example of , the first frame data FD1 may be frame data FDo(N+1).

[0144] In an embodiment, the controller 11 can understand the length of the extended front period EVFP2 by calculating the repetition cycle of the operating clock CYC during the extended front period EVFP2. For example, the operating clock CYC can be a signal synchronized with the synchronization signal ESYNC, and can have a cycle longer than the cycle of the synchronization signal ESYNC. For example, the period in which one cycle of the operating clock CYC is performed can be equal to the period in which 400 cycles of the synchronization signal ESYNC are repeated.

[0145] In an embodiment, the controller 11 may determine whether the first period (or the extended front period EVFP2) is longer than a first reference period (see Figure 7 The first reference period may be predefined. For example, the first reference period may be predefined to be equal to the first period when the display frequency is about 20 Hz.

[0146] In the embodiment and as described above, for the convenience of description, a case where the intermediate frequency D Hz is greater than about 20 Hz and equal to or less than about 40 Hz is described as an example. Figure 6 In the example of , the controller 11 may determine that the extended front edge period EVFP2 is shorter than the first reference period.

[0147] In an embodiment, the controller 11 may determine whether the first period (or the extended front period EVFP2) is longer than the second reference period (see Figure 7 S204). The second reference period may be predefined. For example, the second reference period may be predefined to be equal to the first period when the display frequency is about 40 Hz. Figure 6 In the example of , the controller 11 may determine that the extended front edge period EVFP2 is longer than the second reference period. In an embodiment, the controller 11 may count the number of frames (see Figure 7 At this time point, the count value may be 1. When the number of frames counted is inconsistent with the number of reference frames, the controller 11 may return to step S201 and repeat the above process (see Figure 7 The number of reference frames may be predefined in the sixth register. For example, assume that the number of reference frames is predefined to be 3.

[0148] In an embodiment, the controller 11 may further receive a plurality of frame data FDo(N+2), FDo(N+3), and FDo(N+4). When the number of frames (e.g., frames corresponding to the periods t2b to t5b, t5b to t6b, and t6b to t7b) in which the first period is shorter than the first reference period and longer than the second reference period is consistent with the reference number (i.e., the number of reference frames) (S206), the controller 11 may send the first frame request signal TE1 after the time point t8b of receiving the second frame data FD2 which is the last frame data among the frame data FDo(N+2), FDo(N+3), and FDo(N+4).

[0149] In an embodiment, the controller 11 may generate a frame request signal TE at a predetermined number of times and send the frame request signal TE to the processor 9 (see Figure 7 S203). Figure 6 , a case where the frame request signal TE is transmitted three times (at time points t8b, t10b, and t12b) is described as an example.

[0150] In an embodiment, the controller 11 may send the first frame request signal TE1 after the time point t8b at which the second frame data FD2 is received. The first frame data FDo(N+1) and the second frame data FDo(N+4) may be different image data. For example, the controller 11 may send the first frame request signal TE1 during the second period t8b to t9b after the time point t8b at which the second frame data FD2 is received.

[0151] In an embodiment, when the processor 9 receives the first frame request signal TE1 , the processor 9 may send a second vertical synchronization data packet VP2 .

[0152] In an embodiment, the second time period t8b to t9b from the time point t8b of completing the reception of the second frame data FD2 to the time point t9b of starting to receive the second vertical synchronization data packet VP2 can be shorter than the corresponding first time period t3b to t5b. That is, the frequency CHz of the frame period t7b to t9b in which the frame insertion function is performed can be higher than the intermediate frequency DHz. The frequency CHz can be the maximum frequency at which the processor 9 can operate. The frequency CHz can be the maximum value of the range of the high frequency AHz. Therefore, the image corresponding to the frame data FDo(N+4) can be repeatedly displayed at a high frequency CHz. Therefore, by repeatedly displaying the image at a high frequency before displaying the image after the time point t13b at the intermediate frequency DHz, the afterimage phenomenon caused by the hysteresis characteristic can be prevented.

[0153] In an embodiment, the processor 9 may send the third frame data FD3 after sending the second vertical synchronization data packet VP2. Since the rendering of the next frame data FDi(N+4) is not completed in the processor 9, the third frame data FDo(N+4) and the second frame data FDo(N+4) may be the same image data.

[0154] In an embodiment, the controller 11 may transmit the second frame request signal TE2 after the time point t10b at which the reception of the third frame data FD3 is completed.

[0155] In an embodiment, the third period t10b to t11b from the time point t10b at which the reception of the third frame data FD3 is completed to the time point t11b at which the reception of the third vertical synchronization data packet VP3 is started may be equal to the second period t8b to t9b.

[0156] In an embodiment, the controller 11 may transmit the frame request signal TE3 again at the time point t12b. The number of transmissions of the frame request signal TE may be determined in advance.

[0157] In an embodiment, the controller 11 may not send the frame request signal TE at the time point t14b when the frame data FDo(N+4) is received. Therefore, the extended front edge period EVFP2 may appear after the time point t15b, and thus the pixel unit 14 may display an image at the intermediate frequency DHz. Since the time after the time point t15b overlaps with the time after the time point t4b, additional description is omitted (for example, description about the frame data FDi(N+5) is omitted).

[0158] Figure 8 is a block diagram of an electronic device according to an embodiment.

[0159] refer to Figure 8 In an embodiment, the electronic device 101 outputs various information through the display module 140 in the operating system. When the processor 110 executes an application stored in the memory 180, the display module 140 provides the application information to the user through the display panel 141.

[0160] In an embodiment, the processor 110 obtains external input through the input module 130 or the sensor module 191 and executes an application corresponding to the external input. For example, when the user selects the camera icon displayed in the display panel 141, the processor 110 obtains the user input through the input sensor 191-2 and activates the camera module 171. The processor 110 transmits the image data corresponding to the captured image obtained by the camera module 171 to the display module 140. The display module 140 can display the image corresponding to the captured image through the display panel 141. As another embodiment, when personal information authentication is performed in the display module 140, the fingerprint sensor 191-1 obtains the input fingerprint information as input data. The processor 110 compares the input data obtained by the fingerprint sensor 191-1 with the authentication data stored in the memory 180, and executes the application according to the comparison result. The display module 140 can display the information executed according to the application logic through the display panel 141.

[0161] As yet another embodiment, when the music streaming icon displayed in the display module 140 is selected, the processor 110 acquires the user input through the input sensor 191-2 and activates the music streaming application stored in the memory 180. When a music execution command is input in the music streaming application, the processor 110 activates the sound output module 193 to provide the user with sound information corresponding to the music execution command.

[0162] In the embodiment, the operation of the electronic device 101 is briefly described. Hereinafter, the configuration of the electronic device 101 is described in detail. Some of the configurations of the electronic device 101 to be described later may be integrated and provided as one configuration, and one configuration may be separated into two or more configurations and provided.

[0163] In the examples and with reference to Figure 8, the electronic device 101 can communicate with the external electronic device 102 through a network (for example, a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, the electronic device 101 may include a processor 110, a memory 180, an input module 130, a display module 140, a power module 150, an internal module 190, and an external module 170. According to an embodiment, in the electronic device 101, at least one of the components described above may be omitted, or one or more other components may be added. According to an embodiment, some of the components described above (for example, a sensor module 191, an antenna module 192, or a sound output module 193) may be integrated into another component (for example, the display module 140). In an embodiment, the processor 110 may execute software to control at least another component of the electronic device 101 (for example, a hardware or software component) connected to the processor 110, and perform various data processing or operations. The processor 110 or the main processor 111 may communicate with Figure 1A The processor 110 may store a command or data received from another component (e.g., the input module 130, the sensor module 191, or the communication module 173) in the volatile memory 181 as at least part of data processing or operation, and process the command or data stored in the volatile memory 181, and the result data may be stored in the non-volatile memory 182.

[0164] In an embodiment, the processor 110 may include a main processor 111 and an auxiliary processor 112. The main processor 111 may include one or more of a central processing unit (CPU) 111-1 and an application processor (AP). The main processor 111 may also include any one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). The main processor 111 may also include a neural processing unit (NPU) 111-3. NPU 111-3 is a processor that specifically processes an artificial intelligence model, and the artificial intelligence model can be generated by machine learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), and a deep Q network, or a combination of two or more of the above networks, but is not limited to the above examples. Additionally or alternatively, in addition to the hardware structure, the artificial intelligence model may also include a software structure. At least two of the above-mentioned processing unit and processor may be implemented as one integrated configuration (eg, a single chip), or each may be implemented as an independent configuration (eg, a plurality of chips).

[0165] In an embodiment, the auxiliary processor 112 may include a controller 112-1. The auxiliary processor 112 or the controller 112-1 may be connected to Figure 1A The controller 112-1 may include an interface conversion circuit and a timing control circuit. The controller 112-1 receives an image signal from the main processor 111, converts the data format of the image signal to correspond to the interface specification with the display module 140, and outputs the image data. The controller 112-1 may output various control signals required to drive the display module 140.

[0166] In an embodiment, the auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, a rendering circuit 112-4, etc. The data conversion circuit 112-2 may receive image data from the controller 112-1, compensate the image data to display an image with a desired brightness according to the characteristics of the electronic device 101 or the user's settings, or convert the image data to reduce power consumption or compensate for afterimages, etc. The gamma correction circuit 112-3 may convert the image data or the gamma reference voltage, etc. so that the image displayed in the electronic device 101 has a desired gamma characteristic. The rendering circuit 112-4 may receive image data from the controller 112-1, and render the image data in consideration of the pixel setting of the display panel 141 applied to the electronic device 101, etc. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may be integrated into another component (e.g., the main processor 111 or the controller 112-1). At least one of the data conversion circuit 112 - 2 , the gamma correction circuit 112 - 3 , and the rendering circuit 112 - 4 may be integrated into a data driver 143 to be described later.

[0167] In an embodiment, the memory 180 may store various data used by at least one component of the electronic device 101 (eg, the processor 110 or the sensor module 191) and input data or output data for commands related to the various data. Figure 1A The memory 180 may include at least one of a volatile memory 181 and a non-volatile memory 182.

[0168] In an embodiment, the input module 130 may receive commands or data from outside the electronic device 101 (e.g., a user or an external electronic device 102) to be used by a component of the electronic device 101 (e.g., the processor 110, the sensor module 191, or the sound output module 193).

[0169] The input module 130 may include a first input module 131 into which a command or data from a user is input and a second input module 132 into which a command or data from an external electronic device 102 is input. The first input module 131 may include a microphone, a mouse, a keyboard, a key (e.g., a button) or a pen (e.g., a passive pen or an active pen). The second input module 132 may support a specified protocol that can be connected to the external electronic device 102 in a wired or wireless manner. According to an embodiment, the second input module 132 may include a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface. The second input module 132 may include a connector that can be physically connected to the external electronic device 102, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0170] In an embodiment, the display module 140 may visually provide information to a user. The display module 140 may include a display panel 141, a scan driver 142, and a data driver 143. The display module 140 may further include a window, a base, and a bracket for protecting the display panel 141.

[0171] In an embodiment, the display panel 141 may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, and the type of the display panel 141 is not particularly limited. The display panel 141 may be a rigid type or a flexible type that can be rolled or folded. The display module 140 may further include a support, a bracket, or a heat dissipation member that supports the display panel 141. The display panel 141 may be connected to the display module 140. Figure 1A Corresponding to the pixel unit 14.

[0172] In an embodiment, the scan driver 142 may be mounted on the display panel 141 as a driving chip. In addition, the scan driver 142 may be integrated in the display panel 141. The scan driver 142 may be connected to the display panel 141. Figure 1A The scan driver 142 corresponds to the scan driver 13 of the display panel 141. For example, the scan driver 142 may include an amorphous silicon thin film transistor (TFT) gate driver circuit (ASG), a low temperature polysilicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) built in the display panel 141. The scan driver 142 receives a control signal from the controller 112-1 and outputs a scan signal to the display panel 141 in response to the control signal.

[0173] In an embodiment, the display panel 141 may further include an emission driver. The emission driver outputs an emission control signal to the display panel 141 in response to a control signal received from the controller 112-1. The emission driver may be formed separately from the scan driver 142 or integrated into the scan driver 142. Figure 1A Corresponding to the transmitting driver 15.

[0174] In an embodiment, the data driver 143 receives a control signal from the controller 112-1, converts the image data into an analog voltage (eg, a data voltage) in response to the control signal, and then outputs the data voltage to the display panel 141. The data driver 143 may be connected to the display panel 141. Figure 1A Corresponding to a part of the controller 11.

[0175] In an embodiment, the data driver 143 may be integrated into another component (eg, the controller 112 - 1 ). The functions of the interface conversion circuit and the timing control circuit of the controller 112 - 1 described above may be integrated into the data driver 143 .

[0176] In an embodiment, the display module 140 may further include an emission driver and a voltage generating circuit, etc. The voltage generating circuit may output various voltages required to drive the display panel 141 .

[0177] In an embodiment, the power module 150 supplies power to the components of the electronic device 101. The power module 150 may include a battery that charges the power voltage. The battery may include a non-rechargeable primary battery and a rechargeable secondary battery or a fuel cell. The power module 150 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the above-mentioned modules and the modules to be described later. The power module 150 may include a wireless power transmission / reception component electrically connected to the battery. The wireless power transmission / reception component may include a plurality of antenna radiators in the form of a coil.

[0178] In an embodiment, the electronic device 101 may further include an internal module 190 and an external module 170. The internal module 190 may include a sensor module 191, an antenna module 192, and a sound output module 193. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0179] In an embodiment, the sensor module 191 may sense an input through the user's body or an input through a pen in the first input module 131, and may generate an electrical signal or data value corresponding to the input. The sensor module 191 may include at least one of a fingerprint sensor 191-1, an input sensor 191-2, and a digitizer 191-3.

[0180] In an embodiment, the fingerprint sensor 191-1 may generate a data value corresponding to the user's fingerprint. The fingerprint sensor 191-1 may include any one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0181] In an embodiment, the input sensor 191-2 may generate a data value corresponding to the coordinate information of the input through the user's body or the pen. The input sensor 191-2 generates the amount of capacitance change caused by the input as a data value. The input sensor 191-2 may sense the input through the passive pen, or may send data to / receive data from the active pen.

[0182] In an embodiment, the input sensor 191-2 may measure a biometric signal such as blood pressure, moisture, or body fat. For example, when the user touches the sensor layer or the sensing panel with a body part and does not move during a certain period of time, the input sensor 191-2 may sense the biometric signal based on a change in the electric field caused by the body part, and output the information desired by the user to the display module 140.

[0183] In an embodiment, the digitizer 191-3 may generate a data value corresponding to the coordinate information input by the pen. The digitizer 191-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 191-3 may sense the input through the passive pen, or send data to or receive data from the active pen.

[0184] In an embodiment, at least one of the fingerprint sensor 191-1, the input sensor 191-2, and the digitizer 191-3 may be implemented as a sensor layer formed on the display panel 141 through a continuous process. The fingerprint sensor 191-1, the input sensor 191-2, and the digitizer 191-3 may be disposed on the display panel 141, and any one of the fingerprint sensor 191-1, the input sensor 191-2, and the digitizer 191-3 (e.g., the digitizer 191-3) may be disposed under the display panel 141.

[0185] In an embodiment, at least two of the fingerprint sensor 191-1, the input sensor 191-2, and the digitizer 191-3 may be formed to be integrated into one sensing panel by the same process. When at least two of the fingerprint sensor 191-1, the digitizer 191-3, and the input sensor 191-2 are integrated into one sensing panel, the sensing panel may be disposed between the display panel 141 and a window disposed above the display panel 141. According to an embodiment, the sensing panel may be disposed on the window, and the position of the sensing panel is not particularly limited. In an embodiment, at least one of the fingerprint sensor 191-1, the input sensor 191-2, and the digitizer 191-3 may be embedded in the display panel 141. That is, at least one of the fingerprint sensor 191-1, the input sensor 191-2, and the digitizer 191-3 may be formed simultaneously by a process of forming an element (e.g., a light emitting element and a transistor, etc.) included in the display panel 141.

[0186] In an embodiment, the sensor module 191 may generate an electrical signal or a data value corresponding to an internal state or an external state of the electronic device 101. The sensor module 191 may also include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0187] In an embodiment, the antenna module 192 may include one or more antennas for sending signals or power to the outside or receiving signals or power from the outside. According to an embodiment, the communication module 173 may send a signal to an external electronic device or receive a signal from an external electronic device through an antenna suitable for the communication method. The antenna pattern of the antenna module 192 may be integrated into a configuration of the display module 140 (e.g., the display panel 141) or the input sensor 191-2. In an embodiment, the sound output module 193 is a device for outputting a sound signal to the outside of the electronic device 101, and may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver specifically for receiving calls. According to an embodiment, the receiver may be formed integrally with the speaker or separately from the speaker. The sound output pattern of the sound output module 193 may be integrated into the display module 140.

[0188] In an embodiment, the camera module 171 can capture still images and moving images. According to the embodiment, the camera module 171 may include one or more lenses, image sensors, or image signal processors. The camera module 171 may also include an infrared camera capable of measuring the presence or absence of a user, the position of the user, and the sight of the user, etc.

[0189] In an embodiment, the light module 172 may provide light. The light module 172 may include a light emitting diode or a xenon lamp. The light module 172 may operate in conjunction with the camera module 171 or may operate independently.

[0190] In an embodiment, the communication module 173 may support the establishment of a wired or wireless communication channel between the electronic device 101 and the external electronic device 102 and the communication execution through the established communication channel. The communication module 173 may include any one or both of a wireless communication module such as a cellular communication module, a short-range wireless communication module or a global navigation satellite system (GNSS) communication module and a wired communication module such as a local area network (LAN) communication module or a power line communication module. The communication module 173 may communicate with the external electronic device 102 through a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct connection or infrared data association (IrDA) or a long-range communication network such as a cellular network, the Internet or a computer network (e.g., LAN or wide area network (WAN)). The above-mentioned various types of communication modules 173 may be implemented as a single chip or a separate chip. In an embodiment, the input module 130, the sensor module 191 and the camera module 171, etc., may be used to control the operation of the display module 140 in conjunction with the processor 110.

[0191] In an embodiment, the processor 110 outputs a command or data to the display module 140, the sound output module 193, the camera module 171, or the optical module 172 based on the input data received from the input module 130. For example, the processor 110 may generate image data in response to input data applied through a mouse or an active pen, etc. and output the image data to the display module 140, or generate command data in response to the input data and output the command data to the camera module 171 or the optical module 172. When input data is not received from the input module 130 for a certain period of time, the processor 110 may convert the operation mode of the electronic device 101 into a low power mode or a sleep mode to reduce the power consumed in the electronic device 101.

[0192] In an embodiment, the processor 110 outputs a command or data to the display module 140, the sound output module 193, the camera module 171, or the optical module 172 based on the sensing data received from the sensor module 191. For example, the processor 110 may compare the authentication data applied by the fingerprint sensor 191-1 with the authentication data stored in the memory 180, and then execute an application program according to the comparison result. The processor 110 may execute a command based on the sensing data sensed by the input sensor 191-2 or the digitizer 191-3 or output the corresponding image data to the display module 140. When the sensor module 191 includes a temperature sensor, the processor 110 may receive temperature data for measuring temperature from the sensor module 191, and further perform brightness correction, etc. on the image data based on the temperature data.

[0193] In an embodiment, the processor 110 may receive measurement data for the presence of a user, the position of a user, and the sight of a user from the camera module 171. The processor 110 may further perform brightness correction on the image data based on the measurement data. For example, the processor 110, which determines the presence or absence of a user through an input from the camera module 171, may output image data whose brightness has been corrected through the data conversion circuit 112-2 or the gamma correction circuit 112-3 to the display module 140. In an embodiment, some of the above components may be connected to each other through a communication method between peripheral devices (e.g., a bus, a general purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or a super path interconnect (UPI) link) to exchange signals (e.g., commands or data) with each other. The processor 110 may communicate with the display module 140 through a mutually agreed interface (e.g., any one of the communication methods described above may be used), and is not limited to the communication method described above.

[0194] The electronic device 101 according to various embodiments may be various types of devices. For example, the electronic device 101 may include at least one of, for example, a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. The electronic device 101 is not limited to the above devices.

[0195] Although the present invention has been particularly shown and described with reference to embodiments of the present invention, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the present invention. Therefore, it will be understood that the foregoing is an illustration of various embodiments and is not to be construed as being limited to the specific embodiments disclosed, and modifications to the present invention are intended to be included within the scope of the present invention. In addition, embodiments or portions of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A controller, wherein: The controller comprises: A receiving interface configured to receive a first frame of data and a first vertical synchronization data packet; and A sending interface, configured to send a first frame request signal, When a first period from the time point when the receiving interface completes receiving the first frame data to the time point when the receiving interface starts receiving the first vertical synchronization data packet is longer than a first reference period, the sending interface sends the first frame request signal.

2. The controller according to claim 1, wherein: The first frame request signal is sent after the time point of completing receiving the second frame data.

3. The controller according to claim 2, wherein: The first frame data and the second frame data are different image data.

4. The controller according to claim 2, wherein: When the first frame request signal is sent, a second vertical synchronization data packet is received.

5. The controller according to claim 4, wherein: receiving a third frame of data after receiving the second vertical synchronization data packet, and The third frame data and the second frame data are the same image data.

6. The controller according to claim 5, wherein: A second frame request signal is sent after the time point of completing receiving the third frame data.

7. The controller according to claim 6, wherein: A second period from the time point at which the reception of the second frame data is completed to the time point at which the reception of the second vertical synchronization data packet starts is shorter than the first period.

8. The controller according to claim 7, wherein: A third period from the time point of completing receiving the third frame data to the time point of starting receiving the third vertical synchronization data packet is equal to the second period.

9. The controller according to claim 1, wherein: When the first period is shorter than the first reference period and longer than the second reference period, the receiving interface further receives a plurality of frame data, and When the first period is shorter than the first reference period and the number of frames longer than the second reference period is consistent with the number of reference frames, the sending interface sends the first frame request signal after completing the time point of receiving the second frame data which is the last frame data among the multiple frame data.

10. The controller according to claim 9, wherein: When the first frame request signal is sent, receiving a second vertical synchronization data packet, wherein, after receiving the second vertical synchronization data packet, receiving the third frame data, The third frame data and the second frame data are the same image data. wherein, after the time point of completing receiving the third frame data, a second frame request signal is sent, wherein a second period from the time point at which the second frame of data is received to the time point at which the second vertical synchronization data packet is received is shorter than the first period, and The third time period from the time point of completing the reception of the third frame data to the time point of starting to receive the third vertical synchronization data packet is equal to the second time period.

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