Row driving buffer, display panel, driving and control method and display device

Abstract

The invention provides a row driving buffer, a display panel, a driving and control method and a display device. The row driving buffer comprises a control switch logic circuit and a buffer circuit; the output end of the buffer circuit is electrically connected with the driving output end; the control switch logic circuit is electrically connected with an enabling control end, an input signal end and a control end of the buffer circuit, and is used for providing an input signal provided by the input signal end to the driving output end through the buffer circuit when the enabling control end provides an effective enabling control signal, so that the driving output end drives the driving circuit to drive the driving circuit to drive the driving circuit to drive the driving circuit to drive the driving circuit to drive the driving circuit to drive the driving circuit. And when the enable control end provides an invalid enable control signal, the buffer circuit is controlled to stop providing the input signal to the drive output end. According to the invention, the isolation function of a normal working mode and an AOI (Automatic Optical Inspection) test mode can be compatible.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a row drive buffer, a display panel, a driving and control method, and a display device. Background Art

[0002] The associated row driver buffer is not compatible with the isolation function of the normal operating mode and the AOI (Automatic Optical Inspection) test mode. Summary of the invention

[0003] The main purpose of the present invention is to provide a row drive buffer, a display panel, a driving and control method and a display device to solve the problem of the isolation function that is not compatible with the normal working mode and the AOI (automatic optical inspection) test mode in the related art.

[0004] In one aspect, an embodiment of the present invention provides a row driver buffer, comprising a control switch logic circuit and a buffer circuit; an output terminal of the buffer circuit is electrically connected to a driver output terminal;

[0005] The control switch logic circuit is electrically connected to the enable control terminal, the input signal terminal and the control terminal of the buffer circuit respectively, and is used for providing the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit when the enable control terminal provides a valid enable control signal, and controlling the buffer circuit to stop providing the input signal to the drive output terminal when the enable control terminal provides an invalid enable control signal.

[0006] Optionally, the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate and a control inverter; the buffer circuit includes a first control terminal and a second control terminal;

[0007] The first input terminal of the first NAND gate is electrically connected to the enable control terminal, the second input terminal of the first NAND gate is electrically connected to the input signal terminal, and the output terminal of the first NAND gate is electrically connected to the input terminal of the control transmission gate;

[0008] The first input terminal of the second NAND gate is electrically connected to the enable control terminal, the second input terminal of the second NAND gate is electrically connected to the inverting input signal terminal, and the output terminal of the second NAND gate is electrically connected to the input terminal of the control inverter;

[0009] The output end of the control transmission gate is electrically connected to the first control end, and the output end of the control inverter is electrically connected to the second control end;

[0010] The control transmission gate is used to provide the signal connected to its input terminal to the first control terminal;

[0011] The control inverter is used for inverting a signal connected to its input terminal to obtain an inverted signal, and providing the inverted signal to the second control terminal.

[0012] Optionally, the buffer includes an inverter, and the inverter includes at least one first transistor and at least one second transistor;

[0013] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the driving output terminal;

[0014] The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the driving output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0015] Optionally, the first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0016] In a second aspect, an embodiment of the present invention provides a display panel, including a driving module, wherein the driving module includes N of the above-mentioned row driving buffers; N is an integer greater than 1.

[0017] The display panel described in at least one embodiment of the present invention includes multiple rows of scan lines; the nth row drive buffer includes an nth drive output terminal; n is a positive integer less than or equal to N; and the nth drive output terminal is electrically connected to the nth row of scan lines.

[0018] Optionally, the driving module further includes a test control switch circuit;

[0019] The test control switch circuit includes N switch sub-circuits;

[0020] The control end of the nth switch subcircuit is electrically connected to the test control line, the first end of the nth switch subcircuit is electrically connected to the test signal line, the second end of the nth switch subcircuit is electrically connected to the nth drive output end, and the nth switch subcircuit is used to control the connection between the test signal line and the nth drive output end when the test control line provides a valid test control signal, and control the disconnection between the test signal line and the nth drive output end when the test control line provides an invalid test control signal.

[0021] Optionally, the nth switch subcircuit includes an nth transmission gate; the test control line includes a positive phase test control line and a negative phase test control line;

[0022] The input end of the nth transmission gate is electrically connected to the test signal line, and the output end of the nth transmission gate is electrically connected to the nth driving output end;

[0023] The positive phase control terminal of the nth transmission gate is electrically connected to the positive phase test control line, and the negative phase control terminal of the nth transmission gate is electrically connected to the negative phase test control line.

[0024] Optionally, the test signal line is directly electrically connected to the first ends of the N switch sub-circuits.

[0025] The display panel described in at least one embodiment of the present invention further includes a shift register and a level converter;

[0026] The shift register includes a multi-stage shift register unit, and the level converter includes a multi-stage level conversion unit;

[0027] The n-th stage shift register unit is electrically connected to the n-th stage level conversion unit, and is used to provide an n-th driving signal to the n-th stage level conversion unit;

[0028] The n-th level conversion unit is electrically connected to the n-th row driving buffer, and is used to perform level conversion on the n-th driving signal, and provide the level-converted n-th driving signal to the n-th row driving buffer.

[0029] The display panel described in at least one embodiment of the present invention includes a plurality of rows and columns of pixel circuits, and the driving module includes a first driving module, a second driving module and a third driving module;

[0030] The first driving module is used to provide the pixel circuit with a first scanning signal for controlling the writing of data voltage;

[0031] The second driving module is used to provide the pixel circuit with a second scanning signal for light emission control;

[0032] The third driving module is used to provide the pixel circuit with a third scanning signal for initialization control;

[0033] The first driving module includes a first row driving buffer, the second driving module includes a second row driving buffer, and the third driving module includes a third row driving buffer; the first row driving buffer includes a first buffer, the second row driving buffer includes a second buffer, and the third row driving buffer includes a third buffer;

[0034] The first buffer includes A first transistors connected in parallel and A second transistors connected in parallel, the second buffer includes B first transistors connected in parallel and B second transistors connected in parallel, and the third buffer includes C first transistors connected in parallel and C second transistors connected in parallel;

[0035] A is greater than B, A is greater than C; A, B and C are all positive integers.

[0036] The display panel according to at least one embodiment of the present invention comprises a first test signal line, a second test signal line and a third test signal line; the first driving module comprises a first test control switch circuit, the second driving module comprises a second test control switch circuit, and the third driving module comprises a third test control switch circuit;

[0037] The first driving module includes a plurality of first row driving buffers arranged in sequence along a first direction, and the first test signal line extends along the first direction; the first test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in the first test control switch circuit;

[0038] The second driving module includes a plurality of second row driving buffers arranged in sequence along a first direction, and the second test signal line extends along the first direction; the second test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in the second test control switch circuit;

[0039] The third driving module includes a plurality of third row driving buffers arranged in sequence along the first direction, and the third test signal line extends along the first direction; the third test signal line is directly electrically connected to the first ends of the plurality of switch sub-circuits included in the third test control switch circuit. Optionally, the driving module includes a multi-stage driving circuit and at least one stage of dummy driving circuit; the dummy driving circuit includes at least one dummy row driving buffer; the display panel includes at least one row of dummy pixel circuits;

[0040] The dummy row driving buffer in the last stage dummy driving circuit included in the driving module is electrically connected to the corresponding test signal line and the last row dummy pixel circuit respectively.

[0041] In a third aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned row driver buffer, and the driving method includes:

[0042] When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit;

[0043] When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the driving output terminal.

[0044] In a fourth aspect, an embodiment of the present invention provides a control method, which is applied to the above-mentioned display panel, and is characterized in that the control method includes:

[0045] When the display panel is in the optical detection stage, the enable control terminal provides an invalid enable control signal, controls the switch logic circuit to control the buffer circuit to stop providing the input signal to the drive output terminal, and the switch subcircuit controls the connection between the test signal line and the corresponding drive output terminal under the control of the test control signal;

[0046] When the display panel is in the display stage, the enable control terminal provides a valid enable control signal, and the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit. Under the control of the test control signal, the switch sub-circuit controls the disconnection between the test signal line and the corresponding drive output terminal.

[0047] In a fifth aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0048] The row driver buffer, display panel, driving and control method and display device described in the embodiments of the present invention are compatible with the isolation function of the normal working mode and the AOI (automatic optical inspection) test mode, and the state of the row driver buffer can be controlled to be on or off through the enable control signal, thereby achieving isolation between the normal working mode and the AOI test mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a structural diagram of a row driver buffer according to an embodiment of the present invention;

[0050] Figure 2 is a structural diagram of a row driver buffer according to at least one embodiment of the present invention;

[0051] Figure 3 is a circuit diagram of a row driver buffer according to at least one embodiment of the present invention;

[0052] Figure 4 is a structural diagram of a row driver buffer according to at least one embodiment of the present invention;

[0053] Figure 5A It is a waveform diagram of a scanning signal with strong driving capability provided by the driving output terminal OT;

[0054] Figure 5B It is a waveform diagram of a scan signal with a weak driving capability provided by the driving output terminal OT;

[0055] Figure 6 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0056] Figure 7 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0057] Figure 8is a circuit diagram of a driving module according to at least one embodiment of the present invention;

[0058] Fig. 9A yes Figure 8 A schematic diagram of the working state of at least one embodiment of the driving module shown;

[0059] Fig. 9B yes Figure 8 A schematic diagram of the working state of at least one embodiment of the driving module shown;

[0060] Fig.10 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0061] Fig.11 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0062] Fig. 12A is a circuit diagram of a driving module according to at least one embodiment of the present invention;

[0063] Fig. 12B yes Fig. 12A The circuit diagram of the shift register chip SRC in FIG.

[0064] Fig. 12C yes Fig. 12A Circuit diagram of the level converter chip LSC in FIG.

[0065] Fig.12D yes Fig. 12A A circuit diagram of a row driver buffer chip LDC;

[0066] Fig.13 is a circuit diagram of a plurality of row driver buffers according to at least one embodiment of the present invention;

[0067] Fig.14 is a partial layout diagram of at least one embodiment of a drive module;

[0068] Fig.15 is Fig.14 Layout diagram of adding signal lines based on . DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0071] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0072] like Figure 1 As shown, the row driving buffer according to the embodiment of the present invention comprises a control switch logic circuit 11 and a buffer circuit 12; the output end of the buffer circuit 12 is electrically connected to the driving output end OT;

[0073] The control switch logic circuit 11 is electrically connected to the enable control terminal LD_EN, the input signal terminal SI and the control terminal of the buffer circuit 12 respectively, and is used for providing the input signal provided by the input signal terminal SI to the drive output terminal OT through the buffer circuit 12 when the enable control terminal LE_EN provides a valid enable control signal, and controlling the buffer circuit 12 to stop providing the input signal to the drive output terminal OT when the enable control terminal LD_EN provides an invalid enable control signal.

[0074] The row driver buffer described in the embodiment of the present invention includes a control switch logic circuit and a buffer circuit. When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal to the drive output terminal through the buffer circuit; when the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the drive output terminal, so as to control the drive output terminal to be in a high impedance state. At this time, the external test input signal for AOI testing can be provided to the drive output terminal through the corresponding test signal line to perform AOI testing. The row driver buffer described in the embodiment of the present invention can be compatible with the isolation function of the normal working mode and the AOI test mode, and the state of the row driver buffer can be controlled to be on or off by the enable control signal, thereby realizing the isolation of the normal working mode and the AOI test mode.

[0075] The row driver buffer described in at least one embodiment of the present invention not only has the function of enhancing the driving capability, but also has the function of switching between the normal working mode and the AOI (automatic optical inspection) test mode, which not only ensures a single path for signal transmission in the AOI test mode, but also protects the reliability of the driving module.

[0076] At least one embodiment of the present invention provides a row driving buffer applied to a driving module, wherein the driving module is mainly implemented by a digital circuit and provides a control signal for row driving of a pixel circuit array.

[0077] Line Driver is essentially a three-state buffer, whose output is controlled by the enable input. When the enable input provides a valid enable control signal, Line Driver realizes normal logic state output; when the enable input provides an invalid enable control signal, the output of Line Driver is in high impedance state, which is equivalent to a circuit break. The core function of the line driver buffer is to enhance the driving capability of the signal without changing the signal logic. Therefore, Line Driver can be used as the last stage of the driving module to enhance the driving capability of the line drive signal before entering the pixel circuit array.

[0078] The driving signal output by the driving module controls the gate of the switching transistor in the pixel circuit (the first electrode of the switching transistor can be electrically connected to the data line, and the second electrode of the switching transistor can be electrically connected to the driving transistor), and the switching timing of the switching transistor determines the working logic of the pixel circuit. If the response speed of the switching transistor is slow, the grayscale voltage may not be written into the pixel circuit in time, resulting in insufficient charging rate and poor display uniformity. Therefore, Line Driver can improve the switching response time and optimize the instantaneous rise time and fall time of the driving signal, thereby ensuring that the charging rate meets the design specification requirements.

[0079] In at least one embodiment of the present invention, the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate and a control inverter; the buffer circuit includes a first control terminal and a second control terminal;

[0080] The first input terminal of the first NAND gate is electrically connected to the enable control terminal, the second input terminal of the first NAND gate is electrically connected to the input signal terminal, and the output terminal of the first NAND gate is electrically connected to the input terminal of the control transmission gate;

[0081] The first input terminal of the second NAND gate is electrically connected to the enable control terminal, the second input terminal of the second NAND gate is electrically connected to the inverting input signal terminal, and the output terminal of the second NAND gate is electrically connected to the input terminal of the control inverter;

[0082] The output end of the control transmission gate is electrically connected to the first control end, and the output end of the control inverter is electrically connected to the second control end;

[0083] The control transmission gate is used to provide the signal connected to its input terminal to the first control terminal;

[0084] The control inverter is used for inverting a signal connected to its input terminal to obtain an inverted signal, and providing the inverted signal to the second control terminal.

[0085] In a specific implementation, the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate and a control inverter; the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate and a control inverter; the buffer circuit includes a first control terminal and a second control terminal; the first NAND gate performs a NAND operation on the enable control signal and the input signal, and provides the obtained signal to the input terminal of the control transmission gate; the second NAND gate performs a NAND operation on the enable control signal and the inverted input signal provided by the inverted input signal terminal, and provides the obtained signal to the input terminal of the control inverter.

[0086] like Figure 2 As shown, the control switch logic circuit includes a first NAND gate NAD1, a second NAND gate NAD2, a control transmission gate TGC and a control inverter FC; the buffer circuit includes a first control terminal CT1 and a second control terminal CT2;

[0087] The first input terminal of the first NAND gate NAD1 is electrically connected to the enable control terminal LD_EN, the second input terminal of the first NAND gate NAD1 is electrically connected to the input signal terminal SI, and the output terminal of the first NAND gate NAD1 is electrically connected to the input terminal of the control transmission gate TGC;

[0088] The first input terminal of the second NAND gate NAD2 is electrically connected to the enable control terminal, the second input terminal of the second NAND gate NAD2 is electrically connected to the inverting input signal terminal FSI, and the output terminal of the second NAND gate NAD2 is electrically connected to the input terminal of the control inverter FC;

[0089] The output end of the control transmission gate TGC is electrically connected to the first control terminal CT1, and the output end of the control inverter TGC is electrically connected to the second control terminal CT2;

[0090] The control transmission gate TGC is used to provide the signal connected to its input terminal to the first control terminal CT1;

[0091] The control inverter FC is used to invert the signal connected to its input terminal to obtain an inverted signal, and provide the inverted signal to the second control terminal CT2;

[0092] The positive phase control terminal of TGC is electrically connected to the high voltage terminal VDD, and the negative phase control terminal of TGC is electrically connected to the second low voltage terminal VSS2.

[0093] In at least one embodiment of the present invention, the buffer includes an inverter, and the inverter includes at least one first transistor and at least one second transistor;

[0094] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the driving output terminal;

[0095] The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the driving output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0096] In a specific implementation, the buffer may include at least one inverter, which includes a first transistor and a second transistor; the gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the drive output terminal; the gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the drive output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0097] Optionally, the first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0098] In at least one embodiment of the present invention, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a first low voltage terminal.

[0099] like Figure 3 As shown, in Figure 2 Based on at least one embodiment shown, the buffer includes an inverter, and the inverter includes a first transistor T1 and a second transistor T2;

[0100] The gate of T1 is electrically connected to the first control terminal CT1, the source of T1 is electrically connected to the high voltage terminal VDD, and the drain of T1 is electrically connected to the driving output terminal OT;

[0101] The gate of T2 is electrically connected to the second control terminal CT2, the source of T2 is electrically connected to the driving output terminal OT, and the drain of T2 is electrically connected to the first low voltage terminal VSS1;

[0102] T1 is a p-type transistor and T2 is an n-type transistor.

[0103] The present invention Figure 3 At least one embodiment of the row driver buffer shown in FIG. 1 is in operation.

[0104] When LD_EN provides a low voltage signal, SI provides a low voltage signal, and FSI provides a high voltage signal, NAD1 outputs a high voltage signal to the input of TGC, NAD2 outputs a high voltage signal to the input of FC, TGC outputs a high voltage signal to CT1, FC provides a low voltage signal to CT2, T1 and T2 are turned off, and OT is in a high impedance state;

[0105] When LD_EN provides a low voltage signal, SI provides a high voltage signal, and FSI provides a low voltage signal, NAD1 outputs a high voltage signal to the input of TGC, NAD2 outputs a high voltage signal to the input of FC, TGC outputs a high voltage signal to CT1, FC provides a low voltage signal to CT2, T1 and T2 are turned off, and OT is in a high impedance state;

[0106] When LD_EN provides a high voltage signal, SI provides a low voltage signal, and FSI provides a high voltage signal, NAD1 provides a high voltage signal to the input end of TGC, NAD2 provides a low voltage signal to the input end of FC, TGC outputs a high voltage signal to CT1, FC outputs a high voltage signal to CT2, T1 is turned off, T2 is turned on, OT is connected to VSS1, and OT outputs a low voltage signal;

[0107] When LD_EN provides a high voltage signal, SI provides a high voltage signal, and FSI provides a low voltage signal, NAD1 provides a low voltage signal to the input end of TGC, NAD2 provides a high voltage signal to the input end of FC, TGC outputs a low voltage signal to CT1, FC outputs a low voltage signal to CT2, T1 is turned on, T2 is turned off, OT is connected to VDD, and OT outputs a high voltage signal;

[0108] In at least one embodiment of the present invention, the row driver buffer may include an even number of inverters, thereby ensuring that when the enable control terminal provides a valid enable control signal, the signal connected to the input terminal of the row driver buffer and the signal output from the output terminal of the row driver buffer are both high voltage signals, or, are both low voltage signals.

[0109] exist Figure 3 In at least one embodiment shown, NAD1, NAD2, TGC and FC are equivalent to a first inverter, and T1 and T2 are equivalent to a second inverter.

[0110] In at least one embodiment of the present invention, the inverter may include a plurality of first transistors connected in parallel and a plurality of second transistors connected in parallel, so that more currents can be output simultaneously, thereby achieving an enhanced driving effect;

[0111] The display panel may include a first driving module, a second driving module and a third driving module;

[0112] The first driving module can be used to provide a first scanning signal, which is a row driving signal for controlling the writing of data voltage and is closely related to the charging rate of the pixel circuit, so a strong driving capability is required. The inverter included in the row driving buffer in the first driving module can use 32 first transistors connected in parallel with each other and 32 second transistors connected in parallel with each other;

[0113] The second driving module may be used to provide a second scanning signal, the second scanning signal is a row driving signal for light emission control, and the inverter included in the row driving buffer in the second driving module may use 8 first transistors connected in parallel with each other and 8 second transistors connected in parallel with each other;

[0114] The third driving module may be used to provide a third scanning signal, wherein the third scanning signal is a row driving signal for resetting the potential of the first electrode of the light emitting element, and the inverter included in the row driving buffer in the third driving module may use 8 first transistors connected in parallel with each other and 8 second transistors connected in parallel with each other;

[0115] The number of transistors used in the inverter included in the row driving buffer in the driving module can be adjusted and changed according to the pixel circuit driving requirements, and the number of transistors used can be selected based on the design requirements.

[0116] like Figure 4 As shown, in at least one embodiment of the present invention, the row driver buffer LD is essentially a three-state buffer. Compared with the related buffers, an enable control terminal LD_EN is newly added, and the enable control terminal LD_EN is used to provide an enable control signal, and the function of the enable control signal is to control whether the input signal can be transmitted to the driver output terminal. When LD_EN outputs a high voltage signal, LD is in a normal working state, that is, the input signal can pass through the LD output signal; when LD_EN outputs a low voltage signal, LD is in a cut-off state, that is, the input signal cannot pass through the LD output, and the driver output terminal is in a high impedance state. If a signal passes through the driver output terminal, it will not be fed back to the input signal terminal.

[0117] In at least one embodiment of the present invention, the main function of the row drive buffer is to keep the waveform amplitude of the scanning signal unchanged and enhance the driving ability of the scanning signal. The driving ability refers to the output signal of the previous driving circuit, which can be effectively responded to by the subsequent driving circuit within a specified time, that is, the voltage changes to the expected voltage value within the specified time. If the driving ability is insufficient, the output current will be insufficient, that is, the upper and lower edges of the scanning signal are not steep enough, and the time to maintain the expected voltage value within the specified time is short; especially in the display field, if the pixel charging rate requirements are to be met, the voltage of the scanning signal needs to be changed to the expected voltage within a limited rise time Tr and a limited fall time Tf, and it needs to be maintained for a sufficient effective time Ta.

[0118] Figure 5A It is the waveform diagram of the scanning signal with strong driving capability provided by the driving output terminal OT. Figure 5B It is a waveform diagram of a scan signal with a weak driving capability provided by the driving output terminal OT.

[0119] The display panel described in the embodiment of the present invention includes a driving module, and the driving module includes N of the above-mentioned row driving buffers; N is an integer greater than 1.

[0120] The display panel described in at least one embodiment of the present invention includes multiple rows of scan lines; the nth row drive buffer includes an nth drive output terminal; n is a positive integer less than or equal to N; and the nth drive output terminal is electrically connected to the nth row of scan lines.

[0121] In at least one embodiment of the present invention, the driving module further includes a test control switch circuit;

[0122] The test control switch circuit includes N switch sub-circuits;

[0123] The control end of the nth switch subcircuit is electrically connected to the test control line, the first end of the nth switch subcircuit is electrically connected to the test signal line, the second end of the nth switch subcircuit is electrically connected to the nth drive output end, and the nth switch subcircuit is used to control the connection between the test signal line and the nth drive output end when the test control line provides a valid test control signal, and control the disconnection between the test signal line and the nth drive output end when the test control line provides an invalid test control signal.

[0124] In a specific implementation, the driving module may include a test control switch circuit, and the test control switch circuit includes N switch sub-circuits;

[0125] In the display stage, the test control line provides an invalid test control signal, and the nth switch subcircuit controls the disconnection between the test signal line and the nth drive output terminal;

[0126] In the optical detection stage, the test control line provides a valid test control signal, and the nth switch subcircuit controls the connection between the test signal line and the nth driving output terminal to provide the test signal provided by the test signal line to the nth driving output terminal.

[0127] In at least one embodiment of the present invention, the nth switch subcircuit includes an nth transmission gate; the test control line includes a positive phase test control line and a negative phase test control line;

[0128] The input end of the nth transmission gate is electrically connected to the test signal line, and the output end of the nth transmission gate is electrically connected to the nth driving output end;

[0129] The positive phase control terminal of the nth transmission gate is electrically connected to the positive phase test control line, and the negative phase control terminal of the nth transmission gate is electrically connected to the negative phase test control line.

[0130] In a specific implementation, the nth switch subcircuit may include an nth transmission gate, which controls the connection or disconnection between the test signal line and the nth drive output terminal under the control of a positive phase test control signal provided by the positive phase test control line and an inverse phase test control signal provided by the inverse phase test control line.

[0131] In at least one embodiment of the present invention, the test signal line is directly electrically connected to the first ends of the N switch sub-circuits.

[0132] In a specific implementation, the test signal line can be directly electrically connected to the first ends of N switch sub-circuits. The extension direction of the test signal line is roughly the same as the extension direction of the data line. The test signal line runs through all rows from top to bottom. Each switch sub-circuit directly obtains the test signal from the test signal line. If a row of switch sub-circuits fails, it will not affect the AOI inspection of other rows, and will not hinder the level transmission of the AOI test signal. The above setting avoids the problem of being completely unable to perform AOI testing due to component failure.

[0133] like Figure 6 As shown, the driving module described in at least one embodiment of the present invention includes a first row driving buffer LD1, a second row driving buffer LD2 and a third row driving buffer LD3;

[0134] The display panel described in at least one embodiment of the present invention includes a first row of scan lines S1, a second row of scan lines S2 and a third row of scan lines S3;

[0135] The first row driving buffer LD1 comprises a first driving output terminal OT1; the first driving output terminal OT1 is electrically connected to the first row scanning line S1;

[0136] The second row driving buffer LD2 comprises a second driving output terminal OT2; the second driving output terminal OT2 is electrically connected to the second row scanning line S2;

[0137] The third row driving buffer LD3 comprises a third driving output terminal OT3; the third driving output terminal OT3 is electrically connected to the third row scanning line S3;

[0138] At least one embodiment of the driving module further includes a test control switch circuit;

[0139] The test control switch circuit includes a first switch subcircuit K1, a second switch subcircuit K2 and a third switch subcircuit K3;

[0140] The control end of the first switch sub-circuit K1 is electrically connected to the test control line EN, the first end of the first switch sub-circuit K1 is electrically connected to the test signal line G_A, the second end of the first switch sub-circuit K1 is electrically connected to the first drive output terminal OT1, and the first switch sub-circuit K1 is used to control the connection between the test signal line G_A and the first drive output terminal OT1 when the test control line EN provides a valid test control signal, and control the disconnection between the test signal line G_A and the first drive output terminal OT1 when the test control line EN provides an invalid test control signal;

[0141] The control end of the second switch sub-circuit K2 is electrically connected to the test control line EN, the first end of the second switch sub-circuit K2 is electrically connected to the test signal line G_A, the second end of the second switch sub-circuit K2 is electrically connected to the second drive output terminal OT2, and the second switch sub-circuit K2 is used to control the connection between the test signal line G_A and the second drive output terminal OT2 when the test control line EN provides a valid test control signal, and control the disconnection between the test signal line G_A and the second drive output terminal OT2 when the test control line EN provides an invalid test control signal;

[0142] The control end of the third switch sub-circuit K3 is electrically connected to the test control line EN, the first end of the third switch sub-circuit K3 is electrically connected to the test signal line G_A, the second end of the third switch sub-circuit K3 is electrically connected to the third drive output terminal OT3, and the third switch sub-circuit K3 is used to control the connection between the test signal line G_A and the third drive output terminal OT3 when the test control line EN provides a valid test control signal, and control the disconnection between the test signal line G_A and the third drive output terminal OT3 when the test control line EN provides an invalid test control signal.

[0143] like Figure 7 As shown, in Figure 6 Based on at least one embodiment shown,

[0144] The first switch sub-circuit includes a first transmission gate TG1; the test control line includes a positive phase test control line EN_A and a negative phase test control line EN_A';

[0145] The input end of the first transmission gate TG1 is electrically connected to the test signal line G_A, and the output end of the first transmission gate TG1 is electrically connected to the first driving output end OT1;

[0146] The positive phase control terminal of the first transmission gate TG1 is electrically connected to the positive phase test control line EN_A, and the negative phase control terminal of the first transmission gate TG1 is electrically connected to the negative phase test control line EN_A′;

[0147] The second switch sub-circuit comprises a second transmission gate TG2;

[0148] The input end of the second transmission gate TG2 is electrically connected to the test signal line G_A, and the output end of the second transmission gate TG2 is electrically connected to the second driving output end OT2;

[0149] The positive phase control terminal of the second transmission gate TG2 is electrically connected to the positive phase test control line EN_A, and the negative phase control terminal of the second transmission gate TG2 is electrically connected to the negative phase test control line EN_A′;

[0150] The third switch sub-circuit comprises a third transmission gate TG3;

[0151] The input end of the third transmission gate TG3 is electrically connected to the test signal line G_A, and the output end of the third transmission gate TG3 is electrically connected to the third driving output end OT3;

[0152] A positive phase control terminal of the third transmission gate TG3 is electrically connected to the positive phase test control line EN_A, and a negative phase control terminal of the third transmission gate TG3 is electrically connected to the negative phase test control line EN_A′.

[0153] like Figure 8 As shown, in Figure 7 Based on at least one embodiment shown,

[0154] The first transmission gate includes a first first NAND gate NAD11, a first second NAND gate NAD12, a first control transmission gate TGC1, a first control inverter FC1, a first first transistor T11 and a first second transistor T12;

[0155] The first input terminal of the first first NAND gate NAD11 is electrically connected to the enable control terminal LD_EN, the second input terminal of the first first NAND gate NAD11 is electrically connected to the first input signal terminal SI1, and the output terminal of the first first NAND gate NAD11 is electrically connected to the input terminal of the first control transmission gate TGC1;

[0156] The first input terminal of the first second NAND gate NAD12 is electrically connected to the enable control terminal LD_EN, the second input terminal of the first second NAND gate NAD12 is electrically connected to the first inverting input signal terminal FSI1, and the output terminal of the first second NAND gate NAD12 is electrically connected to the input terminal of the first control inverter FC1;

[0157] The output end of the first control transmission gate TGC1 is electrically connected to the first first control terminal CT11, and the output end of the first control inverter TGC1 is electrically connected to the first second control terminal CT12;

[0158] The first control transmission gate TGC1 is used to provide the signal connected to its input terminal to the first first control terminal CT11;

[0159] The first control inverter FC1 is used to invert the signal connected to its input terminal to obtain an inverted signal, and provide the inverted signal to the first second control terminal CT12;

[0160] The positive phase control terminal of TGC1 is electrically connected to the high voltage terminal VDD, and the negative phase control terminal of TGC1 is electrically connected to the second low voltage terminal VSS2;

[0161] The gate of T11 is electrically connected to CT11, the source of T11 is electrically connected to the high voltage terminal VDD, and the drain of T11 is electrically connected to OT1;

[0162] The gate of T12 is electrically connected to CT12, the source of T12 is electrically connected to OT1, and the drain of T12 is electrically connected to the first low voltage terminal VSS1;

[0163] The second transmission gate includes a second first NAND gate NAD21, a second second NAND gate NAD22, a second control transmission gate TGC2, a second control inverter FC2, a second first transistor T21 and a second second transistor T22;

[0164] The first input terminal of the second first NAND gate NAD21 is electrically connected to the enable control terminal LD_EN, the second input terminal of the second first NAND gate NAD21 is electrically connected to the second input signal terminal SI2, and the output terminal of the second first NAND gate NAD21 is electrically connected to the input terminal of the second control transmission gate TGC2;

[0165] The first input terminal of the second second NAND gate NAD22 is electrically connected to the enable control terminal LD_EN, the second input terminal of the second second NAND gate NAD22 is electrically connected to the second inverting input signal terminal FSI2, and the output terminal of the second second NAND gate NAD22 is electrically connected to the input terminal of the second control inverter FC2;

[0166] The output end of the second control transmission gate TGC2 is electrically connected to the second first control terminal CT21, and the output end of the second control inverter TGC2 is electrically connected to the second second control terminal CT22;

[0167] The second control transmission gate TGC2 is used to provide the signal connected to its input terminal to the second first control terminal CT21;

[0168] The second control inverter FC2 is used to invert the signal connected to its input terminal to obtain an inverted signal, and provide the inverted signal to the second second control terminal CT22;

[0169] The positive phase control terminal of TGC2 is electrically connected to the high voltage terminal VDD, and the negative phase control terminal of TGC2 is electrically connected to the second low voltage terminal VSS2;

[0170] The gate of T21 is electrically connected to CT21, the source of T21 is electrically connected to the high voltage terminal VDD, and the drain of T21 is electrically connected to OT2;

[0171] The gate of T22 is electrically connected to CT22, the source of T22 is electrically connected to OT2, and the drain of T22 is electrically connected to the first low voltage terminal VSS1;

[0172] The third transmission gate includes a third first NAND gate NAD31, a third second NAND gate NAD32, a third control transmission gate TGC3, a third control inverter FC3, a third first transistor T31 and a third second transistor T32;

[0173] The first input terminal of the third first NAND gate NAD31 is electrically connected to the enable control terminal LD_EN, the second input terminal of the third first NAND gate NAD31 is electrically connected to the third input signal terminal SI3, and the output terminal of the third first NAND gate NAD31 is electrically connected to the input terminal of the third control transmission gate TGC3;

[0174] The first input terminal of the third second NAND gate NAD32 is electrically connected to the enable control terminal LD_EN, the second input terminal of the third second NAND gate NAD32 is electrically connected to the third inverting input signal terminal FSI3, and the output terminal of the third second NAND gate NAD32 is electrically connected to the input terminal of the third control inverter FC3;

[0175] The output end of the third control transmission gate TGC3 is electrically connected to the third first control terminal CT31, and the output end of the third control inverter TGC3 is electrically connected to the third second control terminal CT32;

[0176] The third control transmission gate TGC3 is used to provide the signal connected to its input terminal to the third first control terminal CT31;

[0177] The third control inverter FC3 is used to invert the signal connected to its input terminal to obtain an inverted signal, and provide the inverted signal to the third second control terminal CT32;

[0178] The positive phase control terminal of TGC3 is electrically connected to the high voltage terminal VDD, and the negative phase control terminal of TGC3 is electrically connected to the second low voltage terminal VSS2;

[0179] The gate of T31 is electrically connected to CT31, the source of T31 is electrically connected to the high voltage terminal VDD, and the drain of T31 is electrically connected to OT3;

[0180] The gate of T32 is electrically connected to CT32 , the source of T32 is electrically connected to OT3 , and the drain of T32 is electrically connected to the first low voltage terminal VSS1 .

[0181] exist Figure 8 In at least one embodiment shown, T11 , T21 , and T31 are all p-type transistors, and T12 , T22 , and T32 are all n-type transistors.

[0182] Figure 8 When at least one embodiment shown is in operation, in the display stage, LD_EN provides a high voltage signal, EN_A provides a low voltage signal, and EN_A' provides a high voltage signal; Fig. 9A As shown, TG1, TG2 and TG3 are all turned off, G_A is controlled to be disconnected from OT1, G_A is controlled to be disconnected from OT2, and G_A is controlled to be disconnected from OT3;

[0183] When SI1 provides a high voltage signal and FSI1 provides a low voltage signal, NAD11 outputs a low voltage signal TGC1, TGC1 provides a low voltage signal to CT11, and T11 is turned on; NAD12 outputs a high voltage signal to FC1, FC1 outputs a low voltage signal to CT12, and T12 is turned off;

[0184] When SI1 provides a low voltage signal and FSI1 provides a high voltage signal, NAD11 outputs a high voltage signal to TGC1, TGC1 provides a high voltage signal to CT11, and T11 is turned off; NAD12 outputs a low voltage signal to FC1, FC1 outputs a high voltage signal to CT12, and T12 is turned on;

[0185] When SI2 provides a high voltage signal and FSI2 provides a low voltage signal, NAD21 outputs a low voltage signal TGC2, TGC2 provides a low voltage signal to CT21, and T21 is turned on; NAD22 outputs a high voltage signal to FC2, FC2 outputs a low voltage signal to CT22, and T22 is turned off;

[0186] When SI2 provides a low voltage signal and FSI2 provides a high voltage signal, NAD21 outputs a high voltage signal to TGC2, TGC2 provides a high voltage signal to CT21, and T21 is turned off; NAD22 outputs a low voltage signal to FC2, FC2 outputs a high voltage signal to CT22, and T22 is turned on;

[0187] When SI3 provides a high voltage signal and FSI3 provides a low voltage signal, NAD31 outputs a low voltage signal TGC3, TGC3 provides a low voltage signal to CT31, and T31 is turned on; NAD32 outputs a high voltage signal to FC3, FC3 outputs a low voltage signal to CT32, and T32 is turned off;

[0188] When SI3 provides a low voltage signal and FSI3 provides a high voltage signal, NAD31 outputs a high voltage signal to TGC3, TGC3 provides a high voltage signal to CT31, and T31 is turned off; NAD32 outputs a low voltage signal to FC3, FC3 outputs a high voltage signal to CT32, and T32 is turned on.

[0189] Figure 8 When at least one embodiment shown is in operation, in the optical detection stage, LD_EN provides a low voltage signal, EN_A provides a high voltage signal, and EN_A' provides a low voltage signal; Fig. 9B As shown, TG1, TG2 and TG3 are all turned on, controlling the connection between G_A and OT1, controlling the connection between G_A and OT2, and controlling the connection between G_A and OT3;

[0190] NAD11 outputs a high voltage signal to TGC1, TGC1 provides a high voltage signal to CT11, and T11 is turned off; NAD12 outputs a high voltage signal to FC1, FC1 provides a low voltage signal to CT12, and T12 is turned off;

[0191] NAD21 outputs a high voltage signal to TGC2, TGC2 provides a high voltage signal to CT21, and T21 is turned off; NAD22 outputs a high voltage signal to FC2, FC2 provides a low voltage signal to CT22, and T22 is turned off;

[0192] NAD31 outputs a high voltage signal to TGC3, TGC3 provides a high voltage signal to CT31, and T31 is turned off; NAD32 outputs a high voltage signal to FC3, FC3 provides a low voltage signal to CT32, and T32 is turned off.

[0193] Figure 8 When at least one embodiment shown is in operation, in the optical detection stage, TG1, TG2 and TG3 are all in the on state, and the test signal for AOI test is provided from the test signal line G_A to OT1, OT2 and OT3, and finally acts on the gate of the transistor in the pixel circuit. Since each row driver buffer is in a high-impedance state, the signal will not flow back to the row driver buffer, thereby protecting the driving module in the optical detection stage, that is, the row driver buffer realizes the isolation of the normal working mode and the AOI test mode.

[0194] The display panel described in at least one embodiment of the present invention further includes a shift register and a level converter;

[0195] The shift register includes a multi-stage shift register unit, and the level converter includes a multi-stage level conversion unit;

[0196] The n-th stage shift register unit is electrically connected to the n-th stage level conversion unit, and is used to provide the n-th stage driving signal to the n-th stage level conversion unit;

[0197] The n-th level conversion unit is electrically connected to the n-th row driving buffer, and is used to perform level conversion on the n-th driving signal, and provide the level-converted n-th driving signal to the n-th row driving buffer.

[0198] In a specific implementation, the display panel may further include a shift register and a level converter, the shift register including a multi-stage shift register unit, and the level converter including a multi-stage level conversion unit; the n-th stage shift register unit provides an n-th stage drive signal to the n-th stage level conversion unit; the n-th stage level conversion unit performs level conversion on the n-th drive signal, and provides the n-th drive signal after level conversion to the n-th row drive buffer.

[0199] like Fig.10 As shown, the n-th stage shift register unit 91 is electrically connected to the n-th stage level conversion unit 92, and is used to provide the n-th stage driving signal to the n-th stage level conversion unit 92;

[0200] The n-th level conversion unit 92 is electrically connected to the n-th row driving buffer 93 , and is used to perform level conversion on the n-th driving signal, and provide the level-converted n-th driving signal to the n-th row driving buffer 93 .

[0201] In at least one embodiment of the present invention, each shift register unit is mainly composed of a double edge trigger and a logic unit. The main function of the double edge trigger is to control the signal to be transmitted serially row by row, and there is a row period between rows; the main function of the logic unit is to generate a pixel circuit control timing by logically combining the control signal generated by the DDIC (display driver integrated circuit);

[0202] Since the display device adopts the Two Chip mode, the voltage output by the DDIC needs to support all modules in the BP (driving backplane), but the voltage domains required by different modules are different, so the signal similar to the control signal can only take into account the voltage requirements of most modules. For example, the high voltage of the control signal is 4.8V and the low voltage is 0V. However, the back gate voltage and source voltage of the reset transistor in the pixel circuit are negative voltages. In order to ensure the effective closure of the switch, the gate potential also needs to be set to a negative voltage (for example, -3.2V). Therefore, a level conversion unit is required to convert the low voltage of the output waveform into a negative voltage.

[0203] like Fig.11 As shown, the shift register includes a first-stage shift register unit SR1, a second-stage shift register unit SR2, a third-stage shift register unit SR3 and a fourth-stage shift register unit SR4;

[0204] The level converter comprises a first-stage level conversion unit LS1, a second-stage level conversion unit LS2, a third-stage level conversion unit LS3 and a fourth-stage level conversion unit LS4;

[0205] The driving module includes a first row driving buffer LD1, a second row driving buffer LD2, a third row driving buffer LD3 and a fourth row driving buffer LD4;

[0206] SR1 is electrically connected to the start voltage terminal STV, the control clock signal terminal CKV, the pulse control signal terminal PL and the first scan control pin GSD respectively;

[0207] SR1 may be electrically connected to LS1 through the first row first driving signal terminal G1_R1, the first row second driving signal terminal G2_R1, and the first row third driving signal terminal G3_R1, respectively;

[0208] SR2 may be electrically connected to LS2 through the second row first driving signal terminal G1_R2, the second row second driving signal terminal G2_R2, and the second row third driving signal terminal G3_R2, respectively;

[0209] SR3 may be electrically connected to LS3 through the third row first driving signal terminal G1_R3, the third row second driving signal terminal G2_R3, and the third row third driving signal terminal G3_R3, respectively;

[0210] SR4 may be electrically connected to LS4 through the fourth row first driving signal terminal G1_R4, the fourth row second driving signal terminal G2_R4, and the fourth row third driving signal terminal G3_R4, respectively;

[0211] G1_R1 is electrically connected to the first input terminal of SR2, G2_R1 is electrically connected to the second input terminal of SR2, and G3_R1 is electrically connected to the third input terminal of SR2;

[0212] G1_R2 is electrically connected to the first input terminal of SR3, G2_R2 is electrically connected to the second input terminal of SR3, and G3_R2 is electrically connected to the third input terminal of SR3;

[0213] G1_R3 is electrically connected to the first input terminal of SR4, G2_R3 is electrically connected to the second input terminal of SR4, and G3_R3 is electrically connected to the third input terminal of SR4;

[0214] LD1 is electrically connected to the first row first scan signal terminal G1_RW1, the first row second scan signal terminal G2_RW1 and the first row third scan signal terminal G3_RW1 respectively, and is used to provide the first row first scan signal through G1_RW1, the first row second scan signal through G2_RW1, and the first row third scan signal through G3_RW1;

[0215] LD2 is electrically connected to the second row first scan signal terminal G1_RW2, the second row second scan signal terminal G2_RW2, and the second row third scan signal terminal G3_RW2, respectively, and is used to provide the second row first scan signal through G1_RW2, the second row second scan signal through G2_RW2, and the second row third scan signal through G3_RW2;

[0216] LD3 is electrically connected to the third row first scan signal terminal G1_RW3, the third row second scan signal terminal G2_RW3 and the third row third scan signal terminal G3_RW3 respectively, and is used to provide the third row first scan signal through G1_RW3, the third row second scan signal through G2_RW3, and the third row third scan signal through G3_RW3;

[0217] LD4 is electrically connected to the fourth row first scan signal terminal G1_RW4, the fourth row second scan signal terminal G2_RW4 and the fourth row third scan signal terminal G3_RW4 respectively, and is used to provide the fourth row first scan signal through G1_RW4, the fourth row second scan signal through G2_RW4, and the fourth row third scan signal through G3_RW4.

[0218] exist Fig.11In the figure, B1 is a schematic diagram of the waveform of the signal output by the shift register unit, B2 is a schematic diagram of the waveform of the signal output by the level conversion unit, and B3 is a schematic diagram of the waveform of the signal output by the row driving buffer.

[0219] The display panel according to at least one embodiment of the present invention comprises a plurality of rows and columns of pixel circuits, such as Fig.11 As shown, the driving module includes a first driving module GA1, a second driving module GA2 and a third driving module GA3;

[0220] The first driving module GA1 is used to provide the pixel circuit with a first scanning signal for controlling data voltage writing;

[0221] The second driving module GA2 is used to provide the pixel circuit with a second scanning signal for light emission control;

[0222] The third driving module GA3 is used to provide the pixel circuit with a third scanning signal for initialization control;

[0223] The first driving module includes a first row driving buffer, the second driving module includes a second row driving buffer, and the third driving module includes a third row driving buffer; the first row driving buffer includes a first buffer, the second row driving buffer includes a second buffer, and the third row driving buffer includes a third buffer;

[0224] The first buffer includes A first transistors connected in parallel and A second transistors connected in parallel, the second buffer includes B first transistors connected in parallel and B second transistors connected in parallel, and the third buffer includes C first transistors connected in parallel and C second transistors connected in parallel;

[0225] A is greater than B, A is greater than C; A, B and C are all positive integers.

[0226] In a specific implementation, the first driving module GA1 provides a first scanning signal, the second driving module GA2 provides a second scanning signal, and the third driving module GA3 provides a third scanning signal. The first scanning signal is a row driving signal for controlling the writing of the data voltage, which is closely related to the charging rate of the pixel circuit and therefore requires a stronger driving capability. Therefore, the number of transistors included in the inverter included in the row driving buffer in the first driving module can be set to be greater than the number of transistors included in the inverter included in the row driving buffer in the second driving module, and the number of transistors included in the inverter included in the row driving buffer in the first driving module can be set to be greater than the number of transistors included in the inverter included in the row driving buffer in the third driving module.

[0227] In at least one embodiment of the present invention, the second scanning signal is a row driving signal for performing light emitting control; and the third scanning signal is a row driving signal for performing initialization control.

[0228] like Fig. 12A As shown, at least one embodiment of the driving module may include a shift register chip SRC, a level converter chip LSC and a row driver buffer chip LDC;

[0229] The shift register chip SRC comprises a first drive signal output pin WSn, a second drive signal output pin DSn and a third drive signal output pin AZn;

[0230] The level converter chip LSC includes a first drive signal access pin WSI, a second drive signal access pin DSI, a third drive signal access pin AZI, a first first drive signal providing pin WS_LS_OUT, a second first drive signal providing pin WS_LS_OUT', a first second drive signal providing pin DS_LS_OUT, a second second drive signal providing pin DS_LS_OUT', a first third drive signal providing pin AZ_LS_OUT and a second third drive signal providing pin AZ_LS_OUT';

[0231] The row driver buffer chip LDC includes a first first drive signal input pin WS, a second first drive signal input pin WS', a first second drive signal input pin DS, a second second drive signal input pin DS', a first third drive signal input pin AZ, a second third drive signal input pin, a first scan signal output pin WS_OUT, a second scan signal output pin DS_OUT and a third scan signal output pin AZ_OUT;

[0232] AZn is electrically connected to AZI, DSn is electrically connected to DSI, and WSn is electrically connected to WS;

[0233] AZ_LS_OUT1 is electrically connected to AZ, AZ_LS_OUT2 is electrically connected to AZ', DS_LS_OUT1 is electrically connected to DS, DS_LS_OUT2 is electrically connected to DS', WS_LS_OUT1 is electrically connected to WS, and WS_LS_OUT2 is electrically connected to WS'.

[0234] exist Fig. 12A In at least one embodiment shown, VSS1 is a first low voltage terminal, VSS2 is a second low voltage terminal, VDD is a high voltage terminal, and GND is a ground terminal;

[0235] The row driver buffer chip LDC further includes a first enable control pin LD_EN_WS, a second enable control pin LD_EN_DS and a third enable control pin LD_EN_AZ;

[0236] The shift register chip SRC also includes a first first control clock pin CKV_WS1, a second first control clock pin CKV_WS1, a second control clock pin CKV_DS, a third control clock pin CKV_AZ, a first control pulse pin CKV_LF_PULSE_DS, a second control pulse pin CKV_LF_PULSE_AZ, a first scan control pin GSD, a second scan control pin GSD', an input pin Rn, a first pin Dn_WS1, a second pin Dn_WS2, a third pin Dn_DS, a fourth pin Dn_AZ, a fifth pin Dn_LF_PULSE_DS, a sixth pin Dn_LF_PULSE_AZ, a seventh pin Q_INTER_WS1, an eighth pin Q_INTER_WS2, a ninth pin Q_INTER_DS, and a tenth pin Pin Q_INTER_AZ, eleventh pin Q_INTER_LF_PULSE_DS, twelfth pin Q_INTER_LF_PULSE_AZ, thirteenth pin Dn+1_WS1, fourteenth pin Dn+1_WS2, fifteenth pin Dn+1_DS, sixteenth pin Dn+1_AZ, seventeenth pin Dn+1_LF_PULSE_DS, eighteenth pin Dn+1_LF_PULSE_AZ, nineteenth pin Q_INTER+1_WS1, twentieth pin Q_INTER+1_WS2, twenty-first pin Q_INTER+1_DS, twenty-second pin Q_INTER+1_AZ, twenty-third pin Q_INTER+1_LF_PULSE_DS and twenty-fourth pin Q_INTER+1_LF_PULSE_AZ;

[0237] The one labeled GVDD is a high voltage port, and the one labeled GGND is a ground port;

[0238] The terminal labeled CKV1 is the first clock signal terminal, the terminal labeled CKV2 is the second clock signal terminal, the terminal labeled CKV3 is the third clock signal terminal, the terminal labeled CKV4 is the fourth clock signal terminal, the terminal labeled CKV5 is the fifth clock signal terminal, the terminal labeled CKV6 is the sixth clock signal terminal, the terminal labeled LD_EN1 is the first enable control terminal, the terminal labeled LD_EN2 is the second enable control terminal, and the terminal labeled LD_EN3 is the third enable control terminal.

[0239] Fig. 12B yes Fig. 12A The circuit diagram of the shift register chip SRC in the figure, Fig. 12C yes Fig. 12A The circuit diagram of the level converter chip LSC in the Fig.12D yes Fig. 12A Circuit diagram of the row driver buffer chip LDC.

[0240] The display panel according to at least one embodiment of the present invention comprises a first test signal line, a second test signal line and a third test signal line; the first driving module comprises a first test control switch circuit, the second driving module comprises a second test control switch circuit, and the third driving module comprises a third test control switch circuit;

[0241] The first driving module includes a plurality of first row driving buffers arranged in sequence along a first direction, and the first test signal line extends along the first direction; the first test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in the first test control switch circuit;

[0242] The second driving module includes a plurality of second row driving buffers arranged in sequence along a first direction, and the second test signal line extends along the first direction; the second test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in the second test control switch circuit;

[0243] The third driving module includes a plurality of third row driving buffers arranged in sequence along a first direction, and the third test signal line extends along the first direction; the third test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in a third test control switch circuit.

[0244] Optionally, the first direction may be a vertical direction.

[0245] like Fig.13 As shown, the line labeled G_A1 is the first test signal line, the line labeled G_A2 is the second test signal line, and the line labeled G_A3 is the third test signal line; G_A1, G_A2 and G_A3 extend in the vertical direction;

[0246] The first driving module includes a first test control switch circuit 121, and the first test control switch circuit 121 includes a first first switch sub-circuit K11, a second first switch sub-circuit K21 and a third first switch sub-circuit K31;

[0247] The second driving module includes a second test control switch circuit 122, and the second test control switch circuit 122 includes a first second switch sub-circuit K12, a second second switch sub-circuit K22 and a third second switch sub-circuit K32;

[0248] The third driving module includes a third test control switch circuit 123, and the third test control switch circuit 123 includes a first third switch sub-circuit K13, a second third switch sub-circuit K23 and a third third switch sub-circuit K33;

[0249] The first driving module includes a first first row driving buffer LD11, a second first row driving buffer LD21 and a third first row driving buffer LD31; LD11, LD21 and LD31 are arranged in a vertical direction;

[0250] The second driving module includes a first second row driving buffer LD12, a second second row driving buffer LD22 and a third second row driving buffer LD32; LD12, LD22 and LD32 are arranged in a vertical direction;

[0251] The third driving module includes a first third row driving buffer LD13, a second third row driving buffer LD23 and a third third row driving buffer LD33; LD13, LD23 and LD33 are arranged in a vertical direction;

[0252] K11, K21, and K31 are all directly electrically connected to G_A1;

[0253] K12, K22, and K32 are all directly electrically connected to G_A2;

[0254] K13, K23 and K33 are all directly electrically connected to G_A3.

[0255] exist Fig.13 Among them, the one labeled EN_A is the positive phase test control line, and the one labeled EN_A' is the negative phase test control line.

[0256] exist Fig.13 In at least one embodiment shown, the first test signal line is directly electrically connected to the first ends of the multiple switch sub-circuits included in the first test control switch circuit; the second test signal line is directly electrically connected to the first ends of the multiple switch sub-circuits included in the second test control switch circuit; the third test signal line is directly electrically connected to the first ends of the multiple switch sub-circuits included in the third test control switch circuit; each switch sub-circuit directly obtains the test signal from the corresponding test signal line. If a row of switch sub-circuits fails, it will not affect the AOI inspection of other rows, and will not hinder the level transmission of the AOI test signal. The above arrangement avoids the problem of being completely unable to perform AOI testing due to component failure.

[0257] In at least one embodiment of the present invention, the driving module includes a multi-stage driving circuit and at least one stage of dummy driving circuit; the dummy driving circuit includes at least one dummy row driving buffer; the display panel includes at least one row of dummy pixel circuits;

[0258] The dummy row driving buffer in the last stage dummy driving circuit included in the driving module is electrically connected to the corresponding test signal line and the last row dummy pixel circuit respectively.

[0259] In a specific implementation, the driving module may include N levels of driving circuits and at least one level of dummy driving circuit; N is an integer greater than 1;

[0260] The at least one pseudo driving circuit can be cascaded with the Nmth driving circuit included in the driving module, that is, the at least one pseudo driving circuit can be arranged at the rear stage of the Nth driving circuit, and the pseudo row driving buffer in the last pseudo driving circuit included in the driving module can be directly electrically connected to the corresponding test signal line and the last row of pseudo pixel circuits, so that when normal display is performed, on the premise that each transmission gate included in the test control switch circuit is turned off, the corresponding electrical test signal can be directly provided to the last row of pseudo pixel circuits through the corresponding test signal line to enable electrical detection.

[0261] Fig.14 This is the layout diagram of the drive module part;

[0262] like Fig.14 As shown, at least one embodiment of the driving module includes a 3073rd first row driving buffer LD30731, a 3073rd second row driving buffer LD30732, a 3073rd third row driving buffer LD30733, a 3074th first row driving buffer LD30741, a 3074th second row driving buffer LD30742, a 3074th third row driving buffer LD30743, a first pseudo first row driving buffer LDD11, a first pseudo second row driving buffer LDD12, a first pseudo third row driving buffer LDD13, a second pseudo first row driving buffer LDD21, a second pseudo second row driving buffer LDD22, and a second pseudo third row driving buffer LDD23;

[0263] LD30731 is used to provide a first scanning signal for the 3073rd row of pixel circuits included in the display panel, LD30732 is used to provide a second scanning signal for the 3073rd row of pixel circuits included in the display panel, and LD30733 is used to provide a third scanning signal for the 3073rd row of pixel circuits included in the display panel;

[0264] LD30741 is used to provide a first scanning signal for the 3074th row of pixel circuits included in the display panel, LD30742 is used to provide a second scanning signal for the 3074th row of pixel circuits included in the display panel, and LD30743 is used to provide a third scanning signal for the 3074th row of pixel circuits included in the display panel;

[0265] LDD11 is electrically connected to the first row of Dummy pixel circuits included in the display panel, LDD12 is electrically connected to the first row of Dummy pixel circuits included in the display panel, and LDD13 is electrically connected to the first row of Dummy pixel circuits included in the display panel;

[0266] LDD21 is electrically connected to the second row of Dummy pixel circuits included in the display panel, LDD22 is electrically connected to the second row of Dummy pixel circuits included in the display panel, and LDD23 is electrically connected to the second row of Dummy pixel circuits included in the display panel.

[0267] like Fig.14 As shown, at least one embodiment of the driving module further includes a 3703rd first transmission gate TG37031, a 3703rd second transmission gate TG37032, a 3703rd third transmission gate TG37033, a 3704th first transmission gate TG37041, a 3704th second transmission gate TG37042, a 3704th third transmission gate TG37043, a first dummy first transmission gate TGD11, a first dummy second transmission gate TGD12 and a first dummy third transmission TGD13;

[0268] TG37031 is directly connected to the first test signal line ( Fig.14 TG30732 is electrically connected to the second test signal line (not shown) through the second wire L2. Fig.14 TG37033 is electrically connected to the third test signal line (not shown) through the third wire L3. Fig.14 ) electrical connections.

[0269] exist Fig.14 In at least one embodiment shown, TG37031 is directly electrically connected to the first test signal line through corresponding wires, TG30732 is directly electrically connected to the second test signal line through corresponding wires, TG37033 is directly electrically connected to the third test signal line through corresponding wires, TG37041 is directly electrically connected to the first test signal line through corresponding wires, TG30742 is directly electrically connected to the second test signal line through corresponding wires, TG37043 is directly electrically connected to the third test signal line through corresponding wires, TGD11 is directly electrically connected to the first test signal line through corresponding wires, TGD12 is directly electrically connected to the second test signal line through corresponding wires, and TGD13 is directly electrically connected to the third test signal line through corresponding wires. Each transmission gate directly obtains the corresponding test signal from the corresponding test signal line. If a transmission gate fails, it will not affect the AOI inspection of other rows, and will not hinder the level transmission of the AOI test signal. The above setting avoids the problem of being completely unable to perform AOI testing due to component failure.

[0270] exist Fig.14 In at least one embodiment shown, the 3073rd first row driver buffer LD30731, the 3073rd second row driver buffer LD30732, and the 3073rd third row driver buffer LD30733 are sequentially arranged in a direction away from the display area;

[0271] The 3074th first row driver buffer LD30741, the 3074th second row driver buffer LD30742, and the 3074th third row driver buffer LD30743 are sequentially arranged in a direction away from the display area;

[0272] The first dummy first row driver buffer LDD11, the first dummy second row driver buffer LDD12 and the first dummy third row driver buffer LDD13 are sequentially arranged in a direction away from the display area;

[0273] The second dummy first row driver buffer LDD21 , the second dummy second row driver buffer LDD22 , and the second dummy third row driver buffer LDD23 are sequentially arranged in a direction away from the display area.

[0274] In a specific implementation, since the sensitivity of the first scanning signal is greater than that of the second scanning signal, and the sensitivity of the second scanning signal is greater than that of the third scanning signal, the first row driver buffer, the second row driver buffer and the third row driver buffer can be arranged in sequence along a direction away from the display area; that is, the distance between the first row driver buffer and the display area is set to be closer to avoid the problem of signal distortion of the first scanning signal due to the long connection between the first scanning signal and the display area.

[0275] Fig.15 is Fig.14 On the basis of the layout diagram, a first test signal line G_A1, a second test signal line G_A2, a third test signal line G_A3, a positive phase test control line EN_A and a negative phase test control line EN_A' are additionally provided.

[0276] like Fig.15 As shown, the first test signal line G_A1, the second test signal line G_A2, the third test signal line G_A3, the positive phase test control line EN_A and the negative phase test control line EN_A′ may be sequentially arranged in a direction close to the display area.

[0277] exist Fig.15In at least one embodiment shown, G_A1, G_A2, G_A3, EN_A and EN_A' can be located on the same layer, G_A1, G_A2, G_A3, EN_A and EN_A' can be located on the side of the driving module away from the substrate, and G_A1, G_A2, G_A3, EN_A, EN_A' and the driving module can all be arranged on the substrate.

[0278] exist Fig.14 , Fig.15 In at least one embodiment shown, at the rear end of the row driver buffer corresponding to the last row of pseudo pixel circuits, the corresponding first transmission gate, the corresponding second transmission gate and the corresponding third transmission gate may not be provided, the second pseudo first row driver buffer LDD21 may be electrically connected to the first test signal line and the first scanning end of the last row of pseudo pixel circuits, respectively, the second pseudo second row driver buffer LDD221 may be electrically connected to the second test signal line and the second scanning end of the last row of pseudo pixel circuits, respectively, and the second pseudo third row driver buffer LDD23 may be electrically connected to the third test signal line and the third scanning end of the last row of pseudo pixel circuits, respectively, so that when normal display is performed, on the premise that the transmission gates included in the test control switch circuit are turned off, the corresponding electrical test signal can be directly provided to the last row of pseudo pixel circuits through the first test signal line, the second test signal line and the third test signal line, so as to enable electrical detection.

[0279] The driving method described in the embodiment of the present invention is applied to the above-mentioned row driving buffer, and the driving method includes:

[0280] When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit;

[0281] When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the driving output terminal.

[0282] The control method described in the embodiment of the present invention is applied to the above-mentioned display panel, and the control method includes:

[0283] When the display panel is in the optical detection stage, the enable control terminal provides an invalid enable control signal, controls the switch logic circuit to control the buffer circuit to stop providing the input signal to the drive output terminal, and the switch subcircuit controls the connection between the test signal line and the corresponding drive output terminal under the control of the test control signal;

[0284] When the display panel is in the display stage, the enable control terminal provides a valid enable control signal, and the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit. Under the control of the test control signal, the switch sub-circuit controls the disconnection between the test signal line and the corresponding drive output terminal.

[0285] The display device described in the embodiment of the present invention includes the above-mentioned display panel.

[0286] Optionally, the display device may be a silicon-based OLED microdisplay.

[0287] Silicon-based OLED (organic light-emitting diode) microdisplay is an active organic light-emitting diode display device that combines CMOS (Complementary Metal Oxide Semiconductor) technology and OLED technology, using single-crystal silicon as the active driving backplane. Silicon-based OLED microdisplay has the advantages of ultra-high resolution, high PPI (Pixels Per Inch), high contrast, high brightness, low power consumption, small size, and light weight. Therefore, it is widely used in AR (augmented reality), VR (virtual reality), MR (mixed reality), EVF (electronic viewfinder), FPV (First Person View, a wireless camera return device installed on a remote-controlled aircraft model or vehicle model), drones, thermal imagers, night vision devices, infrared cameras, medical equipment, etc.

[0288] In at least one embodiment of the present invention, the silicon-based OLED micro display may be composed of two ICs, one is a Si-BP (driving backplane) and the other is a DDIC (display driver integrated circuit). Among them, the Si-BP is mainly composed of modules such as a pixel circuit array, a driving module and a Source Driver.

[0289] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A row driver buffer, characterized in that: It includes a control switch logic circuit and a buffer circuit; the output end of the buffer circuit is electrically connected to the drive output end; The control switch logic circuit is electrically connected to the enable control terminal, the input signal terminal and the control terminal of the buffer circuit respectively, and is used for providing the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit when the enable control terminal provides a valid enable control signal, and controlling the buffer circuit to stop providing the input signal to the drive output terminal when the enable control terminal provides an invalid enable control signal.

2. The row driver buffer according to claim 1, wherein: The control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate and a control inverter; the buffer circuit includes a first control terminal and a second control terminal; The first input terminal of the first NAND gate is electrically connected to the enable control terminal, the second input terminal of the first NAND gate is electrically connected to the input signal terminal, and the output terminal of the first NAND gate is electrically connected to the input terminal of the control transmission gate; The first input terminal of the second NAND gate is electrically connected to the enable control terminal, the second input terminal of the second NAND gate is electrically connected to the inverting input signal terminal, and the output terminal of the second NAND gate is electrically connected to the input terminal of the control inverter; The output end of the control transmission gate is electrically connected to the first control end, and the output end of the control inverter is electrically connected to the second control end; The control transmission gate is used to provide the signal connected to its input terminal to the first control terminal; The control inverter is used for inverting the signal connected to its input terminal to obtain an inverted signal, and providing the inverted signal to the second control terminal.

3. The row driver buffer according to claim 2, wherein: The buffer comprises an inverter, the inverter comprising at least one first transistor and at least one second transistor; The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the driving output terminal; The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the driving output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

4. The row driver buffer according to claim 3, wherein: The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

5. A display panel, characterized in that: The invention comprises a driving module, wherein the driving module comprises N row driving buffers according to any one of claims 1 to 4; N is an integer greater than 1.

6. The display panel according to claim 5, characterized in that: comprising a plurality of rows of scanning lines; the nth row driving buffer comprising an nth driving output terminal; n is a positive integer less than or equal to N; The nth driving output terminal is electrically connected to the nth row of scanning lines.

7. The display panel according to claim 6, wherein: The driving module also includes a test control switch circuit; The test control switch circuit includes N switch sub-circuits; The control end of the nth switch subcircuit is electrically connected to the test control line, the first end of the nth switch subcircuit is electrically connected to the test signal line, the second end of the nth switch subcircuit is electrically connected to the nth drive output end, and the nth switch subcircuit is used to control the connection between the test signal line and the nth drive output end when the test control line provides a valid test control signal, and control the disconnection between the test signal line and the nth drive output end when the test control line provides an invalid test control signal.

8. The display panel according to claim 7, wherein: The nth switch subcircuit includes an nth transmission gate; the test control line includes a positive phase test control line and a negative phase test control line; The input end of the nth transmission gate is electrically connected to the test signal line, and the output end of the nth transmission gate is electrically connected to the nth driving output end; The positive phase control terminal of the nth transmission gate is electrically connected to the positive phase test control line, and the negative phase control terminal of the nth transmission gate is electrically connected to the negative phase test control line.

9. The display panel according to claim 7 or 8, characterized in that: The test signal line is directly electrically connected to the first ends of the N switch sub-circuits.

10. The display panel according to any one of claims 6 to 8, characterized in that: Also included are shift registers and level shifters; The shift register includes a multi-stage shift register unit, and the level converter includes a multi-stage level conversion unit; The n-th stage shift register unit is electrically connected to the n-th stage level conversion unit, and is used to provide the n-th stage driving signal to the n-th stage level conversion unit; The n-th level conversion unit is electrically connected to the n-th row driving buffer, and is used to perform level conversion on the n-th driving signal, and provide the level-converted n-th driving signal to the n-th row driving buffer.

11. The display panel according to any one of claims 5 to 8, characterized in that: It includes a multi-row and multi-column pixel circuit, wherein the driving module includes a first driving module, a second driving module and a third driving module; The first driving module is used to provide the pixel circuit with a first scanning signal for controlling the writing of data voltage; The second driving module is used to provide the pixel circuit with a second scanning signal for light emission control; The third driving module is used to provide the pixel circuit with a third scanning signal for initialization control; The first driving module includes a first row driving buffer, the second driving module includes a second row driving buffer, and the third driving module includes a third row driving buffer; the first row driving buffer includes a first buffer, the second row driving buffer includes a second buffer, and the third row driving buffer includes a third buffer; The first buffer includes A first transistors connected in parallel and A second transistors connected in parallel, the second buffer includes B first transistors connected in parallel and B second transistors connected in parallel, and the third buffer includes C first transistors connected in parallel and C second transistors connected in parallel; A is greater than B, A is greater than C; A, B and C are all positive integers.

12. The display panel according to claim 11, wherein: The first drive module comprises a first test control switch circuit, the second drive module comprises a second test control switch circuit, and the third drive module comprises a third test control switch circuit; The first driving module includes a plurality of first row driving buffers arranged in sequence along a first direction, and the first test signal line extends along the first direction; the first test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in the first test control switch circuit; The second driving module includes a plurality of second row driving buffers arranged in sequence along a first direction, and the second test signal line extends along the first direction; the second test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in the second test control switch circuit; The third driving module includes a plurality of third row driving buffers arranged in sequence along a first direction, and the third test signal line extends along the first direction; the third test signal line is directly electrically connected to first ends of a plurality of switch sub-circuits included in a third test control switch circuit.

13. The display panel according to claim 5, wherein: The driving module includes a multi-stage driving circuit and at least one stage of dummy driving circuit; the dummy driving circuit includes at least one dummy row driving buffer; the display panel includes at least one row of dummy pixel circuits; The dummy row driving buffer in the last stage dummy driving circuit included in the driving module is electrically connected to the corresponding test signal line and the last row dummy pixel circuit respectively.

14. A driving method, applied to the row driver buffer according to any one of claims 1 to 5, characterized in that: The driving method comprises: When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit; When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the driving output terminal.

15. A control method, applied to the display panel according to any one of claims 7 to 9, characterized in that: The control method comprises: When the display panel is in the optical detection stage, the enable control terminal provides an invalid enable control signal, controls the switch logic circuit to control the buffer circuit to stop providing the input signal to the drive output terminal, and the switch subcircuit controls the connection between the test signal line and the corresponding drive output terminal under the control of the test control signal; When the display panel is in the display stage, the enable control terminal provides a valid enable control signal, and the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit. Under the control of the test control signal, the switch sub-circuit controls the disconnection between the test signal line and the corresponding drive output terminal.

16. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 5 to 13.

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