A memory and its access method, an electronic device

Abstract

A memory and its access method, and an electronic device, are disclosed. The memory includes at least one memory array, multiple bit lines extending along a third direction perpendicular to a substrate, and multiple common bit lines extending along a second direction parallel to the substrate. The memory array includes multiple memory cells arrayed along the first and second directions parallel to the substrate, and multiple word lines extending along the first direction. Bit lines in the same column distributed along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each bit line is connected to the common bit line through a first gating sub-circuit. The first gating sub-circuit is also connected to a first gating control line, and the first gating sub-circuit is configured to connect or disconnect the bit lines and the common bit lines according to the control of the first gating control line. The solution provided in this embodiment, where multiple bit lines are connected to a single common bit line, can reduce the number of sense amplifiers used in the memory.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a memory and its access method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a memory including at least one memory array, multiple bit lines extending along a third direction perpendicular to a substrate, and multiple common bit lines extending along a second direction parallel to the substrate. The memory array includes multiple memory cells arrayed along the first and second directions parallel to the substrate and multiple word lines extending along the first direction. Bit lines in the same column distributed along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each bit line is connected to the common bit line through a first gating sub-circuit. The first gating sub-circuit is also connected to a first gating control line. The first gating sub-circuit is configured to connect or disconnect the bit lines and the common bit lines according to the control of the first gating control line.

[0006] In some embodiments, multiple first gating sub-circuits that are respectively connected to multiple bit lines distributed along a first direction are connected to the same first gating control line.

[0007] In some embodiments, the first gating sub-circuit includes a first transistor, the gate electrode of the first transistor is connected to the first gating control line, the first electrode is connected to the bit line, and the second electrode is connected to the common bit line.

[0008] In some embodiments, the memory further includes: a plurality of second gating sub-circuits respectively connected to a first end of each word line, the second gating sub-circuit being connected to a second gating control line and a word line driver, the second gating sub-circuit being configured to connect or disconnect the word line and the word line driver according to the control of the second gating control line; and a plurality of third gating sub-circuits respectively connected to a second end of each word line, the third gating sub-circuit being connected to a third gating control line and a voltage terminal, the third gating sub-circuit being configured to connect or disconnect the word line and the voltage terminal according to the control of the third gating control line, with word lines on the same layer connected to the same word line driver.

[0009] In some embodiments, the memory includes a plurality of memory arrays stacked along the third direction, the bit lines passing through the plurality of memory arrays, second gating sub-circuits connected to word lines of the same row in different layers connected to the same second gating control line, word lines of different rows connected to different second gating control lines, third gating sub-circuits connected to word lines of the same row in different layers connected to the same third gating control line, word lines of different rows connected to different third gating control lines, and word lines of different layers connected to different word line drivers.

[0010] In some embodiments, the second gating control line connected to the second gating sub-circuit connected to the word line of the i-th row is connected to the first gating control line connected to the first gating sub-circuit connected to the bit line of the i-th row, where i is from 1 to m, and m is the number of rows of word lines contained in each layer of the memory array.

[0011] In some embodiments, the second and third gating subcircuits connected to the same word line are configured to opposite states.

[0012] In some embodiments, the plurality of second gating subcircuits of the memory are configured such that the second gating subcircuit connected to the word line of the target row where the word line to be selected is located is configured to be in a connected state, and the second gating subcircuit connected to the word lines of other rows besides the target row is configured to be in a disconnected state.

[0013] In some embodiments, the second gating sub-circuit includes a second transistor, the gate electrode of the second transistor being connected to the second gating control line, the first electrode being connected to the first end of the word line, and the second electrode being connected to the word line driver.

[0014] In some embodiments, the third gating sub-circuit includes a third transistor, the gate electrode of which is connected to the third gating control line, the first electrode of which is connected to the second end of the word line, and the second electrode of which is connected to the voltage terminal.

[0015] In some embodiments, the common bit line is disposed on the side of the memory array facing the substrate or on the side away from the substrate.

[0016] This disclosure provides an electronic device including the memory described in any of the above embodiments.

[0017] This disclosure provides a memory access method, including:

[0018] During the data read / write phase, based on the target layer and target row of the memory cell to be operated on, an enable level signal is applied to the second strobe control line connected to the word line of the target row, and an disable level signal is applied to the second strobe control line connected to the word line of a cell not in the target row; an disable level signal is applied to the third strobe control line connected to the word line of the target row, and an enable level signal is applied to the third strobe control line connected to the word line of a cell not in the target row; an enable level signal is applied to the first strobe control line connected to the bit line of the target row, and an disable level signal is applied to the first strobe control line connected to the bit line of a cell not in the target row; an activation signal is applied to the word line driver of the target layer, and an inactivation signal is applied to the word line driver of the cell not in the target layer.

[0019] In some embodiments, it also includes:

[0020] During the pre-charge phase, an enable level signal is applied to all first strobe control lines, an enable level signal is applied to all second strobe control lines, an disable level signal is applied to all third strobe control lines, and an inactive signal is applied to all word line drivers.

[0021] In some embodiments, when the second gating control line connected to the second gating sub-circuit of the word line in the i-th row is connected to the first gating control line connected to the first gating sub-circuit of the bit line in the i-th row, where i is 1 to m, and m is the number of rows of word lines contained in each layer of the memory array:

[0022] During the data read / write phase, an enable level signal is applied to the first gating control line connected to the bit line of the target row, and an disable level signal is applied to the first gating control line connected to the bit line of a non-target row. Applying an enable level signal to the second gating control line connected to the word line of the target row and applying a disable level signal to the second gating control line connected to the word line of a non-target row includes: applying the same enable level signal to the first gating control line connected to the bit line of the target row and the second gating control line connected to the word line of the target row; applying the same disable level signal to the first gating control line connected to the bit line of a non-target row and the second gating control line connected to the word line of a non-target row.

[0023] This application includes a memory and its access method, and an electronic device. The memory includes at least one memory array, multiple bit lines extending along a third direction perpendicular to a substrate, and multiple common bit lines extending along a second direction parallel to the substrate. The memory array includes multiple memory cells arrayed along the first and second directions parallel to the substrate, and multiple word lines extending along the first direction. Bit lines in the same column distributed along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each bit line is connected to the common bit line through a first gating sub-circuit. The first gating sub-circuit is also connected to a first gating control line, and the first gating sub-circuit is configured to connect or disconnect the bit lines and the common bit lines according to the control of the first gating control line. The solution provided in this embodiment reduces the number of sense amplifiers used by the memory by connecting bit lines in the same column to the common bit line, thereby allowing the sense amplifier to be connected through the common bit line.

[0024] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0027] Figure 1A A three-dimensional schematic diagram of a memory provided for an exemplary embodiment;

[0028] Figure 1B for Figure 1A A schematic diagram showing the connection between the memory cell and the bit line and word line of the qth layer in the xy direction;

[0029] Figure 1C for Figure 1A A schematic diagram showing the connection between each layer of storage cells and bit lines and word lines in the q-th row along the xz direction;

[0030] Figure 1D for Figure 1A A schematic diagram showing the connection between each layer of storage cells and bit lines and word lines in the q-th column along the yz direction;

[0031] Figure 2 A schematic diagram of a memory provided for an exemplary embodiment. Detailed Implementation

[0032] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0034] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0036] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0037] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0038] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0039] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0040] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0041] Figure 1A A three-dimensional schematic diagram of a memory provided for an embodiment of this disclosure. Figure 1B for Figure 1A A schematic diagram showing the connection between the storage cell and the bit line and word line in the qth layer along the xy direction. Figure 1C for Figure 1A A schematic diagram showing the connection between each layer of storage cells and bit lines and word lines in the q-th row along the xz direction. Figure 1D for Figure 1A A schematic diagram showing the connections between the storage cells of each layer in the q-th column along the yz direction and the bit lines and word lines. (See diagram below.) Figures 1A to 1D As shown, the memory provided in this embodiment includes a multi-layer stacked memory array (k layers, memory arrays L1 to Lk), which are stacked along a third direction z. Each layer of the memory array includes a plurality of memory cells 100 distributed along a first direction x and a second direction y, and a plurality of word lines WL extending along the first direction x. The plurality of word lines WL in each layer are spaced apart along the second direction y. The memory also includes a plurality of bit lines BL extending along a third direction z, which are distributed along the first direction x and the second direction y. Each layer of the memory array includes m rows and n columns of memory cells 100, and includes m word lines WL, wherein the word line in the i-th row of the r-th layer is word line WL_i_r, where i is 1 to m and r is 1 to k. The memory includes m rows and n columns of bit lines BL, where the bit line in the j-th column of the i-th row is bit line BL_i_j, where j is 1 to n. Figures 1B to 1DThe following explanation uses a 1T1C structure for memory cell 100 as an example. That is, memory cell 100 is a structure in which an access transistor and a capacitor Cs are connected. The gate electrode of the access transistor is connected to the word line WL, the first electrode is connected to the bit line BL, the second electrode is connected to the first end of the capacitor Cs, the second end of the capacitor Cs is connected to the common voltage terminal Vcom, and the first end of the capacitor Cs serves as the memory node SN. The memory cell C_i_j_r in the i-th row and j-th column of the r-th layer is connected to the word line WL_i_r and the bit line BL_i_j. Figures 1B to 1D A 1T1C structure memory cell is shown, but this disclosure is not limited to this; the memory may include memory cells with other structures, such as 2T0C, 2T1C, etc. The first direction x and the second direction y are parallel to the substrate (…). Figures 1A to 1D (The substrate is not shown in the diagram), and the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular.

[0042] like Figure 1B As shown, in the q-th layer, the storage cell 100 in the i-th row is connected to the word line WL_i_q in the i-th row of the q-th layer; i is 1 to m. The storage cell 100 in the i-th row and j-th column is connected to the bit line BL_i_j in the i-th row and j-th column, where i is 1 to m and j is 1 to n. It can be seen that the word line WL extends along the first direction x, and the bit line BL extends along a third direction z, which is perpendicular to the first direction x and the second direction y.

[0043] like Figure 1C As shown, the storage cell 100 in the q-th row and r-th layer is connected to the word line WL_q_r in the q-th row and r-th layer, where r is from 1 to k. The storage cell 100 in the q-th row and j-th column of each layer is connected to the bit line BL_q_j in the q-th row and j-th column, where j is from 1 to n. It can be seen that the word line WL extends along the first direction x, and the bit line BL extends along the third direction z.

[0044] like Figure 1D As shown, the storage cell 100 in the q-th column, r-th layer, and i-th row is connected to the word line WL_i_r in the i-th row and r-th layer, where r is 1 to k and i is 1 to m; the storage cell 100 in the i-th row and q-th column of each layer is connected to the bit line BL_i_q in the i-th row and q-th column, where i is 1 to m. It can be seen that the word line WL extends along the first direction x, which is perpendicular to the second direction y and the third direction z, while the bit line BL extends along the third direction z.

[0045] Figure 2 A schematic diagram of a memory provided for an exemplary embodiment. Figure 2 In the diagram, memory cell 100 is not shown; only word line WL and bit line BL are shown. The connection relationship between word line WL and bit line BL and memory cell 100 can be found in [reference needed]. Figures 1A to 1DThis will not be elaborated further. For example... Figure 2 As shown, the memory also includes multiple common bit lines (CBLs). Bit lines BL in the same column distributed along the second direction y can be connected to the same common bit line CBL. Bit lines BL in different columns are connected to different common bit lines CBLs. For example, the first column of bit lines BL is connected to the first common bit line CBL1, the second column of bit lines BL is connected to the second common bit line CBL2, and the nth column of bit lines BL is connected to the nth common bit line CBLn. Each common bit line CBL is connected to a sense amplifier SA. Compared to a scheme where each bit line BL is connected to a sense amplifier SA, the solution provided in this embodiment can significantly reduce the number of sense amplifier SAs by using common bit lines CBLs. Adjacent memory arrays can share the same SA.

[0046] In some embodiments, the common bit line (CBL) may be disposed on the side of the memory array facing the substrate or on the side away from the substrate. When the memory comprises multiple stacked memory arrays, the common bit line (CBL) may be disposed on the side of the stacked memory arrays facing the substrate or on the side away from the substrate.

[0047] In some embodiments, each bit line BL can be connected to the common bit line CBL via a first gating sub-circuit 10. The first gating sub-circuit 10 is also connected to a first gating control line, which is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the first gating control line. That is, under the control of the first gating control line, the signal of the common bit line CBL is either loaded or not loaded onto the bit line BL.

[0048] In some embodiments, the first gating sub-circuits 10 connected to the same row bit lines BL distributed along the first direction x are connected to the same first gating control line, and the first gating sub-circuits of bit lines BL in different rows are connected to different first gating control lines. For example, the first gating sub-circuits 10 connected to the bit lines BL in the first row are all connected to the first first gating control line R_1, the first gating sub-circuits 10 connected to the bit lines BL in the second row are all connected to the second first gating control line R_2, and so on, with the first gating sub-circuits 10 connected to the bit lines BL in the m-th row being connected to the m-th first gating control line R_m. Thus, a bit line BL can be selected through the common bit line CBL and the first gating control line. For example, if the j-th common bit line CBL is loaded with an activation signal (the other common bit lines are loaded with non-activation signals), and the ith first gating control line R_i selects the corresponding first gating sub-circuit 10 (the other first gating control lines do not select the corresponding first gating sub-circuit 10), then the bit line BL_i_j in the ith row and j-th column is loaded with an activation signal.

[0049] In some embodiments, selecting only one bit line BL at a time can reduce the capacitive load of SA and the capacitance of the memory cell.

[0050] In some embodiments, the first gating sub-circuit 10 may include a first transistor T1, the gate electrode of the first transistor T1 being connected to the first gating control line, the first electrode being connected to the bit line BL, and the second electrode being connected to the common bit line CBL. The structure of the first gating sub-circuit 10 described in this embodiment is merely an example, and other circuits capable of gating may also be used.

[0051] In some embodiments, the first transistor T1 may be an N-type transistor, but this disclosure is not limited thereto; the first transistor T1 may be a P-type transistor.

[0052] In some embodiments, the word lines WL can be connected to word line drivers, with each layer's word lines WL connected to the same word line driver, and different layers' word lines WL connected to different word line drivers. The word line drivers can correspond one-to-one with the layers of the memory array. For example, the word line WL of layer 1 is connected to word line driver SWD_1, and the word line WL of layer k is connected to word line driver SWD_k. The word line driver can be connected to the first end of the word line WL.

[0053] Only one word line WL can be selected at a time; therefore, a gating subcircuit can be configured to select word line WL. In some embodiments, the first end of word line WL can be connected to the word line driver via a second gating subcircuit 20. The second gating subcircuit 20 is also connected to a second gating control line, and the second gating subcircuit 20 is configured to connect or disconnect the word line driver and the word line WL under the control of the second gating control line. That is, under the control of the second gating control line, the signal of the word line driver is applied or not applied to the word line WL.

[0054] In some embodiments, the second gating sub-circuits 20 connected to word lines WL in the same row of different layers can be connected to the same second gating control line, while the second gating sub-circuits 20 connected to word lines WL in different rows can be connected to different second gating control lines. For example, the second gating sub-circuits 20 connected to word lines WL in the first row of different layers are connected to second gating control line S_1, the second gating sub-circuits 20 connected to word lines WL in the second row of different layers are connected to second gating control line S_2, the second gating sub-circuits 20 connected to word lines WL in the third row of different layers are connected to second gating control line S_3, and so on, with the second gating sub-circuit 20 connected to word lines WL in the m-th row of different layers connected to second gating control line S_m. The number of second gating control lines is consistent with the number of rows of word lines WL contained in a layer of memory array. For example, if each layer of memory array includes m rows of word lines (one word line WL is one row), then there are m second gating control lines.

[0055] In some embodiments, a word line WL can be selected by a word line driver and a second strobe control line. For example, if the word line driver SWD_r corresponding to the r-th layer of the memory array is loaded with an activation signal (the other word line drivers are loaded with inactive signals), and the i-th second strobe control line S_i selects the corresponding second strobe sub-circuit 20 (the other second strobe control lines do not select the corresponding second strobe sub-circuit 20), then the word line WL_i_r in the r-th layer and i-th row is loaded with an activation signal. That is, at any given time, only one word line driver among word line drivers SWD_1 to SWD_k provides an activation signal to a layer of word lines WL, and only one second strobe sub-circuit 20 connected to that word line WL is turned on, connecting the word line WL and the word line driver that provides the activation signal, thereby ensuring that only one word line WL is selected at any given time.

[0056] In some embodiments, the second gating sub-circuit 20 may include a second transistor T2, the gate electrode of which is connected to the second gating control line, a first electrode connected to the first end of the word line WL, and a second electrode connected to the word line driver. The structure of the second gating sub-circuit 20 described in this embodiment is merely an example and may be other circuits capable of gating.

[0057] In some embodiments, the second transistor T2 is, for example, an N-type transistor, but this disclosure is not limited thereto; the second transistor T2 may be a P-type transistor.

[0058] In some embodiments, the second end of the word line WL can be connected to a preset voltage terminal via a third gating sub-circuit 30. The preset voltage terminal can be a low-level signal terminal, such as a ground terminal. The third gating sub-circuit 30 is also connected to a third gating control line, and is configured to connect or disconnect the word line WL and the preset voltage terminal under the control of the third gating control line. The third gating sub-circuit 30 can prevent the word line WL from being in a floating state when the second gating sub-circuit 20 connected to it is disconnected.

[0059] In some embodiments, the third gating sub-circuits 30 connected to word lines WL in the same row of different layers are connected to the same third gating control line, while the third gating sub-circuits 30 connected to word lines WL in different rows are connected to different third gating control lines. For example, the third gating sub-circuits 30 connected to the word lines WL in the first row of different layers are connected to the third gating control line S_1b, the third gating sub-circuits 30 connected to the word lines WL in the second row of different layers are connected to the third gating control line S_2b, the third gating sub-circuits 30 connected to the word lines WL in the third row of different layers are connected to the third gating control line S_3b, and so on, until the third gating sub-circuit 30 connected to the word lines WL in the m-th row of different layers is connected to the third gating control line S_mb. The number of third gating control lines is consistent with the number of rows of word lines WL contained in a layer of memory array. For example, if each layer of memory array includes m rows of word lines (one word line WL is one row), then there are m third gating control lines.

[0060] In some embodiments, the third gating sub-circuit 30 may include a third transistor T3, the gate electrode of which is connected to the third gating control line, the first electrode of which is connected to the second terminal of the word line WL, and the second electrode of which is connected to the preset voltage terminal. The structure of the third gating sub-circuit 30 described in this embodiment is merely an example and may be other circuits capable of gating.

[0061] In some embodiments, the third transistor T3 is, for example, an N-type transistor, but this disclosure is not limited thereto; the third transistor T3 may be a P-type transistor.

[0062] In some embodiments, the states of the second gating sub-circuit 20 and the third gating sub-circuit 30 connected to the same word line WL are opposite; that is, when the second gating sub-circuit 20 is in the connected state, the third gating sub-circuit 30 is in the disconnected state; and when the second gating sub-circuit 20 is in the disconnected state, the third gating sub-circuit 30 is in the connected state. Correspondingly, when the second transistor T2 and the third transistor T3 are transistors of the same type (for example, both the second transistor T2 and the third transistor T3 are N-type MOS transistors, or both are P-type MOS transistors), the signal polarities of the second gating control line connected to the second gating sub-circuit 20 connected to the word line WL in the same row and the third gating control line connected to the third gating sub-circuit 30 connected to the word line in the same row are opposite. For example, when the second gating control line S_2 connected to the second row word line WL is at a high level, the third gating control signal line S_2b connected to the second row word line WL is at a low level. When the second transistor T2 and the third transistor T3 are transistors with opposite polarities (for example, one of the second transistor T2 and the third transistor T3 is an N-type MOS transistor and the other is a P-type MOS transistor), the second gating control line connected to the second gating sub-circuit 20 connected to the word line WL in the same row, and the third gating control line connected to the third gating sub-circuit 30 connected to the word line in the same row, have the same signal polarity. For example, when the second gating control line S_2 connected to the second word line WL in the second row is at a high level, the third gating control signal line S_2b connected to the second word line WL in the second row is at a high level, thereby realizing that the states of the second gating sub-circuit 20 and the third gating sub-circuit 30 connected to the same word line WL are opposite.

[0063] In some embodiments, the plurality of second gating sub-circuits 20 of the memory are configured such that: the second gating sub-circuit 20 connected to the word line in the i-th row where the word line WL to be selected is located (here referring to the second gating sub-circuit 20 connected to the word line in the i-th row of each layer) is configured to be in a connected state, and the second gating sub-circuit 20 connected to the word lines WL in other rows besides the i-th row is configured to be in a disconnected state, where i is 1 to m, and m is the number of rows of word lines WL contained in each layer of the memory array. The word line driver connected to the layer where the word line in the i-th row to be selected is located is loaded with an activation signal, and other layers are loaded with an inactive signal, thereby selecting only one layer of the multiple layers of word lines in the i-th row. Combining the previous point, if the states of the second gating sub-circuit 20 and the third gating sub-circuit 30 connected to the same word line WL are reversed, then the third gating sub-circuit 30 connected to the word lines WL of other rows except the i-th row is configured to be in a connected state. That is, the word lines WL of other rows except the i-th row are connected to the preset voltage terminal and will not be in a floating state. Among the word lines WL of the i-th row in different layers, the word lines are connected to the word line driver. The word line driver can load an activation signal or an inactivation signal, that is, the word lines WL of the i-th row will not be floating.

[0064] The storage unit 100 can be a 1T1C structure, or a 2T0C structure, or a 2T1C structure, etc. When the storage unit is a 1T1C structure, one storage unit 100 can be connected to one bit line BL and one word line WL. When the storage unit 100 is a 2T0C structure, one storage unit 100 can be connected to one bit line BL, one read word line RWL and one write word line WWL; or, one storage unit 100 can be connected to one read bit line RBL, one write bit line WBL, one read word line RWL and one write word line WWL.

[0065] In some embodiments, the bit lines BL of the memory array may include read bit lines RBL and write bit lines WBL, and the word lines WL of the memory array may include read word lines RWL and write word lines WWL. In this case, the read bit lines RBL and RWL can respectively serve as... Figure 2 The bit line BL and word line WL are configured with corresponding common bit line CBL, first gating sub-circuit 10, second gating sub-circuit 20 and third gating sub-circuit 30, as well as corresponding first gating control line, second gating control line and third gating control line; the write bit line WBL and write word line WWL can be respectively used as Figure 2 The bit line BL and word line WL are configured with another set of corresponding common bit lines CBL, first gating sub-circuit 10, second gating sub-circuit 20 and third gating sub-circuit 30, as well as corresponding first gating control lines, second gating control lines and third gating control lines.

[0066] In some embodiments, the memory array may include a read word line (RWL), a write word line (WWL), and a bit line (BL) (the read bit line RBL and the write bit line WBL are combined). In this embodiment, corresponding second gating sub-circuit 20 and third gating sub-circuit 30 may be provided for the read word line RWL and the write word line WWL, respectively, as well as corresponding second gating control lines and third gating control lines. A common bit line, a first gating sub-circuit 10, and a first gating control line may be provided for the bit line BL. Similarly... Figure 2 In the structure, the word lines WL at this time include read word lines RWL and write word lines WWL. Each layer of read word lines RWL is connected to a read word line driver, and read word lines RWL of different layers are connected to different read word line drivers. Each layer of write word lines WWL is connected to a write word line driver, and write word lines WWL of different layers are connected to different write word line drivers.

[0067] In some embodiments, when the memory cell 100 is a 1T1C structure, the second gating control line S_i connected to the second gating sub-circuit 20 connected to the word line WL of the i-th row can be connected to the first gating control line R_i connected to the first gating sub-circuit 10 connected to the bit line BL of the i-th row, where i is 1 to m. The plurality of memory cells 100 connected to the word line WL of the i-th row are respectively connected to the plurality of bit lines BL of the i-th row. That is, a single gating control line can be used to connect the gate electrode of the second gating sub-circuit 20 connected to the word line WL of the i-th row and the gate electrode of the first gating sub-circuit 10 connected to the bit line BL of the i-th row. A single gating control line controls the second gating sub-circuit 20 connected to the word line WL of the i-th row and the first gating sub-circuit 10 connected to the bit line BL of the i-th row. The solution provided in this embodiment can reduce the number of control lines, reduce the control circuitry that generates control signals, and reduce the device footprint. However, this embodiment is not limited to this; the second strobe control line S_i and the first strobe control line R_i can be set independently. When the storage cell 100 is a 2T0C structure and the read bit line RBL and the write bit line WBL are combined, the second strobe control line S_i and the first strobe control line R_i are set independently and are not connected.

[0068] This disclosure provides a memory access control method, including:

[0069] During the data read / write phase, based on the target layer and target row of the storage unit to be operated on, an on-level signal is applied to the second gating control line connected to the word line of the target row (so that the second gating sub-circuit connecting word lines of target rows of different layers is in a connected state), and an off-level signal is applied to the second gating control line connected to the word line of a non-target row (so that the second gating sub-circuit connecting word lines of a non-target row of different layers is in a turned-off state); an off-level signal is applied to the third gating control line connected to the word line of the target row (so that the third gating sub-circuit connecting word lines of target rows of different layers is in a turned-off state), and an on-level signal is applied to the third gating control line connected to the word line of a non-target row (so that the second gating sub-circuit connecting word lines of a non-target row of different layers is in a connected state). The third gating sub-circuit of the word line of the non-target row in the same layer is in the connected state; an on level signal is applied to the first gating control line connected to the bit line of the target row (so that the first gating sub-circuit of the bit line connected to the target row is in the connected state), and an off level signal is applied to the first gating control line connected to the bit line of the non-target row (so that the first gating sub-circuit of the bit line connected to the non-target row is in the off state); an activation signal is applied to the word line driver of the target layer, and an inactive signal is applied to the word line driver of the non-target layer (combined with the second gating sub-circuit of the target row being in the connected state, at this time, only the word line of the target row of the target layer is activated, so that the access transistor of the memory cell of the target row of the target layer can be turned on).

[0070] This embodiment provides a memory access method that uses fewer control signals to control bit lines, thus reducing the number of control lines.

[0071] An on signal is a signal that enables the corresponding gating sub-circuit to be in the connected state, while an off signal is a signal that enables the corresponding gating sub-circuit to be in the off state.

[0072] In some embodiments, it also includes:

[0073] During the precharge phase, an enable level signal is applied to all first gating control lines (so that all first gating sub-circuits are in the connected state), an enable level signal is applied to all second gating control lines (so that all second gating sub-circuits are in the connected state), an disable level signal is applied to all third gating control lines (so that all third gating sub-circuits are in the disabled state), and an inactive signal is applied to all word line drivers (so that all memory cell access transistors are turned off).

[0074] In some embodiments, when the second gating control line connected to the second gating sub-circuit of the word line in the i-th row is connected to the first gating control line connected to the first gating sub-circuit of the bit line in the i-th row, where i is 1 to m, and m is the number of rows of word lines contained in each layer of the memory array:

[0075] During the data read / write phase, an enable level signal is applied to the first gating control line connected to the bit line of the target row, and an disable level signal is applied to the first gating control line connected to the bit line of a non-target row. Applying an enable level signal to the second gating control line connected to the word line of the target row and a disable level signal to the second gating control line connected to the word line of a non-target row includes: applying the same enable level signal to both the first gating control line connected to the bit line of the target row and the second gating control line connected to the word line of the target row; and applying the same disable level signal to both the first gating control line connected to the bit line of a non-target row and the second gating control line connected to the word line of a non-target row. That is, the same signal can control the first and second gating control lines connected to the bit lines and word lines of the same row, respectively, reducing the number of control signals and simplifying the control process.

[0076] The working process of the memory is illustrated below through an embodiment. Figure 2Taking the memory shown as an example, in this embodiment, the memory cell 100 has a 1T1C structure, the access transistor is an N-type MOS transistor, the first transistor T1, the second transistor T2, and the third transistor T3 are all N-type MOS transistors, and the second gating control line S_i is connected to the first gating control line R_i. The following description only uses the second gating control line S_i, meaning that the second gating control line S_i also controls the first gating sub-circuit 10. The common bit line CBL can also be connected to the precharge sub-circuit. The memory's operating stages can include a precharge stage, a data read stage, and a data write-back stage, wherein:

[0077] During the precharge phase, all second gating control lines S_i are loaded with a high-level signal, where i is 1 to m, to turn on all second transistors T2 and the first transistor T1. After the second transistor T2 is turned on, all word lines WL are connected to the corresponding word line drivers. Word line drivers SWD_1 to SWD_K are all loaded with a low-level signal, which is applied to the word line WL. All memory cell access transistors are turned off, the precharge sub-circuit is turned on, and a precharge voltage of 1 / 2VDD is applied to each common bit line CBL. Each common bit line CBL applies the precharge voltage to the connected column of bit lines BL. All third gating control lines S_ib are loaded with a low-level signal, causing all third transistors T3 to turn off.

[0078] During the data reading phase, the precharge electronic circuit is turned off. Taking the reading of data from memory cell 100 in the p-th layer and q-th row as an example, the second gating control line S_q remains at a high level, while the remaining second gating control lines S_i, where i is 1 to m and i ≠ q, are loaded with a low level signal. This turns off the second transistor T2 and the first transistor T1 connected to the second gating control lines S_i, where i is 1 to m and i ≠ q. In the word line drivers SWD_1 to SWD_K, SWD_p is loaded with a high level signal. The access transistor of the memory cell 100 connected to the word line WL of the p-th layer and q-th row is turned on, while the access transistors of the other memory cells 100 are turned off. The common bit lines CBL1 to CBLn are respectively connected to the n bit lines of the q-th row, and share charge with the memory nodes of the n memory cells 100 of the p-th layer and q-th row. The sensing amplifiers connected to CBL1 to CBLn sense the voltage of CBL1 to CBLn to determine the data stored in the memory cell 100 of the p-th layer and q-th row. The third gating control line S_qb is kept at a low level, while the other third gating control lines S_ib, i is 1 to m and i ≠ q, are loaded with a high level signal, thereby turning on the third transistor T3 connected to the third gating control line S_ib, i is 1 to m and i ≠ q. The word lines WL of the other rows except the q-th row are connected to the preset voltage terminal to prevent the word lines WL from floating.

[0079] During the data write-back phase, the second gating control line S_q remains at a high level, while the remaining second gating control lines S_i, where i is 1 to m and i ≠ q, are loaded with a low level signal. The third gating control line S_qb remains at a low level, while the remaining third gating control lines S_ib, where i is 1 to m and i ≠ q, are loaded with a high level signal. The common bit lines CBL1 to CBLn are connected to the n bit lines of the q-th row, respectively, and share charge with the storage nodes of the n storage cells 100 in the p-th layer and the q-th row, thereby realizing the data write-back.

[0080] The solution provided in this embodiment uses the same control signal to control bit lines and word lines in the same row, reducing the number of control signal lines, reducing the required control circuitry, and simplifying the control logic. This disclosure also provides an electronic device, including the memory of the foregoing embodiments. The electronic device can be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device can include memory in a computer, etc., and is not limited thereto.

[0081] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A memory, characterized in that, The device includes at least one memory array, multiple bit lines extending along a third direction perpendicular to the substrate, and multiple common bit lines extending along a second direction parallel to the substrate. The memory array includes multiple memory cells arrayed along the first and second directions parallel to the substrate and multiple word lines extending along the first direction. Bit lines in the same column distributed along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each bit line is connected to the common bit line through a first gating sub-circuit. The first gating sub-circuit is also connected to a first gating control line. The first gating sub-circuit is configured to: connect or disconnect the bit lines and the common bit lines according to the control of the first gating control line; and the multiple first gating sub-circuits respectively connected to the multiple bit lines distributed along the first direction are connected to the same first gating control line.

2. The memory according to claim 1, characterized in that, The memory further includes: a plurality of second gating sub-circuits respectively connected to a first end of each word line, the second gating sub-circuit being connected to a second gating control line and a word line driver, the second gating sub-circuit being configured to connect or disconnect the word line and the word line driver according to the control of the second gating control line; and a plurality of third gating sub-circuits respectively connected to a second end of each word line, the third gating sub-circuit being connected to a third gating control line and a voltage terminal, the third gating sub-circuit being configured to connect or disconnect the word line and the voltage terminal according to the control of the third gating control line, with word lines on the same layer connected to the same word line driver.

3. The memory according to claim 2, characterized in that, The memory includes multiple memory arrays stacked along the third direction, the bit lines passing through the multiple memory arrays, second gating sub-circuits connected to word lines of the same row in different layers are connected to the same second gating control line, word lines of different rows are connected to different second gating control lines, third gating sub-circuits connected to word lines of the same row in different layers are connected to the same third gating control line, word lines of different rows are connected to different third gating control lines, and word lines of different layers are connected to different word line drivers.

4. The memory according to claim 3, characterized in that, The second gating control line connected to the second gating sub-circuit of the word line in the i-th row is connected to the first gating control line connected to the first gating sub-circuit of the bit line in the i-th row, where i is from 1 to m, and m is the number of rows of word lines contained in each layer of the memory array.

5. The memory according to claim 3, characterized in that, The second and third gating sub-circuits, which are connected to the same word line, are configured to opposite states.

6. The memory according to claim 5, characterized in that, The memory's multiple second gating sub-circuits are configured such that the second gating sub-circuit connected to the word line of the target row containing the word line to be selected is configured to be in a connected state, and the second gating sub-circuit connected to the word lines of other rows besides the target row is configured to be in a disconnected state.

7. The memory according to claim 1, characterized in that, The first gating sub-circuit includes a first transistor, the gate electrode of the first transistor is connected to the first gating control line, the first electrode is connected to the bit line, and the second electrode is connected to the common bit line.

8. The memory according to claim 2, characterized in that, The second gating sub-circuit includes a second transistor, the gate electrode of the second transistor is connected to the second gating control line, the first electrode is connected to the first end of the word line, and the second electrode is connected to the word line driver.

9. The memory according to claim 2, characterized in that, The third gating sub-circuit includes a third transistor, the gate electrode of which is connected to the third gating control line, the first electrode of which is connected to the second end of the word line, and the second electrode of which is connected to the voltage terminal.

10. The memory according to any one of claims 1 to 9, characterized in that, The common bit line is located on the side of the memory array facing the substrate, or on the side away from the substrate.

11. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 10.

12. A method for accessing a memory as described in claim 3 or 4, characterized in that, include: During the data read / write phase, based on the target layer and target row of the storage unit to be operated, an enable level signal is loaded on the second strobe control line connected to the word line of the target row, and an disable level signal is loaded on the second strobe control line connected to the word line of a non-target row. A shutdown level signal is applied to the third gating control line connected to the word line of the target row, and an enable level signal is applied to the third gating control line connected to the word line of a non-target row. An enable level signal is applied to the first strobe control line connected to the bit line of the target row, and an disable level signal is applied to the first strobe control line connected to the bit line of a non-target row. An activation signal is applied to the word line driver of the target layer, and an inactivation signal is applied to the word line driver of the non-target layer.

13. The memory access method according to claim 12, characterized in that, Also includes: During the pre-charge phase, an enable level signal is applied to all first strobe control lines, an enable level signal is applied to all second strobe control lines, an disable level signal is applied to all third strobe control lines, and an inactive signal is applied to all word line drivers.

14. The memory access method according to claim 12, characterized in that, When the second gating control line connected to the second gating sub-circuit of the word line in the i-th row is connected to the first gating control line connected to the first gating sub-circuit of the bit line in the i-th row, where i is from 1 to m, and m is the number of rows of word lines contained in each layer of the memory array: During the data read / write phase, the steps of loading an enable level signal on a first gating control line connected to the bit line of the target row and loading an disable level signal on a first gating control line connected to a bit line other than the target row; loading an enable level signal on a second gating control line connected to the word line of the target row and loading an disable level signal on a second gating control line connected to a word line other than the target row include: loading the same enable level signal to the first gating control line connected to the bit line of the target row and the second gating control line connected to the word line of the target row; and loading the same disable level signal to the first gating control line connected to the bit line other than the target row and the second gating control line connected to the word line other than the target row.

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