Erasable programmable read-only memory and programming method

Abstract

The invention provides an erasable programmable read-only memory and a programming method. The erasable programmable read-only memory comprises a P-type well region and an N-type well region which are located in a substrate and arranged adjacently; the first gate oxide layer and the gate are located on the surface of the P-type well region; the second gate oxide layer and the floating gate are located on the surface of the N-type well region; the first N-type impurity region, the second N-type impurity region and the first P-type impurity region are located in the P-type well region and arranged at intervals, the first N-type impurity region and the second N-type impurity region are located on the two sides of the grid electrode, and the first N-type impurity region and the second N-type impurity region serve as the source end and the drain end of the NMOS respectively; the third N-type impurity region, the fourth N-type impurity region, the second P-type impurity region and the third P-type impurity region are located in the N-type well region and arranged at intervals, and the second P-type impurity region and the third P-type impurity region are located on the two sides of the floating gate and serve as the source end and the drain end of a PMOS respectively; wherein the second N-type impurity region is communicated with the second P-type impurity region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an erasable programmable read-only memory and a programming method. Background Art

[0002] Erasable programmable read-only memory (EPROM) is a computer memory chip that retains data (non-volatile) after power is removed. EPROM is usually a group of floating-gate transistors that are individually programmed by an electronic device that provides a higher voltage than the voltage normally used in the circuit.

[0003] The EPROM of the prior art is as follows Figure 1 , a floating gate 11 is needed to play the role of programming and storing charges. By applying a high bias voltage to the N-type substrate 12, electrons can tunnel through the oxide layer 13 to the floating gate 11 under certain conditions. After programming, the floating gate 11 will accumulate a large number of negatively charged electrons, which is equivalent to applying a negative voltage to the floating gate 11. At this time, the EPROM is in a conducting or semi-conducting state, that is, programming is completed. After programming is completed, it can only be erased by strong ultraviolet irradiation. When the device is irradiated with ultraviolet rays, the charge in its floating gate will be removed, thereby achieving the purpose of removing the stored data.

[0004] However, erasing with ultraviolet light is troublesome, and the EPROM is always in the open state before being erased with ultraviolet light, so the life of the EPROM is reduced. Summary of the invention

[0005] The object of the present invention is to provide an erasable programmable read-only memory and a programming method, which can easily control the opening and erasing of the EPROM, thereby improving the life of the EPROM.

[0006] In order to achieve the above object, the present invention provides an erasable programmable read-only memory, comprising:

[0007] substrate;

[0008] A P-type well region and an N-type well region located in the substrate and arranged adjacent to each other;

[0009] A first gate oxide layer and a gate are sequentially located on the surface of the P-type well region;

[0010] A second gate oxide layer and a floating gate are sequentially located on the surface of the N-type well region;

[0011] A first N-type impurity region, a second N-type impurity region and a first P-type impurity region are arranged at intervals in the P-type well region, the first N-type impurity region and the second N-type impurity region are located on both sides of the gate, the first N-type impurity region and the second N-type impurity region serve as a source terminal and a drain terminal of the NMOS respectively, and the second N-type impurity region and the first P-type impurity region are separated by a shallow trench isolation structure;

[0012] a third N-type impurity region, a fourth N-type impurity region, a second P-type impurity region and a third P-type impurity region arranged at intervals in the N-type well region, the second P-type impurity region and the third P-type impurity region being located on both sides of the floating gate, the second P-type impurity region and the third P-type impurity region serving as a source terminal and a drain terminal of the PMOS, respectively, the third N-type impurity region and the second P-type impurity region as well as the third N-type impurity region and the first P-type impurity region being separated by a shallow trench isolation structure, and the third P-type impurity region and the fourth N-type impurity region being separated by a shallow trench isolation structure;

[0013] a self-aligned silicide blocking film located on the surface of the floating gate;

[0014] Wherein, the second N-type impurity region is connected to the second P-type impurity region.

[0015] Optionally, the erasable programmable read-only memory further includes: CTs respectively located on the surfaces of the N-type well region, the first N-type impurity region, the gate, the second N-type impurity region, the first P-type impurity region, the third N-type impurity region, the second P-type impurity region, the third P-type impurity region and the fourth N-type impurity region.

[0016] Optionally, the erasable programmable read-only memory further includes a metal layer, and the metal layer is connected to the CT on the surface of the second N-type impurity region and the second P-type impurity region.

[0017] Optionally, in the erasable programmable read-only memory, the substrate includes a P-type substrate.

[0018] Optionally, in the erasable programmable read-only memory, materials of the first gate oxide layer and the second gate oxide layer both include silicon oxide.

[0019] Optionally, in the erasable programmable read-only memory, materials of the gate and the floating gate both include polysilicon.

[0020] Accordingly, the present invention also provides a programming method for an erasable programmable read-only memory, comprising:

[0021] Applying a negative voltage to the N-type well region, applying a high potential to the gate and the source end of the PMOS, and connecting the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS to a low potential to achieve programming;

[0022] Applying a voltage greater than the operating voltage and less than the breakdown voltage to the third N-type impurity region to achieve data writing;

[0023] An operating voltage is applied to the gate and the source terminal of the NMOS, and the source terminal of the PMOS is connected to 0 to achieve the storage state of 0 and 1.

[0024] Optionally, in the programming method of the erasable programmable read-only memory, a negative voltage is applied to the N-type well region through a CT located on the surface of the N-type well region, a high potential is applied to the gate and the source end of the PMOS through a CT located on the surface of the gate and the source end of the PMOS, and a low potential is connected to the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS through a CT located on the surface of the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS.

[0025] Optionally, in the programming method of the erasable programmable read-only memory, a voltage greater than an operating voltage and less than a breakdown voltage is applied to the third N-type impurity region through a CT located on a surface of the third N-type impurity region.

[0026] Optionally, in the programming method of the erasable programmable read-only memory, an operating voltage is applied to the gate and the source end of the NMOS through a CT located on the surface of the gate and the source end of the NMOS.

[0027] The erasable programmable read-only memory and programming method provided by the present invention include: a substrate; a P-type well region and an N-type well region located in the substrate and adjacent to each other; a first gate oxide layer and a gate located in sequence on the surface of the P-type well region; a second gate oxide layer and a floating gate located in sequence on the surface of the N-type well region; a first N-type impurity region, a second N-type impurity region and a first P-type impurity region located in the P-type well region and spaced apart from each other, the first N-type impurity region and the second N-type impurity region being located on both sides of the gate, the first N-type impurity region and the second N-type impurity region serving as a source end and a drain end of an NMOS respectively, and a shallow trench isolation structure being formed between the second N-type impurity region and the first P-type impurity region. Separation; the third N-type impurity region, the fourth N-type impurity region, the second P-type impurity region and the third P-type impurity region are arranged at intervals in the N-type well region, the second P-type impurity region and the third P-type impurity region are located on both sides of the floating gate, the second P-type impurity region and the third P-type impurity region are used as the source end and the drain end of the PMOS respectively, the third N-type impurity region and the second P-type impurity region and the third N-type impurity region and the first P-type impurity region are separated by a shallow trench isolation structure, and the third P-type impurity region and the fourth N-type impurity region are separated by a shallow trench isolation structure; a self-aligned silicide barrier film located on the surface of the floating gate; wherein the second N-type impurity region and the second P-type impurity region are connected. The present invention can control the opening and storage of the PMOS and the erasure of data by applying a high potential to the N-type well region, the gate, and the source end of the PMOS, and applying different potentials to the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS. Compared with the prior art method of erasing data only by ultraviolet irradiation, the present invention can easily control the opening and erasure of the EPROM, thereby improving the life of the EPROM. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of the prior art;

[0029] Figure 2 is a layout of an erasable programmable read-only memory according to an embodiment of the present invention;

[0030] Figure 3 Schematic diagram of the structure of an erasable programmable read-only memory according to an embodiment of the present invention;

[0031] Figure 4 is a flowchart of a programming method of an erasable programmable read-only memory according to an embodiment of the present invention;

[0032] In the figure: 11-floating gate, 12-N-type substrate, 13-oxide layer, 110-substrate, 120-shallow trench isolation structure, 130-P-type well region, 140-N-type well region, 150-first gate oxide layer, 160-gate, 170-second gate oxide layer, 180-floating gate, 190-first N-type impurity region, 200-second N-type impurity region, 210-first P-type impurity region, 220-third N-type impurity region, 230-second P-type impurity region, 240-third P-type impurity region, 250-fourth N-type impurity region, 260-self-aligned silicide blocking film. DETAILED DESCRIPTION

[0033] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0035] Please refer to Figure 2 and Figure 3The present invention provides an erasable programmable read-only memory, comprising: a substrate 110; a P-type well region 130 and an N-type well region 140 located in the substrate 110 and adjacent to each other; a first gate oxide layer 150 and a gate 160 located in sequence on the surface of the P-type well region 130; a second gate oxide layer 170 and a floating gate 180 located in sequence on the surface of the N-type well region 140; a first N-type impurity region 190, a second N-type impurity region 200 and a first P-type impurity region 210 located in the P-type well region 130 and spaced apart from each other, the first N-type impurity region 190 and the second N-type impurity region 200 being located on both sides of the gate 160, the first N-type impurity region 190 and the second N-type impurity region 200 serving as a source terminal and a drain terminal of an NMOS, respectively, the second N-type impurity region 200 and the first P-type impurity region 210 being separated by a shallow trench isolation structure 120 ; a third N-type impurity region 220, a fourth N-type impurity region 250, a second P-type impurity region 230 and a third P-type impurity region 240 arranged at intervals in the N-type well region 140, the second P-type impurity region 230 and the third P-type impurity region 240 are located on both sides of the floating gate 180, the second P-type impurity region 230 and the third P-type impurity region 240 serve as the source and drain of the PMOS respectively, the third N-type impurity region 220 and the second P-type impurity region 230 as well as the third N-type impurity region 220 and the first P-type impurity region 210 are separated by a shallow trench isolation structure 120, and the third P-type impurity region 240 and the fourth N-type impurity region 250 are separated by a shallow trench isolation structure 120; a self-aligned silicide blocking film 260 located on the surface of the floating gate 180; wherein the second N-type impurity region 200 and the second P-type impurity region 230 are connected.

[0036] Furthermore, the erasable programmable read-only memory of the present invention may further include: CTs respectively located on the surfaces of the N-type well region 140, the first N-type impurity region 190, the gate 160, the second N-type impurity region 200, the first P-type impurity region 210, the third N-type impurity region 220, the second P-type impurity region 230, the third P-type impurity region 240, and the fourth N-type impurity region 250. The erasable programmable read-only memory of the present invention may further include a metal layer, and the metal layer is connected to the CTs on the surfaces of the second N-type impurity region 200 and the second P-type impurity region 230.

[0037] In the embodiment of the present invention, the substrate 110 comprises a P-type substrate. The materials of the first gate oxide layer 150 and the second gate oxide layer 170 both comprise silicon oxide. The materials of the gate 160 and the floating gate 180 both comprise polysilicon.

[0038] The method for forming an erasable programmable read-only memory includes, first, providing a substrate 110, which may be a wafer, and implanting P-type ions into the substrate 110 to form a P-type substrate. Etching the substrate 110 to form a plurality of shallow trenches spaced apart, filling the shallow trenches with silicon dioxide to form a shallow trench isolation structure 120, and forming an active region. Implanting N-type ions and P-type ions into the substrate 110 respectively to form a P-type well region 130 and an N-type well region 140 located in the substrate and adjacently arranged. Next, an oxide layer and a polysilicon material layer are sequentially formed on the surface of the substrate 110, and the polysilicon material layer and the oxide layer are etched, and a first gate oxide layer 150 and a gate 160 are formed on the surface of the P-type well region 130, and a second gate oxide layer 170 and a floating gate 180 are formed on the surface of the N-type well region 140. Next, ions are implanted into the substrate 110 on both sides of the gate 160 to form a first N-type impurity region 190, a second N-type impurity region 200, and a first P-type impurity region 210 that are spaced apart in the P-type well region 130. The first N-type impurity region 190 and the second N-type impurity region 200 are located on both sides of the gate 160, and the second N-type impurity region 200 and the first P-type impurity region 210 are separated by a shallow trench isolation structure 120. The first N-type impurity region 190 serves as a source terminal of the NMOS, and the second N-type impurity region 200 serves as a drain terminal of the NMOS.

[0039] Next, ions are implanted into the substrate 110 on both sides of the floating gate 180 to form a third N-type impurity region 220, a second P-type impurity region 230, a third P-type impurity region 240 and a fourth N-type impurity region 250 which are arranged at intervals in the N-type well region 140. The second P-type impurity region 230 and the third P-type impurity region 240 are located on both sides of the floating gate 180. The third N-type impurity region 220 and the second P-type impurity region 230 are separated by a shallow trench isolation structure 120, the third N-type impurity region 220 and the first P-type impurity region 210 are separated by a shallow trench isolation structure 120, and the third P-type impurity region 240 and the fourth N-type impurity region 250 are separated by a shallow trench isolation structure 120. The second P-type impurity region 230 serves as a source terminal of the PMOS, and the third P-type impurity region 240 serves as a drain terminal of the PMOS.

[0040] Next, a self-aligned silicide blocking film 260 is formed on the surface of the floating gate 180. Next, CTs are formed on the surfaces of the N-type well region 140, the first N-type impurity region 190, the gate 160, the second N-type impurity region 200, the first P-type impurity region 210, the third N-type impurity region 220, the second P-type impurity region 230, the third P-type impurity region 240, and the fourth N-type impurity region 250. Next, a metal layer is formed, and the metal layer is connected to the CTs on the surfaces of the second N-type impurity region 200 and the second P-type impurity region 230, thereby connecting the second N-type impurity region 200 and the second P-type impurity region 230.

[0041] Please refer to Figure 3 The present invention also provides a programming method of an erasable programmable read-only memory, comprising:

[0042] S11: applying a negative voltage to the N-type well region, applying a high potential to the gate and the source end of the PMOS, and connecting the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS to a low potential to achieve programming;

[0043] S12: applying a voltage greater than the working voltage and less than the breakdown voltage to the third N-type impurity region to achieve data writing;

[0044] S13: Apply operating voltage to the gate and the source terminal of the NMOS, and connect the source terminal of the PMOS to 0 to achieve the storage state of 0 and 1.

[0045] In the embodiment of the present invention, a negative voltage is applied to the N-type well region through a CT located on the surface of the N-type well region, a high potential, such as 1.2V, 1.8 or 3.35V, is applied to the gate and the source end of the PMOS through a CT located on the surface of the gate and the source end of the PMOS, and a low potential, such as 0V, is connected to the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS through a CT located on the surface of the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS. A voltage greater than the working voltage and less than the breakdown voltage is applied to the third N-type impurity region through a CT located on the surface of the third N-type impurity region. An working voltage is applied to the gate and the source end of the NMOS through a CT located on the surface of the gate and the source end of the NMOS.

[0046] Specifically, the embodiment of the present invention is mainly composed of an NMOS and a floating gate PMOS. The source terminal and gate of the NMOS need to be connected separately, the drain terminal of the NMOS and the source terminal of the PMOS are connected in common, the drain terminal of the PMOS is connected separately, and the N-type well region and the P-type well region also need to be connected separately. In the unprogrammed state, the conduction from the source terminal of the PMOS to the source terminal of the NMOS cannot be achieved. During programming, a higher negative voltage needs to be applied to the N-type well region so that electrons tunnel to the floating gate (FG) and accumulate a certain amount of negative charge. After the programming is completed, the PMOS is in a conducting or semi-conducting state. At this time, when the gate and the source terminal of the PMOS are connected to a high potential, and the other ports are connected to a low potential, the source terminal of the PMOS is in a conducting state to the source terminal of the NMOS, and the potential of the source terminal of the port PMOS will be pulled to a low potential, and the programming is successful.

[0047] In the initial state, no gate voltage can be applied to the floating gate of PMOS to form an N-channel field effect, and the source end of PMOS to the drain end of PMOS is in an open circuit state. At this time, no matter how the voltage of the source gate of NMOS and the source end of PMOS is changed, the source end of NMOS to the source end of PMOS cannot be turned on, that is, it can be considered that there is no data stored on this cell.

[0048] When writing data, a higher voltage (greater than the normal working voltage and less than the breakdown voltage) is applied to the third N-type impurity region. At this time, a very high electric field strength will be generated under the floating gate. Under the influence of the high field strength, negatively charged electrons will have a certain probability of direct tunneling or FN tunneling through the second gate oxide layer to reach the floating gate and accumulate. When the accumulation reaches a certain level, it will react to the previously applied electric field, making it difficult for electrons to tunnel through the second gate oxide layer again, which is called a saturation state. At this time, it also represents the completion of data writing, and the high voltage of the third N-type impurity region is withdrawn to the initial state. At this time, a large number of electrons have accumulated on the floating gate.

[0049] When reading data, after the data is written, the floating gate is in an electron-rich state (negative charge), which will attract holes (positive charge) to gather under the second gate oxide layer, resulting in an effect similar to the field effect. A hole (positive charge) conductive path appears between the source end of the PMOS and the drain end of the PMOS, and the PMOS is in a conductive or semi-conductive state. At this time, a high voltage (operating voltage) is applied to the source end and gate of the NMOS. When the source end of the PMOS is connected to 0, it will be found that the source end of the NMOS to the source end of the PMOS can be normally conductive. Data is stored on this cell, and two states of 0 and 1 of the same cell are realized. Moreover, the reading of data at this time is controllable. Specifically, whether to read data can be controlled by whether to apply pressure to the gate, that is, controlling the switch of the NMOS. Compared with the prior art method that can only be erased by ultraviolet irradiation, the embodiment of the present invention increases the service life. And compared with the prior art, no additional mask is used, and no cost is increased.

[0050] In summary, the erasable programmable read-only memory and programming method provided by the embodiment of the present invention include: a substrate; a P-type well region and an N-type well region located in the substrate and adjacent to each other; a first gate oxide layer and a gate located on the surface of the P-type well region in sequence; a second gate oxide layer and a floating gate located on the surface of the N-type well region in sequence; a first N-type impurity region, a second N-type impurity region and a first P-type impurity region located in the P-type well region and spaced apart from each other, the first N-type impurity region and the second N-type impurity region being located on both sides of the gate, the first N-type impurity region and the second N-type impurity region serving as a source terminal and a drain terminal of the NMOS respectively, the second N-type impurity region and the first P-type impurity region being separated by a shallow trench a third N-type impurity region, a fourth N-type impurity region, a second P-type impurity region and a third P-type impurity region arranged at intervals in the N-type well region, the second P-type impurity region and the third P-type impurity region being located on both sides of the floating gate, the second P-type impurity region and the third P-type impurity region serving as a source terminal and a drain terminal of the PMOS respectively, the third N-type impurity region and the second P-type impurity region as well as the third N-type impurity region and the first P-type impurity region being separated by a shallow trench isolation structure, the third P-type impurity region and the fourth N-type impurity region being separated by a shallow trench isolation structure; a self-aligned silicide barrier film located on the surface of the floating gate; wherein the second N-type impurity region and the second P-type impurity region are connected. The present invention can control the opening and storage of PMOS and the erasure of data by applying a high potential to the N-type well region, the gate, and the source end of PMOS, and applying different potentials to the source end of NMOS, the first P-type impurity region, the third N-type impurity region, and the drain end of PMOS. Compared with the prior art method of erasing data only by ultraviolet irradiation, the present invention can easily control the opening and erasure of EPROM, thereby improving the life of EPROM.

[0051] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. An erasable programmable read-only memory, characterized in that: include: substrate; A P-type well region and an N-type well region located in the substrate and arranged adjacent to each other; A first gate oxide layer and a gate are sequentially located on the surface of the P-type well region; A second gate oxide layer and a floating gate are sequentially located on the surface of the N-type well region; A first N-type impurity region, a second N-type impurity region and a first P-type impurity region are arranged at intervals in the P-type well region, the first N-type impurity region and the second N-type impurity region are located on both sides of the gate, the first N-type impurity region and the second N-type impurity region serve as a source terminal and a drain terminal of the NMOS respectively, and the second N-type impurity region and the first P-type impurity region are separated by a shallow trench isolation structure; a third N-type impurity region, a fourth N-type impurity region, a second P-type impurity region and a third P-type impurity region arranged at intervals in the N-type well region, the second P-type impurity region and the third P-type impurity region being located on both sides of the floating gate, the second P-type impurity region and the third P-type impurity region serving as a source terminal and a drain terminal of the PMOS, respectively, the third N-type impurity region and the second P-type impurity region as well as the third N-type impurity region and the first P-type impurity region being separated by a shallow trench isolation structure, and the third P-type impurity region and the fourth N-type impurity region being separated by a shallow trench isolation structure; a self-aligned silicide blocking film located on the surface of the floating gate; Wherein, the second N-type impurity region is connected to the second P-type impurity region.

2. The erasable programmable read-only memory according to claim 1, wherein: Also includes: CTs are respectively located on the surfaces of the N-type well region, the first N-type impurity region, the gate, the second N-type impurity region, the first P-type impurity region, the third N-type impurity region, the second P-type impurity region, the third P-type impurity region and the fourth N-type impurity region.

3. The erasable programmable read-only memory according to claim 2, wherein: The metal layer is also included, and the metal layer is connected to the CT on the surface of the second N-type impurity region and the second P-type impurity region.

4. The erasable programmable read-only memory according to claim 1, wherein: The substrate includes a P-type substrate.

5. The erasable programmable read-only memory according to claim 1, wherein: The materials of the first gate oxide layer and the second gate oxide layer both include silicon oxide.

6. The erasable programmable read-only memory according to claim 1, wherein: The gate and the floating gate are both made of polysilicon.

7. A method for programming an erasable programmable read-only memory according to any one of claims 1 to 6, characterized in that: include: Applying a negative voltage to the N-type well region, applying a high potential to the gate and the source end of the PMOS, and connecting the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS to a low potential to achieve programming; Applying a voltage greater than the operating voltage and less than the breakdown voltage to the third N-type impurity region to achieve data writing; An operating voltage is applied to the gate and the source terminal of the NMOS, and the source terminal of the PMOS is connected to 0 to achieve the storage state of 0 and 1.

8. The programming method of an erasable programmable read-only memory according to claim 7, wherein: A negative voltage is applied to the N-type well region through a CT located on the surface of the N-type well region, a high potential is applied to the gate and the source end of the PMOS through a CT located on the surface of the gate and the source end of the PMOS, and a low potential is connected to the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS through a CT located on the surface of the source end of the NMOS, the first P-type impurity region, the third N-type impurity region and the drain end of the PMOS.

9. The programming method of an erasable programmable read-only memory according to claim 7, wherein: A voltage greater than an operating voltage and less than a breakdown voltage is applied to the third N-type impurity region through a CT located on a surface of the third N-type impurity region.

10. The programming method of an erasable programmable read-only memory according to claim 8, wherein: An operating voltage is applied to the gate and the source terminal of the NMOS through a CT located on the surface of the gate and the source terminal of the NMOS.

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