Method and system for interconnecting silicon-based impurity band blocking device and readout circuit

Abstract

The invention provides an interconnection method and system for a silicon-based barrier impurity band device and a readout circuit, and the method comprises the steps: forming a positive electrode and a negative electrode which are in good ohmic contact on the surfaces of a contact layer of the silicon-based barrier impurity band device and the readout circuit through photoetching, electron beam evaporation and stripping; depositing a silicon nitride passivation layer on the positive electrode and the negative electrode through a plasma enhanced chemical vapor deposition process; forming a positive electrode hole and a negative electrode hole in the silicon nitride passivation layer through photoetching, reactive ion beam etching and wet etching processes; and preparing indium columns on the positive electrode hole and the negative electrode hole through photoetching, electron beam evaporation and stripping. According to the method, electrode holes are etched in a passivated silicon-based impurity-blocking band detector and a readout circuit wafer by utilizing the characteristic that indium is infiltrated to gold but not infiltrated to silicon nitride, and an indium column is fused and shrunk into a ball to form a self-alignment effect in a backflow process, so that the problem of alignment errors in a flip-chip bonding process can be effectively solved, and the reliability of the flip-chip bonding process is improved. And the interconnection accuracy and reliability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of terahertz photoelectric detectors, and in particular to a method and system for interconnecting a silicon-based impurity blocking band device with a readout circuit. Background Art

[0002] Since the blocking impurity band (BIB) detector was first proposed, it has attracted widespread attention due to its high quantum efficiency, low noise, and wide response range. Among them, silicon-based blocking impurity band detectors have become one of the research hotspots. In the 5-40m spectral range, the performance of silicon-based blocking impurity band detectors has significant advantages over other types of detectors, which makes it have great application value in the field of astronomy.

[0003] With the continuous deepening of research on silicon-based impurity-blocking detectors, the array size of detectors has gradually developed from the initial 1×12 small array to the current 1024×1024, or even 2048×2048 large array structure. However, this increase in the number of pixels has also brought new problems. Due to the limited chip size, the increase in the number of pixels leads to a decrease in pixel size and a decrease in pixel spacing, which greatly increases the difficulty of interconnection between the device and the readout circuit.

[0004] In order to solve this problem, flip-chip interconnection technology came into being. Flip-chip interconnection technology is a focal plane array bonding technology generally recognized by researchers. It achieves interconnection between each pixel on the focal plane array device and the corresponding output interface of the readout circuit by pre-growing indium pillars on one or both sides of the bonding sheet, and then accurately aligning the bonding points through a flip-chip welder and then extruding and welding. However, the quality of the indium pillars as the connection point between the device and the readout circuit has become a key factor affecting the quality of the interconnection.

[0005] The surface of the indium pillars directly formed by photolithography is rough, uneven, and the height is uneven, which will seriously affect the quality of flip-chip interconnection. In addition, silicon-based impurity-barrier detectors usually work in a deep cryogenic environment of about 4K. In this environment, the irregular shape of the indium pillars will not only cause disconnection problems between the device and the readout circuit, but also cause uneven heat transfer, thereby increasing the number of dead pixels and causing uneven response, seriously affecting the performance of the interconnected chip.

[0006] A vertical table-type germanium-doped gallium terahertz focal plane detector and its preparation method are disclosed in the patent document with publication number CN116581179A, including: a high-conductivity germanium substrate, one side of which is sequentially stacked with a germanium-doped gallium absorption layer, a positive electrode contact area and a silicon nitride passivation layer, and the silicon nitride passivation layer is formed with a positive electrode hole through an opening; the other side of the high-conductivity germanium substrate is provided with a negative electrode contact area. In order to ensure the reliability of each indium point contact, the indium usually needs to be hot-melted during the flip-chip process. However, the irregularity of the indium column and the reverse soldering alignment error are very likely to cause short circuits between adjacent indium columns. This will not only reduce the effective pixel rate, but also further affect the overall performance of the detector.

[0007] Therefore, it is necessary to propose a new technical solution to improve the above technical problems. Summary of the invention

[0008] In view of the defects in the prior art, an object of the present invention is to provide a method and system for interconnecting a silicon-based barrier impurity band device with a readout circuit.

[0009] According to a method for interconnecting a silicon-based impurity blocking band device with a readout circuit provided by the present invention, the method comprises the following steps:

[0010] Step S1: forming positive and negative electrodes with good ohmic contact on the surface of the silicon-based impurity blocking band device and the contact layer of the readout circuit by photolithography, electron beam evaporation and stripping;

[0011] Step S2: depositing a silicon nitride passivation layer on the positive and negative electrodes by a plasma enhanced chemical vapor deposition process;

[0012] Step S3: opening positive and negative electrode holes on the silicon nitride passivation layer by photolithography, reactive ion beam etching and wet etching processes;

[0013] Step S4: preparing indium pillars on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping;

[0014] Step S5: interconnecting the silicon-based impurity-blocking band device and the readout circuit by flip-chip indium pillars through cold-pressing welding to form a hybrid chip;

[0015] Step S6: further optimizing the hybrid chip through a reflow process, wherein, during the reflow process, the indium pillars are melted and shrunk into balls to form a self-alignment effect by utilizing the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride.

[0016] Preferably, in the photolithography step of step S1, a negative photoresist is sprayed by spraying, and a metal electrode evaporation area window is formed through specific exposure, post-baking and development steps; in the electron beam evaporation step, a preset vacuum degree and evaporation rate are used to evaporate Ti / Au metal, wherein the thickness of Ti is 20nm and the thickness of Au is 100nm.

[0017] Preferably, in the reactive ion beam etching step of step S3, a reactive ion beam etching process is adopted to perform etching on the silicon nitride passivation layer, and the etching depth is 200 nm.

[0018] Preferably, in the photolithography step of step S4, an indium column evaporation area window is formed through preset spraying, exposure, post-baking and development steps to prepare the indium column.

[0019] Preferably, the cold pressure welding process in step S5 is performed under nitrogen protective gas, preset chamber environment temperature and pressure control.

[0020] Preferably, the reflow process in step S6 is performed under formic acid protective gas and a preset chamber ambient temperature to optimize the morphology and interconnection quality of the indium column.

[0021] The present invention also provides a silicon-based impurity blocking band device and a readout circuit interconnection system, the system comprising the following modules:

[0022] Module M1: On the surface of the silicon-based impurity-blocking band device and the readout circuit contact layer, positive and negative electrodes with good ohmic contact are formed through photolithography, electron beam evaporation and stripping;

[0023] Module M2: depositing a silicon nitride passivation layer on the positive and negative electrodes by plasma enhanced chemical vapor deposition process;

[0024] Module M3: opening positive and negative electrode holes on the silicon nitride passivation layer by photolithography, reactive ion beam etching and wet etching processes;

[0025] Module M4: preparing indium pillars on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping;

[0026] Module M5: The silicon-based impurity blocking band device and the readout circuit are interconnected by flip-chip indium pillars by cold pressure welding to form a hybrid chip;

[0027] Module M6: Further optimizing the hybrid chip through a reflow process, wherein, during the reflow process, the indium pillars are melted and shrunk into balls to form a self-alignment effect by utilizing the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride.

[0028] Preferably, in the photolithography module of the module M1, a negative photoresist is sprayed by spraying glue, and a metal electrode evaporation area window is formed by a specific exposure, post-baking and development module; in the electron beam evaporation module, a preset vacuum degree and evaporation rate are used to evaporate Ti / Au metal, wherein the thickness of Ti is 20nm and the thickness of Au is 100nm;

[0029] In the reactive ion beam etching module of the module M3, a reactive ion beam etching process is adopted to perform etching on the silicon nitride passivation layer, and the etching depth is 200 nm.

[0030] Preferably, in the photolithography module of the module M4, an indium column evaporation area window is formed by a preset glue spraying, exposure, post-baking and development module to prepare the indium column;

[0031] The cold pressure welding process in the module M5 is carried out under the control of nitrogen protective gas, preset cavity environment temperature and pressure.

[0032] Preferably, the reflow process in the module M6 is performed under formic acid protective gas and a preset chamber ambient temperature to optimize the morphology and interconnection quality of the indium column.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. The present invention utilizes the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride to etch electrode holes on the passivated silicon-based barrier impurity band detector and readout circuit chip. During the reflow process, the indium column will melt and shrink into a ball, forming a self-alignment effect, which can effectively solve the alignment error problem in the flip-chip soldering process and improve the accuracy and reliability of interconnection;

[0035] 2. The present invention adopts cold pressing instead of hot pressing. Cold pressing welding can maintain the shape stability of the indium column in the solid state, prevent the short circuit of adjacent indium columns caused by melting, and further improve the reliability and safety of interconnection;

[0036] 3. The present invention uses a reflow process to reflow these uneven indium columns into smooth and symmetrical spheres, which not only improves the morphology of the indium columns, but also improves the contact quality of the interconnection, avoids the occurrence of virtual connections, and can significantly increase the effective pixel rate and enhance the overall performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0038] Figure 1 A process flow chart of a silicon-based impurity blocking band device and a readout circuit interconnection technology proposed by the present invention;

[0039] Figure 2 It is a schematic cross-sectional structure diagram of a silicon-based impurity blocking band device and a readout circuit interconnected with each other according to the present invention;

[0040] Figure 3 It is a schematic diagram of the structure after metal is grown on the silicon-based impurity barrier band device and the contact layer of the readout circuit;

[0041] Figure 4 It is a schematic diagram of the structure after a silicon nitride passivation layer is deposited on the surface of the silicon-based impurity blocking band device and the readout circuit;

[0042] Figure 5 It is a schematic diagram of the structure after etching metal electrode holes on the surface of the passivation layer of the silicon-based impurity blocking band device and the readout circuit;

[0043] Figure 6 It is a schematic diagram of the structure after the indium pillar is grown on the surface of the silicon-based impurity barrier band device and the readout circuit;

[0044] Figure 7 This is a schematic diagram of the structure after the silicon-based impurity barrier band device and the indium column of the readout circuit are interconnected by reverse soldering.

[0045] in:

[0046] High-resistance silicon substrate 1 Readout circuit 6

[0047] Silicon-doped phosphorus buried layer 2 Metal electrode 7

[0048] Silicon-doped phosphorus absorption layer 3 Silicon nitride passivation layer 8

[0049] Silicon intrinsic barrier layer 4 Indium pillar 9

[0050] Positive contact area 5 DETAILED DESCRIPTION

[0051] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0052] Embodiment 1:

[0053] Reference Figure 1 , Figure 2 and Figure 3 According to a method for interconnecting a silicon-based impurity blocking band device with a readout circuit provided by the present invention, the method comprises the following steps:

[0054] Step S1: on the surface of the silicon-based impurity barrier band device and the readout circuit contact layer, positive and negative electrodes with good ohmic contact are formed by photolithography, electron beam evaporation and stripping; preferably, in the photolithography step, negative photoresist is sprayed by spraying, and a metal electrode evaporation area window is formed by specific exposure, post-baking and development steps; in the electron beam evaporation step, Ti / Au metal is evaporated with a preset vacuum degree and evaporation rate, wherein the thickness of Ti is 20nm and the thickness of Au is 100nm.

[0055] Step S2: Refer to Figure 4 , depositing a silicon nitride passivation layer on the positive and negative electrodes by a plasma enhanced chemical vapor deposition process;

[0056] Step S3: Refer to Figure 5 , on the silicon nitride passivation layer, positive and negative electrode holes are opened by photolithography, reactive ion beam etching and wet etching processes; preferably, in the reactive ion beam etching step, the silicon nitride passivation layer is etched by a reactive ion beam etching process, and the etching depth is 200nm.

[0057] Step S4: Refer to Figure 6 Indium columns are prepared on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping; in the photolithography step, indium column evaporation area windows are formed by preset spraying, exposure, post-baking and development steps to prepare indium columns.

[0058] Step S5: Refer to Figure 7 The silicon-based impurity-blocking band device and the readout circuit are interconnected by flip-chip indium pillars through cold pressure welding to form a hybrid chip; the cold pressure welding process is carried out under nitrogen protective gas, preset cavity environment temperature and pressure control.

[0059] Step S6: further optimizing the hybrid chip through a reflow process, wherein, during the reflow process, the indium pillars are melted and shrunk into balls to form a self-alignment effect by utilizing the indium's wetting reaction to gold and its non-wetting property to silicon nitride. The reflow process is performed under formic acid protective gas and a preset chamber ambient temperature to optimize the morphology and interconnection quality of the indium pillars.

[0060] The present invention also provides a silicon-based blocking impurity band device and a readout circuit interconnection system, which can be realized by executing the process steps of the silicon-based blocking impurity band device and a readout circuit interconnection method, that is, those skilled in the art can understand the silicon-based blocking impurity band device and a readout circuit interconnection method as a preferred implementation of the silicon-based blocking impurity band device and a readout circuit interconnection system.

[0061] Embodiment 2:

[0062] The present invention also provides a silicon-based impurity blocking band device and a readout circuit interconnection system, the system comprising the following modules:

[0063] Module M1: On the surface of the silicon-based impurity-blocking band device and the readout circuit contact layer, positive and negative electrodes with good ohmic contact are formed through photolithography, electron beam evaporation and stripping; in the photolithography module, negative photoresist is sprayed by spraying, and a metal electrode evaporation area window is formed through specific exposure, post-baking and development modules; in the electron beam evaporation module, Ti / Au metal is evaporated using a preset vacuum degree and evaporation rate, where the thickness of Ti is 20nm and the thickness of Au is 100nm;

[0064] Module M2: depositing a silicon nitride passivation layer on the positive and negative electrodes by plasma enhanced chemical vapor deposition process;

[0065] Module M3: On the silicon nitride passivation layer, positive and negative electrode holes are opened by photolithography, reactive ion beam etching and wet etching processes; in the reactive ion beam etching module, the silicon nitride passivation layer is etched by reactive ion beam etching process, and the etching depth is 200nm.

[0066] Module M4: Indium pillars are prepared on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping; in the photolithography module, indium pillar evaporation area windows are formed by preset spraying, exposure, post-baking and development modules to prepare indium pillars;

[0067] Module M5: The silicon-based impurity-blocking band device and the readout circuit are interconnected by flip-chip indium pillars by cold pressure welding to form a hybrid chip; the cold pressure welding process is carried out under nitrogen protective gas, preset chamber environment temperature and pressure control.

[0068] Module M6: Further optimize the hybrid chip through a reflow process, wherein, during the reflow process, the indium pillars are melted and shrunk into balls to form a self-alignment effect by utilizing the indium's wetting reaction to gold and its non-wetting property to silicon nitride. The reflow process is performed under formic acid protection gas and a preset chamber ambient temperature to optimize the morphology and interconnection quality of the indium pillars.

[0069] Embodiment 3:

[0070] The present invention adopts an improved reflow ball shrinking process to reduce the non-uniformity and blind element rate of interconnected chips. By utilizing the wetting reaction of indium to gold and the non-wetting characteristics of silicon nitride passivation film, electrode holes are etched on the passivated silicon-based impurity barrier band detector and readout circuit chip. During the reflow process, the indium column melts and shrinks into a ball to form a self-alignment effect, which can effectively solve the alignment error problem in the flip-chip soldering process; the problem of short circuit between adjacent indium columns in the liquid state is avoided by replacing hot pressing with cold pressing; the uneven and highly uneven indium column formed by photolithography peeling is reflowed into a smooth and symmetrical sphere through the reflow process, effectively improving the interconnection quality of the indium column.

[0071] The present invention utilizes the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride to etch electrode holes on the passivated silicon-based impurity barrier band detector and readout circuit chip. During the reflow process, the indium column melts and shrinks into a ball to form a self-alignment effect, which can effectively solve the alignment error problem in the flip-chip soldering process. The present invention replaces the hot pressing method with cold pressing to avoid the occurrence of short circuits between adjacent indium columns in the molten state. The present invention uses a reflow process to reflow the uneven and highly uneven indium column formed by photolithography peeling into a smooth and symmetrical sphere, effectively improving the interconnection quality of the indium column, avoiding the occurrence of virtual connection, and increasing the effective pixel rate.

[0072] According to the present invention, a method for interconnecting a silicon-based impurity blocking band device with a readout circuit comprises the following steps:

[0073] Step 1: On the surface of the silicon-based impurity barrier band device and the readout circuit contact layer, positive and negative electrodes with good ohmic contact are formed by photolithography, electron beam evaporation and stripping;

[0074] Step 2: depositing a silicon nitride passivation layer on the positive and negative electrodes by plasma enhanced chemical vapor deposition process;

[0075] Step 3: Opening positive and negative electrode holes on the silicon nitride passivation layer by photolithography, reactive ion beam etching and wet etching processes;

[0076] Step 4: preparing indium pillars on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping;

[0077] Step 5: The silicon-based impurity blocking band device and the readout circuit are interconnected by flip-chip indium pillars by cold pressure welding to form a hybrid chip;

[0078] Step 6: Further optimize the hybrid chip through a reflow process.

[0079] Preferably, in the photolithography step of step 1, negative resist is sprayed on the surface of the silicon-based impurity blocking band device and the readout circuit by spraying, exposed for 5 seconds, post-baked at 110° C. for 3 minutes, and developed for 50 seconds to form a metal electrode evaporation area window.

[0080] Preferably, in the electron beam evaporation step of step 1, the metal is evaporated by electron beam evaporation process, the vacuum degree is 5×10-4 Pa, the evaporation rate is 1 nm / s, the evaporated material is Ti / Au, and the thickness is 20 nm / 100 nm respectively.

[0081] Preferably, in the stripping step of step 1, after standing in NMP for 24 hours, the sample is washed in an 80° C. water bath for 10 minutes, ultrasonically cleaned in acetone and isopropanol for 15 minutes respectively, rinsed with deionized water, and dried with nitrogen.

[0082] Preferably, in the photolithography step of step 3, negative resist Rol7133 is sprayed by spraying with a thickness of 3 um, exposed for 5 seconds, post-baked at 110° C. for 3 minutes, and developed for 50 seconds to form a reactive ion beam etching area window.

[0083] Preferably, in the reactive ion beam etching step of step 3, a reactive ion beam etching process is adopted to perform etching on the silicon nitride passivation layer with an etching depth of 200 nm.

[0084] Preferably, in the photolithography step of step 4, negative resist Rol7133 is sprayed by spraying with a thickness of 10 um, exposed for 7 seconds, post-baked at 110° C. for 3 minutes, and developed for 60 seconds to form an indium column evaporation area window.

[0085] Preferably, each positive electrode contact layer formed by the ion implantation is a square with a side length of 30 μm, each metal electrode is a square with a side length of 25 μm, the material is titanium (Ti) / gold (Au), the thickness of titanium is 20 nm, the thickness of gold is 100 nm, the thickness of the silicon nitride passivation layer is 200 nm, the positive and negative electrode openings are circular with a diameter of 15 μm, and the diameter of the indium column after stripping is 20 μm and the thickness is 7 μm.

[0086] Preferably, in step 5, the protective gas for the flip-chip interconnection process is nitrogen, the chamber ambient temperature is 60° C., the pressure is controlled at 4 Kg, and the duration is 430 s.

[0087] Preferably, in the reflux process in step 6, the protective gas during the reflux ball shrinking process is formic acid, the chamber ambient temperature is 190° C., and the duration is 3 minutes.

[0088] The present invention utilizes the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride to etch electrode holes on the passivated silicon-based impurity barrier band detector and the readout circuit chip; during the reflow process, the indium column melts and shrinks into a ball to form a self-alignment effect, which can effectively solve the alignment error problem in the flip-chip soldering process; the cold pressing method is used to replace the hot pressing method to avoid the occurrence of short circuits between adjacent indium columns in a molten state; the uneven and highly non-uniform indium columns formed by photolithography peeling are reflowed into smooth and symmetrical spheres through the reflow process, which effectively improves the interconnection quality of the indium columns, avoids the occurrence of virtual connections, and increases the effective pixel rate.

[0089] The process steps of the silicon-based impurity blocking band device and the readout circuit interconnection technology provided by the present invention are as follows:

[0090] S1, first photolithography: spray negative resist Rol7133 on the surface of silicon-based impurity blocking band device and readout circuit by spraying, with a thickness of 3um, expose for 5s, bake at 110℃ for 3min, and develop for 50s to form a window of metal electrode evaporation area;

[0091] S2, evaporation of metal titanium / gold: metal was evaporated using electron beam evaporation technology, the vacuum degree was 5×10-4Pa, the evaporation rate was 1nm / s, the evaporation material was Ti / Au, and the thickness was 20nm / 100nm respectively;

[0092] S3, stripping: After standing in NMP for 24 hours, the mixture was then washed in a water bath at 80°C for 10 minutes, ultrasonically cleaned in acetone and isopropanol for 15 minutes respectively, rinsed with deionized water, and dried with nitrogen;

[0093] S4, growth of silicon nitride passivation layer: depositing a silicon nitride passivation layer with a thickness of 200 nm by plasma enhanced chemical vapor deposition process;

[0094] S5, second photolithography: spray negative resist Rol7133 by spraying, with a thickness of 3 μm, expose for 5 seconds, bake at 110°C for 3 minutes, and develop for 50 seconds to form a window in the reactive ion beam etching area;

[0095] S6, etching holes: using reactive ion beam etching process, etching is performed on the silicon nitride passivation layer with an etching depth of 200 nm;

[0096] S7, the third photolithography: spray negative resist Rol7133 by spraying, the thickness of the resist is 10um, the exposure is 7s, the post-baking is 3min at 110℃, and the development is 60s to form the indium column evaporation area window;

[0097] S8, evaporation of metal indium: the metal is evaporated by electron beam evaporation process, the vacuum degree is 5×10-5Pa, the evaporation rate is 200nm / min, the evaporated metal is indium, and the thickness is 7um;

[0098] S9, stripping: After standing in NMP for 48 hours, wash in 80°C water bath for 15 minutes, ultrasonically clean in acetone and isopropanol for 15 minutes, rinse with deionized water, and blow dry with nitrogen;

[0099] S10, flip-chip interconnection: the device and the readout circuit sample are placed face to face in a flip-chip soldering equipment. The protective gas during the flip-chip interconnection process is nitrogen, the chamber ambient temperature is 60°C, the pressure is controlled at 4Kg, and the duration is 430s;

[0100] S11, reflux shrinkage: the flip-chip interconnected sample is placed in a reflow oven for reflux shrinkage, the protective gas is formic acid, the chamber ambient temperature is 190°C, and the duration is 3 minutes.

[0101] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1 and Embodiment 2.

[0102] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0103] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for interconnecting a silicon-based impurity barrier band device with a readout circuit, characterized in that: The method comprises the following steps: Step S1: forming positive and negative electrodes with good ohmic contact on the surface of the silicon-based impurity blocking band device and the contact layer of the readout circuit by photolithography, electron beam evaporation and stripping; Step S2: depositing a silicon nitride passivation layer on the positive and negative electrodes by a plasma enhanced chemical vapor deposition process; Step S3: opening positive and negative electrode holes on the silicon nitride passivation layer by photolithography, reactive ion beam etching and wet etching processes; Step S4: preparing indium pillars on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping; Step S5: interconnecting the silicon-based impurity-blocking band device and the readout circuit by flip-chip indium pillars through cold-pressing welding to form a hybrid chip; Step S6: further optimizing the hybrid chip through a reflow process, wherein, during the reflow process, the indium pillars are melted and shrunk into balls to form a self-alignment effect by utilizing the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride.

2. The method for interconnecting a silicon-based impurity blocking band device and a readout circuit according to claim 1, characterized in that: In the photolithography step of step S1, negative photoresist is sprayed by spraying, and a metal electrode evaporation area window is formed through specific exposure, post-baking and development steps; in the electron beam evaporation step, Ti / Au metal is evaporated using a preset vacuum degree and evaporation rate, wherein the thickness of Ti is 20nm and the thickness of Au is 100nm.

3. The method for interconnecting a silicon-based impurity blocking band device and a readout circuit according to claim 1, characterized in that: In the reactive ion beam etching step of step S3, the silicon nitride passivation layer is etched using a reactive ion beam etching process, and the etching depth is 200 nm.

4. The method for interconnecting a silicon-based impurity blocking band device and a readout circuit according to claim 1, characterized in that: In the photolithography step of step S4, the indium column evaporation area window is formed through the preset spraying, exposure, post-baking and development steps to prepare the indium column.

5. The method for interconnecting a silicon-based impurity blocking band device and a readout circuit according to claim 1, characterized in that: The cold pressure welding process in step S5 is performed under the control of nitrogen protective gas, preset chamber environment temperature and pressure.

6. The method for interconnecting a silicon-based impurity blocking band device and a readout circuit according to claim 1, characterized in that: The reflow process in step S6 is performed under formic acid protective gas and a preset chamber ambient temperature to optimize the morphology and interconnection quality of the indium column.

7. A silicon-based barrier impurity band device and readout circuit interconnection system, characterized in that: The system includes the following modules: Module M1: On the surface of the silicon-based impurity-blocking band device and the readout circuit contact layer, positive and negative electrodes with good ohmic contact are formed through photolithography, electron beam evaporation and stripping; Module M2: depositing a silicon nitride passivation layer on the positive and negative electrodes by plasma enhanced chemical vapor deposition process; Module M3: opening positive and negative electrode holes on the silicon nitride passivation layer by photolithography, reactive ion beam etching and wet etching processes; Module M4: preparing indium pillars on the positive and negative electrode holes by photolithography, electron beam evaporation and stripping; Module M5: The silicon-based impurity blocking band device and the readout circuit are interconnected by flip-chip indium pillars by cold pressure welding to form a hybrid chip; Module M6: Further optimizing the hybrid chip through a reflow process, wherein, during the reflow process, the indium pillars are melted and shrunk into balls to form a self-alignment effect by utilizing the wetting reaction of indium to gold and the non-wetting property of indium to silicon nitride.

8. The silicon-based barrier impurity band device and readout circuit interconnection system according to claim 7, characterized in that: In the photolithography module of the module M1, a negative photoresist is sprayed by spraying, and a metal electrode evaporation area window is formed by a specific exposure, post-baking and development module; in the electron beam evaporation module, a preset vacuum degree and evaporation rate are used to evaporate Ti / Au metal, wherein the thickness of Ti is 20nm and the thickness of Au is 100nm; In the reactive ion beam etching module of the module M3, a reactive ion beam etching process is adopted to perform etching on the silicon nitride passivation layer, and the etching depth is 200 nm.

9. The silicon-based barrier impurity band device and readout circuit interconnection system according to claim 7, characterized in that: In the photolithography module of the module M4, an indium column evaporation area window is formed through preset glue spraying, exposure, post-baking and development modules to prepare the indium column; The cold pressure welding process in the module M5 is carried out under the control of nitrogen protective gas, preset cavity environment temperature and pressure.

10. The silicon-based barrier impurity band device and readout circuit interconnection system according to claim 7, characterized in that: The reflow process in the module M6 is performed under formic acid protective gas and a preset chamber ambient temperature to optimize the morphology and interconnection quality of the indium column.

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